static int __init swarm_pata_init(void)
{
u8 __iomem *base;
phys_t offset, size;
struct resource *r;
if (!SIBYTE_HAVE_IDE)
return -ENODEV;
base = ioremap(A_IO_EXT_BASE, 0x800);
offset = __raw_readq(base + R_IO_EXT_REG(R_IO_EXT_START_ADDR, IDE_CS));
size = __raw_readq(base + R_IO_EXT_REG(R_IO_EXT_MULT_SIZE, IDE_CS));
iounmap(base);
offset = G_IO_START_ADDR(offset) << S_IO_ADDRBASE;
size = (G_IO_MULT_SIZE(size) + 1) << S_IO_REGSIZE;
if (offset < A_PHYS_GENBUS || offset >= A_PHYS_GENBUS_END) {
pr_info(DRV_NAME ": PATA interface at GenBus disabled\n");
return -EBUSY;
}
pr_info(DRV_NAME ": PATA interface at GenBus slot %i\n", IDE_CS);
r = swarm_pata_resource;
r[0].start = offset + (SWARM_IDE_BASE << SWARM_IDE_SHIFT);
r[0].end = offset + ((SWARM_IDE_BASE + 8) << SWARM_IDE_SHIFT) - 1;
r[1].start = offset + (SWARM_IDE_CTRL << SWARM_IDE_SHIFT);
r[1].end = offset + ((SWARM_IDE_CTRL + 1) << SWARM_IDE_SHIFT) - 1;
return platform_device_register(&swarm_pata_device);
}
/*
* swarm_ide_probe - if the board header indicates the existence of
* Generic Bus IDE, allocate a HWIF for it.
*/
static int __devinit swarm_ide_probe(struct device *dev)
{
ide_hwif_t *hwif;
u8 __iomem *base;
phys_t offset, size;
int i;
if (!SIBYTE_HAVE_IDE)
return -ENODEV;
/* Find an empty slot. */
for (i = 0; i < MAX_HWIFS; i++)
if (!ide_hwifs[i].io_ports[IDE_DATA_OFFSET])
break;
if (i >= MAX_HWIFS) {
printk(KERN_ERR DRV_NAME ": no free slot for interface\n");
return -ENOMEM;
}
hwif = ide_hwifs + i;
base = ioremap(A_IO_EXT_BASE, 0x800);
offset = __raw_readq(base + R_IO_EXT_REG(R_IO_EXT_START_ADDR, IDE_CS));
size = __raw_readq(base + R_IO_EXT_REG(R_IO_EXT_MULT_SIZE, IDE_CS));
iounmap(base);
offset = G_IO_START_ADDR(offset) << S_IO_ADDRBASE;
size = (G_IO_MULT_SIZE(size) + 1) << S_IO_REGSIZE;
if (offset < A_PHYS_GENBUS || offset >= A_PHYS_GENBUS_END) {
printk(KERN_INFO DRV_NAME
": IDE interface at GenBus disabled\n");
return -EBUSY;
}
printk(KERN_INFO DRV_NAME ": IDE interface at GenBus slot %i\n",
IDE_CS);
swarm_ide_resource.start = offset;
swarm_ide_resource.end = offset + size - 1;
if (request_resource(&iomem_resource, &swarm_ide_resource)) {
printk(KERN_ERR DRV_NAME
": can't request I/O memory resource\n");
return -EBUSY;
}
base = ioremap(offset, size);
/* Setup MMIO ops. */
default_hwif_mmiops(hwif);
/* Prevent resource map manipulation. */
hwif->mmio = 2;
hwif->noprobe = 0;
for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++)
hwif->hw.io_ports[i] =
(unsigned long)(base + ((0x1f0 + i) << 5));
hwif->hw.io_ports[IDE_CONTROL_OFFSET] =
(unsigned long)(base + (0x3f6 << 5));
hwif->hw.irq = K_INT_GB_IDE;
memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->io_ports));
hwif->irq = hwif->hw.irq;
dev_set_drvdata(dev, hwif);
return 0;
}
/*
* swarm_ide_probe - if the board header indicates the existence of
* Generic Bus IDE, allocate a HWIF for it.
*/
static int __devinit swarm_ide_probe(struct device *dev)
{
ide_hwif_t *hwif;
u8 __iomem *base;
phys_t offset, size;
hw_regs_t hw;
int i;
u8 idx[] = { 0xff, 0xff, 0xff, 0xff };
if (!SIBYTE_HAVE_IDE)
return -ENODEV;
hwif = ide_find_port();
if (hwif == NULL) {
printk(KERN_ERR DRV_NAME ": no free slot for interface\n");
return -ENOMEM;
}
base = ioremap(A_IO_EXT_BASE, 0x800);
offset = __raw_readq(base + R_IO_EXT_REG(R_IO_EXT_START_ADDR, IDE_CS));
size = __raw_readq(base + R_IO_EXT_REG(R_IO_EXT_MULT_SIZE, IDE_CS));
iounmap(base);
offset = G_IO_START_ADDR(offset) << S_IO_ADDRBASE;
size = (G_IO_MULT_SIZE(size) + 1) << S_IO_REGSIZE;
if (offset < A_PHYS_GENBUS || offset >= A_PHYS_GENBUS_END) {
printk(KERN_INFO DRV_NAME
": IDE interface at GenBus disabled\n");
return -EBUSY;
}
printk(KERN_INFO DRV_NAME ": IDE interface at GenBus slot %i\n",
IDE_CS);
swarm_ide_resource.start = offset;
swarm_ide_resource.end = offset + size - 1;
if (request_resource(&iomem_resource, &swarm_ide_resource)) {
printk(KERN_ERR DRV_NAME
": can't request I/O memory resource\n");
return -EBUSY;
}
base = ioremap(offset, size);
/* Setup MMIO ops. */
hwif->host_flags = IDE_HFLAG_MMIO;
default_hwif_mmiops(hwif);
for (i = 0; i <= 7; i++)
hw.io_ports_array[i] =
(unsigned long)(base + ((0x1f0 + i) << 5));
hw.io_ports.ctl_addr =
(unsigned long)(base + (0x3f6 << 5));
hw.irq = K_INT_GB_IDE;
hw.chipset = ide_generic;
ide_init_port_hw(hwif, &hw);
idx[0] = hwif->index;
ide_device_add(idx, NULL);
dev_set_drvdata(dev, hwif);
return 0;
}
