/**
* FchInitResetImc - Config Imc controller during Power-On
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitResetImc (
IN VOID *FchDataPtr
)
{
FCH_RESET_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
UINT8 PortStatusByte;
LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
GetChipSysMode (&PortStatusByte, StdHeader);
if ( ((PortStatusByte & ChipSysEcEnable) == 0x00) ) {
//
// EC is disabled by jumper setting or board config
//
RwPci (((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGA4), AccessWidth16, 0xFFFE, BIT0, StdHeader);
// Set PMIO_C4[5] to 1 for cold reset
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC4, AccessWidth8, 0xDF, 0x20);
} else {
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC4, AccessWidth8, 0xF7, 0x08);
FchInitResetEc (FchDataPtr);
}
}
/**
* SoftwareDisableImc - Software disable IMC strap
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
SoftwareDisableImc (
IN VOID *FchDataPtr
)
{
UINT8 ValueByte;
UINT8 PortStatusByte;
UINT32 AbValue;
UINT32 ABStrapOverrideReg;
AMD_CONFIG_PARAMS *StdHeader;
StdHeader = ((FCH_DATA_BLOCK *) FchDataPtr)->StdHeader;
GetChipSysMode (&PortStatusByte, StdHeader);
RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGC8 + 3, AccessWidth8, 0x7F, BIT7, StdHeader);
ReadPmio (FCH_PMIOA_REGBF, AccessWidth8, &ValueByte, StdHeader);
ReadMem ((ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG80), AccessWidth32, &AbValue);
ABStrapOverrideReg = AbValue;
ABStrapOverrideReg &= ~BIT2; // bit2=0 EcEnableStrap
WriteMem ((ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG84), AccessWidth32, &ABStrapOverrideReg);
ReadPmio (FCH_PMIOA_REGD7, AccessWidth8, &ValueByte, StdHeader);
ValueByte |= BIT1; // Set GenImcClkEn to 1
WritePmio (FCH_PMIOA_REGD7, AccessWidth8, &ValueByte, StdHeader);
ValueByte = 06;
LibAmdIoWrite (AccessWidth8, 0xcf9, &ValueByte, StdHeader);
FchStall (0xffffffff, StdHeader);
}
/**
* IsImcEnabled - Is IMC Enabled
* @retval TRUE for IMC Enabled; FALSE for IMC Disabled
*/
BOOLEAN
IsImcEnabled (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 dbSysConfig;
GetChipSysMode (&dbSysConfig, StdHeader);
if (dbSysConfig & ChipSysEcEnable) {
return TRUE;
} else {
return FALSE;
}
}
/**
* FchInitEnvImc - Config Imc controller before PCI emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitEnvImc (
IN VOID *FchDataPtr
)
{
UINT8 PortStatusByte;
FCH_DATA_BLOCK *LocalCfgPtr;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
GetChipSysMode (&PortStatusByte, LocalCfgPtr->StdHeader);
//
// Software IMC enable
//
if (((LocalCfgPtr->Imc.ImcEnableOverWrite == 1) && ((PortStatusByte & ChipSysEcEnable) == 0)) || ((LocalCfgPtr->Imc.ImcEnableOverWrite == 2) && ((PortStatusByte & ChipSysEcEnable) == ChipSysEcEnable))) {
if (ValidateImcFirmware (LocalCfgPtr)) {
SoftwareToggleImcStrapping (LocalCfgPtr);
}
}
FchInitEnvEc (LocalCfgPtr);
}
/**
* ProgramFchEnvSpreadSpectrum - Config SpreadSpectrum before
* PCI emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
ProgramFchEnvSpreadSpectrum (
IN VOID *FchDataPtr
)
{
UINT8 PortStatus;
UINT8 FchSpreadSpectrum;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
FchSpreadSpectrum = LocalCfgPtr->HwAcpi.SpreadSpectrum;
if ( FchSpreadSpectrum ) {
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG08, AccessWidth8, 0xFE, 0x00);
if ( LocalCfgPtr->HwAcpi.SpreadSpectrumOptions == 0 ) {
/// -0.362%
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG18 + 1, AccessWidth8, 0xF0, 0x01);
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG14 + 2, AccessWidth16, 0, 0xCF5C);
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG14, AccessWidth16, 0, 0x0137);
}
if ( LocalCfgPtr->HwAcpi.SpreadSpectrumOptions == 1 ) {
/// -0.375%
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG18 + 1, AccessWidth8, 0xF0, 0x01);
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG14 + 2, AccessWidth16, 0, 0xE000);
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG14, AccessWidth16, 0, 0x0142);
}
if ( LocalCfgPtr->HwAcpi.SpreadSpectrumOptions == 2 ) {
/// -0.4%
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG18 + 1, AccessWidth8, 0xF0, 0x02);
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG14 + 2, AccessWidth16, 0, 0);
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG14, AccessWidth16, 0, 0x0158);
}
if ( LocalCfgPtr->HwAcpi.SpreadSpectrumOptions == 3 ) {
/// -0.425%
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG18 + 1, AccessWidth8, 0xF0, 0x02);
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG14 + 2, AccessWidth16, 0, 0x1FFF);
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG14, AccessWidth16, 0, 0x016D);
}
if ( LocalCfgPtr->HwAcpi.SpreadSpectrumOptions == 4 ) {
/// -0.45%
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG18 + 1, AccessWidth8, 0xF0, 0x02);
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG14 + 2, AccessWidth16, 0, 0x4000);
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG14, AccessWidth16, 0, 0x0183);
}
if ( LocalCfgPtr->HwAcpi.SpreadSpectrumOptions == 5 ) {
/// -0.475%
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG18 + 1, AccessWidth8, 0xF0, 0x02);
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG14 + 2, AccessWidth16, 0, 0x6000);
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG14, AccessWidth16, 0, 0x0198);
}
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG08, AccessWidth8, 0xFE, BIT0);
} else {
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG08, AccessWidth8, 0xFE, 0x00);
}
//
// PLL 100Mhz Reference Clock Buffer setting for internal clock generator mode (BIT5)
// OSC Clock setting for internal clock generator mode (BIT6)
//
GetChipSysMode (&PortStatus, StdHeader);
if ( ((PortStatus & ChipSysIntClkGen) == ChipSysIntClkGen) ) {
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG04 + 1, AccessWidth8, (UINT32)~(BIT5 + BIT6), BIT5 + BIT6);
}
}
