const EDA_RECT TRACK::GetBoundingBox() const
{
// end of track is round, this is its radius, rounded up
int radius = ( m_Width + 1 ) / 2;
int ymax;
int xmax;
int ymin;
int xmin;
if( Type() == PCB_VIA_T )
{
// Because vias are sometimes drawn larger than their m_Width would
// provide, erasing them using a dirty rect must also compensate for this
// possibility (that the via is larger on screen than its m_Width would provide).
// Because it is cheap to return a larger BoundingBox, do it so that
// the via gets erased properly. Do not divide width by 2 for this reason.
radius = m_Width;
ymax = m_Start.y;
xmax = m_Start.x;
ymin = m_Start.y;
xmin = m_Start.x;
}
else
{
radius = ( m_Width + 1 ) / 2;
ymax = std::max( m_Start.y, m_End.y );
xmax = std::max( m_Start.x, m_End.x );
ymin = std::min( m_Start.y, m_End.y );
xmin = std::min( m_Start.x, m_End.x );
}
if( ShowClearance( this ) )
{
// + 1 is for the clearance line itself.
radius += GetClearance() + 1;
}
ymax += radius;
xmax += radius;
ymin -= radius;
xmin -= radius;
// return a rectangle which is [pos,dim) in nature. therefore the +1
EDA_RECT ret( wxPoint( xmin, ymin ), wxSize( xmax - xmin + 1, ymax - ymin + 1 ) );
return ret;
}
void NETCLASS::Format( OUTPUTFORMATTER* aFormatter, int aNestLevel, int aControlBits ) const
throw( IO_ERROR )
{
aFormatter->Print( aNestLevel, "(net_class %s %s\n",
aFormatter->Quotew( GetName() ).c_str(),
aFormatter->Quotew( GetDescription() ).c_str() );
aFormatter->Print( aNestLevel+1, "(clearance %s)\n", FMT_IU( GetClearance() ).c_str() );
aFormatter->Print( aNestLevel+1, "(trace_width %s)\n", FMT_IU( GetTrackWidth() ).c_str() );
aFormatter->Print( aNestLevel+1, "(via_dia %s)\n", FMT_IU( GetViaDiameter() ).c_str() );
aFormatter->Print( aNestLevel+1, "(via_drill %s)\n", FMT_IU( GetViaDrill() ).c_str() );
aFormatter->Print( aNestLevel+1, "(uvia_dia %s)\n", FMT_IU( GetuViaDiameter() ).c_str() );
aFormatter->Print( aNestLevel+1, "(uvia_drill %s)\n", FMT_IU( GetuViaDrill() ).c_str() );
for( NETCLASS::const_iterator it = begin(); it != end(); ++it )
aFormatter->Print( aNestLevel+1, "(add_net %s)\n", aFormatter->Quotew( *it ).c_str() );
aFormatter->Print( aNestLevel, ")\n\n" );
}
void ZONE_CONTAINER::buildFeatureHoleList( BOARD* aPcb, SHAPE_POLY_SET& aFeatures )
{
int segsPerCircle;
double correctionFactor;
// Set the number of segments in arc approximations
if( m_ArcToSegmentsCount == ARC_APPROX_SEGMENTS_COUNT_HIGHT_DEF )
segsPerCircle = ARC_APPROX_SEGMENTS_COUNT_HIGHT_DEF;
else
segsPerCircle = ARC_APPROX_SEGMENTS_COUNT_LOW_DEF;
/* calculates the coeff to compensate radius reduction of holes clearance
* due to the segment approx.
* For a circle the min radius is radius * cos( 2PI / s_CircleToSegmentsCount / 2)
* s_Correction is 1 /cos( PI/s_CircleToSegmentsCount )
*/
correctionFactor = 1.0 / cos( M_PI / (double) segsPerCircle );
aFeatures.RemoveAllContours();
int outline_half_thickness = m_ZoneMinThickness / 2;
int zone_clearance = std::max( m_ZoneClearance, GetClearance() );
zone_clearance += outline_half_thickness;
/* store holes (i.e. tracks and pads areas as polygons outlines)
* in a polygon list
*/
/* items ouside the zone bounding box are skipped
* the bounding box is the zone bounding box + the biggest clearance found in Netclass list
*/
EDA_RECT item_boundingbox;
EDA_RECT zone_boundingbox = GetBoundingBox();
int biggest_clearance = aPcb->GetDesignSettings().GetBiggestClearanceValue();
biggest_clearance = std::max( biggest_clearance, zone_clearance );
zone_boundingbox.Inflate( biggest_clearance );
/*
* First : Add pads. Note: pads having the same net as zone are left in zone.
* Thermal shapes will be created later if necessary
*/
int item_clearance;
/* Use a dummy pad to calculate hole clerance when a pad is not on all copper layers
* and this pad has a hole
* This dummy pad has the size and shape of the hole
* Therefore, this dummy pad is a circle or an oval.
* A pad must have a parent because some functions expect a non null parent
* to find the parent board, and some other data
*/
MODULE dummymodule( aPcb ); // Creates a dummy parent
D_PAD dummypad( &dummymodule );
for( MODULE* module = aPcb->m_Modules; module; module = module->Next() )
{
D_PAD* nextpad;
for( D_PAD* pad = module->Pads(); pad != NULL; pad = nextpad )
{
nextpad = pad->Next(); // pad pointer can be modified by next code, so
// calculate the next pad here
if( !pad->IsOnLayer( GetLayer() ) )
{
/* Test for pads that are on top or bottom only and have a hole.
* There are curious pads but they can be used for some components that are
* inside the board (in fact inside the hole. Some photo diodes and Leds are
* like this)
*/
if( pad->GetDrillSize().x == 0 && pad->GetDrillSize().y == 0 )
continue;
// Use a dummy pad to calculate a hole shape that have the same dimension as
// the pad hole
dummypad.SetSize( pad->GetDrillSize() );
dummypad.SetOrientation( pad->GetOrientation() );
dummypad.SetShape( pad->GetDrillShape() == PAD_DRILL_SHAPE_OBLONG ?
PAD_SHAPE_OVAL : PAD_SHAPE_CIRCLE );
dummypad.SetPosition( pad->GetPosition() );
pad = &dummypad;
}
// Note: netcode <=0 means not connected item
if( ( pad->GetNetCode() != GetNetCode() ) || ( pad->GetNetCode() <= 0 ) )
{
item_clearance = pad->GetClearance() + outline_half_thickness;
item_boundingbox = pad->GetBoundingBox();
item_boundingbox.Inflate( item_clearance );
if( item_boundingbox.Intersects( zone_boundingbox ) )
{
int clearance = std::max( zone_clearance, item_clearance );
pad->TransformShapeWithClearanceToPolygon( aFeatures,
clearance,
segsPerCircle,
correctionFactor );
}
continue;
}
// Pads are removed from zone if the setup is PAD_ZONE_CONN_NONE
if( GetPadConnection( pad ) == PAD_ZONE_CONN_NONE )
{
int gap = zone_clearance;
int thermalGap = GetThermalReliefGap( pad );
gap = std::max( gap, thermalGap );
item_boundingbox = pad->GetBoundingBox();
item_boundingbox.Inflate( gap );
if( item_boundingbox.Intersects( zone_boundingbox ) )
{
pad->TransformShapeWithClearanceToPolygon( aFeatures,
gap,
segsPerCircle,
correctionFactor );
}
}
}
}
/* Add holes (i.e. tracks and vias areas as polygons outlines)
* in cornerBufferPolysToSubstract
*/
for( TRACK* track = aPcb->m_Track; track; track = track->Next() )
{
if( !track->IsOnLayer( GetLayer() ) )
continue;
if( track->GetNetCode() == GetNetCode() && (GetNetCode() != 0) )
continue;
item_clearance = track->GetClearance() + outline_half_thickness;
item_boundingbox = track->GetBoundingBox();
if( item_boundingbox.Intersects( zone_boundingbox ) )
{
int clearance = std::max( zone_clearance, item_clearance );
track->TransformShapeWithClearanceToPolygon( aFeatures,
clearance,
segsPerCircle,
correctionFactor );
}
}
/* Add module edge items that are on copper layers
* Pcbnew allows these items to be on copper layers in microwave applictions
* This is a bad thing, but must be handled here, until a better way is found
*/
for( MODULE* module = aPcb->m_Modules; module; module = module->Next() )
{
for( BOARD_ITEM* item = module->GraphicalItems(); item; item = item->Next() )
{
if( !item->IsOnLayer( GetLayer() ) && !item->IsOnLayer( Edge_Cuts ) )
continue;
if( item->Type() != PCB_MODULE_EDGE_T )
continue;
item_boundingbox = item->GetBoundingBox();
if( item_boundingbox.Intersects( zone_boundingbox ) )
{
( (EDGE_MODULE*) item )->TransformShapeWithClearanceToPolygon(
aFeatures, zone_clearance,
segsPerCircle, correctionFactor );
}
}
}
// Add graphic items (copper texts) and board edges
for( BOARD_ITEM* item = aPcb->m_Drawings; item; item = item->Next() )
{
if( item->GetLayer() != GetLayer() && item->GetLayer() != Edge_Cuts )
continue;
switch( item->Type() )
{
case PCB_LINE_T:
( (DRAWSEGMENT*) item )->TransformShapeWithClearanceToPolygon(
aFeatures,
zone_clearance, segsPerCircle, correctionFactor );
break;
case PCB_TEXT_T:
( (TEXTE_PCB*) item )->TransformBoundingBoxWithClearanceToPolygon(
aFeatures, zone_clearance );
break;
default:
break;
}
}
// Add zones outlines having an higher priority and keepout
for( int ii = 0; ii < GetBoard()->GetAreaCount(); ii++ )
{
ZONE_CONTAINER* zone = GetBoard()->GetArea( ii );
if( zone->GetLayer() != GetLayer() )
continue;
if( !zone->GetIsKeepout() && zone->GetPriority() <= GetPriority() )
continue;
if( zone->GetIsKeepout() && ! zone->GetDoNotAllowCopperPour() )
continue;
// A highter priority zone or keepout area is found: remove this area
item_boundingbox = zone->GetBoundingBox();
if( !item_boundingbox.Intersects( zone_boundingbox ) )
continue;
// Add the zone outline area.
// However if the zone has the same net as the current zone,
// do not add any clearance.
// the zone will be connected to the current zone, but filled areas
// will use different parameters (clearance, thermal shapes )
bool same_net = GetNetCode() == zone->GetNetCode();
bool use_net_clearance = true;
int min_clearance = zone_clearance;
// Do not forget to make room to draw the thick outlines
// of the hole created by the area of the zone to remove
int holeclearance = zone->GetClearance() + outline_half_thickness;
// The final clearance is obviously the max value of each zone clearance
min_clearance = std::max( min_clearance, holeclearance );
if( zone->GetIsKeepout() || same_net )
{
// Just take in account the fact the outline has a thickness, so
// the actual area to substract is inflated to take in account this fact
min_clearance = outline_half_thickness;
use_net_clearance = false;
}
zone->TransformOutlinesShapeWithClearanceToPolygon(
aFeatures,
min_clearance, use_net_clearance );
}
// Remove thermal symbols
for( MODULE* module = aPcb->m_Modules; module; module = module->Next() )
{
for( D_PAD* pad = module->Pads(); pad != NULL; pad = pad->Next() )
{
// Rejects non-standard pads with tht-only thermal reliefs
if( GetPadConnection( pad ) == PAD_ZONE_CONN_THT_THERMAL
&& pad->GetAttribute() != PAD_ATTRIB_STANDARD )
continue;
if( GetPadConnection( pad ) != PAD_ZONE_CONN_THERMAL
&& GetPadConnection( pad ) != PAD_ZONE_CONN_THT_THERMAL )
continue;
if( !pad->IsOnLayer( GetLayer() ) )
continue;
if( pad->GetNetCode() != GetNetCode() )
continue;
item_boundingbox = pad->GetBoundingBox();
int thermalGap = GetThermalReliefGap( pad );
item_boundingbox.Inflate( thermalGap, thermalGap );
if( item_boundingbox.Intersects( zone_boundingbox ) )
{
CreateThermalReliefPadPolygon( aFeatures,
*pad, thermalGap,
GetThermalReliefCopperBridge( pad ),
m_ZoneMinThickness,
segsPerCircle,
correctionFactor, s_thermalRot );
}
}
}
}
void VIA::Draw( EDA_DRAW_PANEL* panel, wxDC* aDC, GR_DRAWMODE aDrawMode,
const wxPoint& aOffset )
{
int radius;
LAYER_NUM curr_layer = ( (PCB_SCREEN*) panel->GetScreen() )->m_Active_Layer;
int fillvia = 0;
PCB_BASE_FRAME* frame = (PCB_BASE_FRAME*) panel->GetParent();
PCB_SCREEN* screen = frame->GetScreen();
if( frame->m_DisplayViaFill == FILLED )
fillvia = 1;
GRSetDrawMode( aDC, aDrawMode );
BOARD * brd = GetBoard( );
EDA_COLOR_T color = brd->GetVisibleElementColor(VIAS_VISIBLE + GetViaType());
if( brd->IsElementVisible( PCB_VISIBLE(VIAS_VISIBLE + GetViaType()) ) == false
&& ( color & HIGHLIGHT_FLAG ) != HIGHLIGHT_FLAG )
return;
if( DisplayOpt.ContrastModeDisplay )
{
if( !IsOnLayer( curr_layer ) )
ColorTurnToDarkDarkGray( &color );
}
if( aDrawMode & GR_HIGHLIGHT )
ColorChangeHighlightFlag( &color, !(aDrawMode & GR_AND) );
ColorApplyHighlightFlag( &color );
SetAlpha( &color, 150 );
radius = m_Width >> 1;
// for small via size on screen (radius < 4 pixels) draw a simplified shape
int radius_in_pixels = aDC->LogicalToDeviceXRel( radius );
bool fast_draw = false;
// Vias are drawn as a filled circle or a double circle. The hole will be drawn later
int drill_radius = GetDrillValue() / 2;
int inner_radius = radius - aDC->DeviceToLogicalXRel( 2 );
if( radius_in_pixels < MIN_VIA_DRAW_SIZE )
{
fast_draw = true;
fillvia = false;
}
if( fillvia )
{
GRFilledCircle( panel->GetClipBox(), aDC, m_Start + aOffset, radius, color );
}
else
{
GRCircle( panel->GetClipBox(), aDC, m_Start + aOffset, radius, 0, color );
if ( fast_draw )
return;
GRCircle( panel->GetClipBox(), aDC, m_Start + aOffset, inner_radius, 0, color );
}
// Draw the via hole if the display option allows it
if( DisplayOpt.m_DisplayViaMode != VIA_HOLE_NOT_SHOW )
{
// Display all drill holes requested or Display non default holes requested
if( (DisplayOpt.m_DisplayViaMode == ALL_VIA_HOLE_SHOW)
|| ( (drill_radius > 0 ) && !IsDrillDefault() ) )
{
if( fillvia )
{
bool blackpenstate = false;
if( screen->m_IsPrinting )
{
blackpenstate = GetGRForceBlackPenState();
GRForceBlackPen( false );
color = WHITE;
}
else
{
color = BLACK; // or DARKGRAY;
}
if( (aDrawMode & GR_XOR) == 0)
GRSetDrawMode( aDC, GR_COPY );
if( aDC->LogicalToDeviceXRel( drill_radius ) > MIN_DRAW_WIDTH ) // Draw hole if large enough.
GRFilledCircle( panel->GetClipBox(), aDC, m_Start.x + aOffset.x,
m_Start.y + aOffset.y, drill_radius, 0, color, color );
if( screen->m_IsPrinting )
GRForceBlackPen( blackpenstate );
}
else
{
if( drill_radius < inner_radius ) // We can show the via hole
GRCircle( panel->GetClipBox(), aDC, m_Start + aOffset, drill_radius, 0, color );
}
}
}
if( ShowClearance( this ) )
{
GRCircle( panel->GetClipBox(), aDC, m_Start + aOffset, radius + GetClearance(), 0, color );
}
// for Micro Vias, draw a partial cross : X on component layer, or + on copper layer
// (so we can see 2 superimposed microvias ):
if( GetViaType() == VIA_MICROVIA )
{
int ax, ay, bx, by;
if( IsOnLayer( LAYER_N_BACK ) )
{
ax = radius; ay = 0;
bx = drill_radius; by = 0;
}
else
{
ax = ay = (radius * 707) / 1000;
bx = by = (drill_radius * 707) / 1000;
}
/* lines | or \ */
GRLine( panel->GetClipBox(), aDC, m_Start.x + aOffset.x - ax,
m_Start.y + aOffset.y - ay,
m_Start.x + aOffset.x - bx,
m_Start.y + aOffset.y - by, 0, color );
GRLine( panel->GetClipBox(), aDC, m_Start.x + aOffset.x + bx,
m_Start.y + aOffset.y + by,
m_Start.x + aOffset.x + ax,
m_Start.y + aOffset.y + ay, 0, color );
// lines - or /
GRLine( panel->GetClipBox(), aDC, m_Start.x + aOffset.x + ay,
m_Start.y + aOffset.y - ax,
m_Start.x + aOffset.x + by,
m_Start.y + aOffset.y - bx, 0, color );
GRLine( panel->GetClipBox(), aDC, m_Start.x + aOffset.x - by,
m_Start.y + aOffset.y + bx,
m_Start.x + aOffset.x - ay,
m_Start.y + aOffset.y + ax, 0, color );
}
// for Buried Vias, draw a partial line : orient depending on layer pair
// (so we can see superimposed buried vias ):
if( GetViaType() == VIA_BLIND_BURIED )
{
int ax = 0, ay = radius, bx = 0, by = drill_radius;
LAYER_NUM layer_top, layer_bottom;
( (VIA*) this )->LayerPair( &layer_top, &layer_bottom );
// lines for the top layer
RotatePoint( &ax, &ay, layer_top * 3600.0 / brd->GetCopperLayerCount( ) );
RotatePoint( &bx, &by, layer_top * 3600.0 / brd->GetCopperLayerCount( ) );
GRLine( panel->GetClipBox(), aDC, m_Start.x + aOffset.x - ax,
m_Start.y + aOffset.y - ay,
m_Start.x + aOffset.x - bx,
m_Start.y + aOffset.y - by, 0, color );
// lines for the bottom layer
ax = 0; ay = radius; bx = 0; by = drill_radius;
RotatePoint( &ax, &ay, layer_bottom * 3600.0 / brd->GetCopperLayerCount( ) );
RotatePoint( &bx, &by, layer_bottom * 3600.0 / brd->GetCopperLayerCount( ) );
GRLine( panel->GetClipBox(), aDC, m_Start.x + aOffset.x - ax,
m_Start.y + aOffset.y - ay,
m_Start.x + aOffset.x - bx,
m_Start.y + aOffset.y - by, 0, color );
}
// Display the short netname:
if( GetNetCode() == NETINFO_LIST::UNCONNECTED )
return;
if( DisplayOpt.DisplayNetNamesMode == 0 || DisplayOpt.DisplayNetNamesMode == 1 )
return;
NETINFO_ITEM* net = GetNet();
if( net == NULL )
return;
int len = net->GetShortNetname().Len();
if( len > 0 )
{
// calculate a good size for the text
int tsize = m_Width / len;
if( aDC->LogicalToDeviceXRel( tsize ) >= MIN_TEXT_SIZE )
{
tsize = (tsize * 7) / 10; // small reduction to give a better look, inside via
if( (aDrawMode & GR_XOR) == 0 )
GRSetDrawMode( aDC, GR_COPY );
EDA_RECT* clipbox = panel? panel->GetClipBox() : NULL;
DrawGraphicHaloText( clipbox, aDC, m_Start,
color, WHITE, BLACK, net->GetShortNetname(), 0,
wxSize( tsize, tsize ),
GR_TEXT_HJUSTIFY_CENTER, GR_TEXT_VJUSTIFY_CENTER,
tsize / 7, false, false );
}
}
}
void TRACK::Draw( EDA_DRAW_PANEL* panel, wxDC* aDC, GR_DRAWMODE aDrawMode,
const wxPoint& aOffset )
{
BOARD * brd = GetBoard( );
EDA_COLOR_T color = brd->GetLayerColor(m_Layer);
if( brd->IsLayerVisible( m_Layer ) == false && !( aDrawMode & GR_HIGHLIGHT ) )
return;
#ifdef USE_WX_OVERLAY
// If dragged not draw in OnPaint otherwise remains impressed in wxOverlay
if( (m_Flags & IS_DRAGGED) && aDC->IsKindOf(wxCLASSINFO(wxPaintDC)))
return;
#endif
if( ( aDrawMode & GR_ALLOW_HIGHCONTRAST ) && DisplayOpt.ContrastModeDisplay )
{
LAYER_NUM curr_layer = ( (PCB_SCREEN*) panel->GetScreen() )->m_Active_Layer;
if( !IsOnLayer( curr_layer ) )
ColorTurnToDarkDarkGray( &color );
}
if( aDrawMode & GR_HIGHLIGHT )
ColorChangeHighlightFlag( &color, !(aDrawMode & GR_AND) );
ColorApplyHighlightFlag( &color );
SetAlpha( &color, 150 );
GRSetDrawMode( aDC, aDrawMode );
int l_trace = m_Width / 2;
if( aDC->LogicalToDeviceXRel( l_trace ) <= MIN_DRAW_WIDTH )
{
GRLine( panel->GetClipBox(), aDC, m_Start + aOffset, m_End + aOffset, 0, color );
return;
}
if( !DisplayOpt.DisplayPcbTrackFill || GetState( FORCE_SKETCH ) )
{
GRCSegm( panel->GetClipBox(), aDC, m_Start + aOffset, m_End + aOffset, m_Width, color );
}
else
{
GRFillCSegm( panel->GetClipBox(), aDC, m_Start.x + aOffset.x,
m_Start.y + aOffset.y,
m_End.x + aOffset.x, m_End.y + aOffset.y, m_Width, color );
}
if( panel->GetScreen()->m_IsPrinting )
return;
// Show clearance for tracks, not for zone segments
if( ShowClearance( this ) )
{
GRCSegm( panel->GetClipBox(), aDC, m_Start + aOffset, m_End + aOffset,
m_Width + (GetClearance() * 2), color );
}
DrawShortNetname( panel, aDC, aDrawMode, color );
}
void D_PAD::Draw( EDA_DRAW_PANEL* aPanel, wxDC* aDC, GR_DRAWMODE aDraw_mode,
const wxPoint& aOffset )
{
wxSize mask_margin; // margin (clearance) used for some non copper layers
#ifdef SHOW_PADMASK_REAL_SIZE_AND_COLOR
int showActualMaskSize = 0; /* Layer number if the actual pad size on mask layer can
* be displayed i.e. if only one layer is shown for this pad
* and this layer is a mask (solder mask or solder paste
*/
#endif
if( m_Flags & DO_NOT_DRAW )
return;
PAD_DRAWINFO drawInfo;
drawInfo.m_Offset = aOffset;
/* We can show/hide pads from the layer manager.
* options are show/hide pads on front and/or back side of the board
* For through pads, we hide them only if both sides are hidden.
* smd pads on back are hidden for all layers (copper and technical layers)
* on back side of the board
* smd pads on front are hidden for all layers (copper and technical layers)
* on front side of the board
* ECO, edge and Draw layers and not considered
*/
BOARD* brd = GetBoard();
bool frontVisible = brd->IsElementVisible( PCB_VISIBLE( PAD_FR_VISIBLE ) );
bool backVisible = brd->IsElementVisible( PCB_VISIBLE( PAD_BK_VISIBLE ) );
if( !frontVisible && !backVisible )
return;
// If pad is only on front side (no layer on back side)
// and if hide front side pads is enabled, do not draw
if( !frontVisible && !( m_layerMask & LSET::BackMask() ).any() )
return;
// If pad is only on back side (no layer on front side)
// and if hide back side pads is enabled, do not draw
if( !backVisible && !( m_layerMask & LSET::FrontMask() ).any() )
return;
PCB_BASE_FRAME* frame = (PCB_BASE_FRAME*) aPanel->GetParent();
wxCHECK_RET( frame != NULL, wxT( "Panel has no parent frame window." ) );
DISPLAY_OPTIONS* displ_opts = (DISPLAY_OPTIONS*)frame->GetDisplayOptions();
PCB_SCREEN* screen = frame->GetScreen();
if( displ_opts && displ_opts->m_DisplayPadFill == SKETCH )
drawInfo.m_ShowPadFilled = false;
else
drawInfo.m_ShowPadFilled = true;
EDA_COLOR_T color = BLACK;
if( m_layerMask[F_Cu] )
{
color = brd->GetVisibleElementColor( PAD_FR_VISIBLE );
}
if( m_layerMask[B_Cu] )
{
color = ColorMix( color, brd->GetVisibleElementColor( PAD_BK_VISIBLE ) );
}
if( color == BLACK ) // Not on a visible copper layer (i.e. still nothing to show)
{
// If the pad is on only one tech layer, use the layer color else use DARKGRAY
LSET mask_non_copper_layers = m_layerMask & ~LSET::AllCuMask();
#ifdef SHOW_PADMASK_REAL_SIZE_AND_COLOR
mask_non_copper_layers &= brd->GetVisibleLayers();
#endif
LAYER_ID pad_layer = mask_non_copper_layers.ExtractLayer();
switch( (int) pad_layer )
{
case UNDEFINED_LAYER: // More than one layer
color = DARKGRAY;
break;
case UNSELECTED_LAYER: // Shouldn't really happen...
break;
default:
color = brd->GetLayerColor( pad_layer );
#ifdef SHOW_PADMASK_REAL_SIZE_AND_COLOR
showActualMaskSize = pad_layer;
#endif
}
}
// if SMD or connector pad and high contrast mode
if( ( aDraw_mode & GR_ALLOW_HIGHCONTRAST ) &&
( GetAttribute() == PAD_SMD || GetAttribute() == PAD_CONN ) &&
displ_opts && displ_opts->m_ContrastModeDisplay )
{
// when routing tracks
if( frame->GetToolId() == ID_TRACK_BUTT )
{
LAYER_ID routeTop = screen->m_Route_Layer_TOP;
LAYER_ID routeBot = screen->m_Route_Layer_BOTTOM;
// if routing between copper and component layers,
// or the current layer is one of said 2 external copper layers,
// then highlight only the current layer.
if( ( screen->m_Active_Layer == F_Cu || screen->m_Active_Layer == B_Cu ) ||
( routeTop==F_Cu && routeBot==B_Cu ) ||
( routeTop==B_Cu && routeBot==F_Cu )
)
{
if( !IsOnLayer( screen->m_Active_Layer ) )
ColorTurnToDarkDarkGray( &color );
}
// else routing between an internal signal layer and some other
// layer. Grey out all PAD_SMD pads not on current or the single
// selected external layer.
else if( !IsOnLayer( screen->m_Active_Layer )
&& !IsOnLayer( routeTop )
&& !IsOnLayer( routeBot ) )
{
ColorTurnToDarkDarkGray( &color );
}
}
// when not edting tracks, show PAD_SMD components not on active layer
// as greyed out
else
{
if( !IsOnLayer( screen->m_Active_Layer ) )
ColorTurnToDarkDarkGray( &color );
}
}
#ifdef SHOW_PADMASK_REAL_SIZE_AND_COLOR
if( showActualMaskSize )
{
switch( showActualMaskSize )
{
case B_Mask:
case F_Mask:
mask_margin.x = mask_margin.y = GetSolderMaskMargin();
break;
case B_Paste:
case F_Paste:
mask_margin = GetSolderPasteMargin();
break;
default:
// Another layer which has no margin to handle
break;
}
}
#endif
// if Contrast mode is ON and a technical layer active, show pads on this
// layer so we can see pads on paste or solder layer and the size of the
// mask
if( ( aDraw_mode & GR_ALLOW_HIGHCONTRAST ) &&
displ_opts && displ_opts->m_ContrastModeDisplay && !IsCopperLayer( screen->m_Active_Layer ) )
{
if( IsOnLayer( screen->m_Active_Layer ) )
{
color = brd->GetLayerColor( screen->m_Active_Layer );
// In high contrast mode, and if the active layer is the mask
// layer shows the pad size with the mask clearance
switch( screen->m_Active_Layer )
{
case B_Mask:
case F_Mask:
mask_margin.x = mask_margin.y = GetSolderMaskMargin();
break;
case B_Paste:
case F_Paste:
mask_margin = GetSolderPasteMargin();
break;
default:
break;
}
}
else
color = DARKDARKGRAY;
}
if( aDraw_mode & GR_HIGHLIGHT )
ColorChangeHighlightFlag( &color, !(aDraw_mode & GR_AND) );
ColorApplyHighlightFlag( &color );
bool DisplayIsol = displ_opts && displ_opts->m_DisplayPadIsol;
if( !( m_layerMask & LSET::AllCuMask() ).any() )
DisplayIsol = false;
if( ( GetAttribute() == PAD_HOLE_NOT_PLATED ) &&
brd->IsElementVisible( NON_PLATED_VISIBLE ) )
{
drawInfo.m_ShowNotPlatedHole = true;
drawInfo.m_NPHoleColor = brd->GetVisibleElementColor( NON_PLATED_VISIBLE );
}
drawInfo.m_DrawMode = aDraw_mode;
drawInfo.m_Color = color;
drawInfo.m_DrawPanel = aPanel;
drawInfo.m_Mask_margin = mask_margin;
drawInfo.m_ShowNCMark = brd->IsElementVisible( PCB_VISIBLE( NO_CONNECTS_VISIBLE ) );
drawInfo.m_IsPrinting = screen->m_IsPrinting;
SetAlpha( &color, 170 );
/* Get the pad clearance. This has a meaning only for Pcbnew.
* for CvPcb GetClearance() creates debug errors because
* there is no net classes so a call to GetClearance() is made only when
* needed (never needed in CvPcb)
*/
drawInfo.m_PadClearance = DisplayIsol ? GetClearance() : 0;
// Draw the pad number
if( displ_opts && !displ_opts->m_DisplayPadNum )
drawInfo.m_Display_padnum = false;
if( displ_opts &&
(( displ_opts ->m_DisplayNetNamesMode == 0 ) || ( displ_opts->m_DisplayNetNamesMode == 2 )) )
drawInfo.m_Display_netname = false;
// Display net names is restricted to pads that are on the active layer
// in high contrast mode display
if( ( aDraw_mode & GR_ALLOW_HIGHCONTRAST ) &&
!IsOnLayer( screen->m_Active_Layer ) && displ_opts && displ_opts->m_ContrastModeDisplay )
drawInfo.m_Display_netname = false;
DrawShape( aPanel->GetClipBox(), aDC, drawInfo );
}
/* Function TransformOutlinesShapeWithClearanceToPolygon
* Convert the zone filled areas polygons to polygons
* inflated (optional) by max( aClearanceValue, the zone clearance)
* and copy them in aCornerBuffer
* param aClearanceValue = the clearance around polygons
* param aAddClearance = true to add a clearance area to the polygon
* false to create the outline polygon.
*/
void ZONE_CONTAINER::TransformOutlinesShapeWithClearanceToPolygon(
CPOLYGONS_LIST& aCornerBuffer,
int aClearanceValue, bool aAddClearance )
{
// Creates the zone outlines polygon (with linked holes if any)
CPOLYGONS_LIST zoneOutines;
BuildFilledSolidAreasPolygons( NULL, &zoneOutines );
// add clearance to outline
int clearance = 0;
if( aAddClearance )
{
clearance = GetClearance();
if( aClearanceValue > clearance )
clearance = aClearanceValue;
}
// Calculate the polygon with clearance
// holes are linked to the main outline, so only one polygon should be created.
KI_POLYGON_SET polyset_zone_solid_areas;
std::vector<KI_POLY_POINT> cornerslist;
unsigned ic = 0;
unsigned corners_count = zoneOutines.GetCornersCount();
while( ic < corners_count )
{
cornerslist.clear();
KI_POLYGON poly;
{
for( ; ic < corners_count; ic++ )
{
CPolyPt* corner = &zoneOutines[ic];
cornerslist.push_back( KI_POLY_POINT( corner->x, corner->y ) );
if( corner->end_contour )
{
ic++;
break;
}
}
bpl::set_points( poly, cornerslist.begin(), cornerslist.end() );
polyset_zone_solid_areas.push_back( poly );
}
}
polyset_zone_solid_areas += clearance;
// Put the resulting polygon in aCornerBuffer corners list
for( unsigned ii = 0; ii < polyset_zone_solid_areas.size(); ii++ )
{
KI_POLYGON& poly = polyset_zone_solid_areas[ii];
CPolyPt corner( 0, 0, false );
for( unsigned jj = 0; jj < poly.size(); jj++ )
{
KI_POLY_POINT point = *(poly.begin() + jj);
corner.x = point.x();
corner.y = point.y();
corner.end_contour = false;
aCornerBuffer.Append( corner );
}
aCornerBuffer.CloseLastContour();
}
}
void D_PAD::Draw( EDA_DRAW_PANEL* aPanel, wxDC* aDC, int aDraw_mode, const wxPoint& aOffset )
{
int color = 0;
wxSize mask_margin; // margin (clearance) used for some non copper layers
#ifdef SHOW_PADMASK_REAL_SIZE_AND_COLOR
int showActualMaskSize = 0; /* Layer number if the actual pad size on mask layer can
* be displayed i.e. if only one layer is shown for this pad
* and this layer is a mask (solder mask or sloder paste
*/
#endif
if( m_Flags & DO_NOT_DRAW )
return;
PAD_DRAWINFO drawInfo;
drawInfo.m_Offset = aOffset;
/* We can show/hide pads from the layer manager.
* options are show/hide pads on front and/or back side of the board
* For through pads, we hide them only if both sides are hidden.
* smd pads on back are hidden for all layers (copper and technical layers)
* on back side of the board
* smd pads on front are hidden for all layers (copper and technical layers)
* on front side of the board
* ECO, edge and Draw layers and not considered
*/
// Mask layers for Back side of board
#define BACK_SIDE_LAYERS \
(LAYER_BACK | ADHESIVE_LAYER_BACK | SOLDERPASTE_LAYER_BACK \
| SILKSCREEN_LAYER_BACK | SOLDERMASK_LAYER_BACK)
// Mask layers for Front side of board
#define FRONT_SIDE_LAYERS \
(LAYER_FRONT | ADHESIVE_LAYER_FRONT | SOLDERPASTE_LAYER_FRONT \
| SILKSCREEN_LAYER_FRONT | SOLDERMASK_LAYER_FRONT)
BOARD* brd = GetBoard();
bool frontVisible = brd->IsElementVisible( PCB_VISIBLE( PAD_FR_VISIBLE ) );
bool backVisible = brd->IsElementVisible( PCB_VISIBLE( PAD_BK_VISIBLE ) );
if( !frontVisible && !backVisible )
return;
/* If pad are only on front side (no layer on back side)
* and if hide front side pads is enabled, do not draw
*/
if( !frontVisible && ( (m_layerMask & BACK_SIDE_LAYERS) == 0 ) )
return;
/* If pad are only on back side (no layer on front side)
* and if hide back side pads is enabled, do not draw
*/
if( !backVisible && ( (m_layerMask & FRONT_SIDE_LAYERS) == 0 ) )
return;
PCB_BASE_FRAME* frame = (PCB_BASE_FRAME*) aPanel->GetParent();
PCB_SCREEN* screen = frame->GetScreen();
if( frame->m_DisplayPadFill == FILLED )
drawInfo.m_ShowPadFilled = true;
else
drawInfo.m_ShowPadFilled = false;
if( m_layerMask & LAYER_FRONT )
{
color = brd->GetVisibleElementColor( PAD_FR_VISIBLE );
}
if( m_layerMask & LAYER_BACK )
{
color |= brd->GetVisibleElementColor( PAD_BK_VISIBLE );
}
if( color == 0 ) /* Not on copper layer */
{
// If the pad in on only one tech layer, use the layer color else use DARKGRAY
int mask_non_copper_layers = m_layerMask & ~ALL_CU_LAYERS;
#ifdef SHOW_PADMASK_REAL_SIZE_AND_COLOR
mask_non_copper_layers &= brd->GetVisibleLayers();
#endif
switch( mask_non_copper_layers )
{
case 0:
break;
case ADHESIVE_LAYER_BACK:
color = brd->GetLayerColor( ADHESIVE_N_BACK );
break;
case ADHESIVE_LAYER_FRONT:
color = brd->GetLayerColor( ADHESIVE_N_FRONT );
break;
case SOLDERPASTE_LAYER_BACK:
color = brd->GetLayerColor( SOLDERPASTE_N_BACK );
#ifdef SHOW_PADMASK_REAL_SIZE_AND_COLOR
showActualMaskSize = SOLDERPASTE_N_BACK;
#endif
break;
case SOLDERPASTE_LAYER_FRONT:
color = brd->GetLayerColor( SOLDERPASTE_N_FRONT );
#ifdef SHOW_PADMASK_REAL_SIZE_AND_COLOR
showActualMaskSize = SOLDERPASTE_N_FRONT;
#endif
break;
case SILKSCREEN_LAYER_BACK:
color = brd->GetLayerColor( SILKSCREEN_N_BACK );
break;
case SILKSCREEN_LAYER_FRONT:
color = brd->GetLayerColor( SILKSCREEN_N_FRONT );
break;
case SOLDERMASK_LAYER_BACK:
color = brd->GetLayerColor( SOLDERMASK_N_BACK );
#ifdef SHOW_PADMASK_REAL_SIZE_AND_COLOR
showActualMaskSize = SOLDERMASK_N_BACK;
#endif
break;
case SOLDERMASK_LAYER_FRONT:
color = brd->GetLayerColor( SOLDERMASK_N_FRONT );
#ifdef SHOW_PADMASK_REAL_SIZE_AND_COLOR
showActualMaskSize = SOLDERMASK_N_FRONT;
#endif
break;
case DRAW_LAYER:
color = brd->GetLayerColor( DRAW_N );
break;
case COMMENT_LAYER:
color = brd->GetLayerColor( COMMENT_N );
break;
case ECO1_LAYER:
color = brd->GetLayerColor( ECO1_N );
break;
case ECO2_LAYER:
color = brd->GetLayerColor( ECO2_N );
break;
case EDGE_LAYER:
color = brd->GetLayerColor( EDGE_N );
break;
default:
color = DARKGRAY;
break;
}
}
// if PAD_SMD pad and high contrast mode
if( ( aDraw_mode & GR_ALLOW_HIGHCONTRAST ) &&
( GetAttribute() == PAD_SMD || GetAttribute() == PAD_CONN ) &&
DisplayOpt.ContrastModeDisplay )
{
// when routing tracks
if( frame && frame->GetToolId() == ID_TRACK_BUTT )
{
int routeTop = screen->m_Route_Layer_TOP;
int routeBot = screen->m_Route_Layer_BOTTOM;
// if routing between copper and component layers,
// or the current layer is one of said 2 external copper layers,
// then highlight only the current layer.
if( ( ( 1 << routeTop ) | ( 1 << routeBot ) ) == ( LAYER_BACK | LAYER_FRONT )
|| ( ( 1 << screen->m_Active_Layer ) & ( LAYER_BACK | LAYER_FRONT ) ) )
{
if( !IsOnLayer( screen->m_Active_Layer ) )
{
color &= ~MASKCOLOR;
color |= DARKDARKGRAY;
}
}
// else routing between an internal signal layer and some other
// layer. Grey out all PAD_SMD pads not on current or the single
// selected external layer.
else if( !IsOnLayer( screen->m_Active_Layer )
&& !IsOnLayer( routeTop )
&& !IsOnLayer( routeBot ) )
{
color &= ~MASKCOLOR;
color |= DARKDARKGRAY;
}
}
// when not edting tracks, show PAD_SMD components not on active layer
// as greyed out
else
{
if( !IsOnLayer( screen->m_Active_Layer ) )
{
color &= ~MASKCOLOR;
color |= DARKDARKGRAY;
}
}
}
#ifdef SHOW_PADMASK_REAL_SIZE_AND_COLOR
if( showActualMaskSize )
{
switch( showActualMaskSize )
{
case SOLDERMASK_N_BACK:
case SOLDERMASK_N_FRONT:
mask_margin.x = mask_margin.y = GetSolderMaskMargin();
break;
case SOLDERPASTE_N_BACK:
case SOLDERPASTE_N_FRONT:
mask_margin = GetSolderPasteMargin();
break;
default:
break;
}
}
#endif
// if Contrast mode is ON and a technical layer active, show pads on this
// layer so we can see pads on paste or solder layer and the size of the
// mask
if( ( aDraw_mode & GR_ALLOW_HIGHCONTRAST ) &&
DisplayOpt.ContrastModeDisplay && screen->m_Active_Layer > LAST_COPPER_LAYER )
{
if( IsOnLayer( screen->m_Active_Layer ) )
{
color = brd->GetLayerColor( screen->m_Active_Layer );
// In hight contrast mode, and if the active layer is the mask
// layer shows the pad size with the mask clearance
switch( screen->m_Active_Layer )
{
case SOLDERMASK_N_BACK:
case SOLDERMASK_N_FRONT:
mask_margin.x = mask_margin.y = GetSolderMaskMargin();
break;
case SOLDERPASTE_N_BACK:
case SOLDERPASTE_N_FRONT:
mask_margin = GetSolderPasteMargin();
break;
default:
break;
}
}
else
color = DARKDARKGRAY;
}
if( aDraw_mode & GR_HIGHLIGHT )
{
if( aDraw_mode & GR_AND )
color &= ~HIGHLIGHT_FLAG;
else
color |= HIGHLIGHT_FLAG;
}
if( color & HIGHLIGHT_FLAG )
color = ColorRefs[color & MASKCOLOR].m_LightColor;
bool DisplayIsol = DisplayOpt.DisplayPadIsol;
if( ( m_layerMask & ALL_CU_LAYERS ) == 0 )
DisplayIsol = false;
if( GetAttribute() == PAD_HOLE_NOT_PLATED )
drawInfo.m_ShowNotPlatedHole = true;
drawInfo.m_DrawMode = aDraw_mode;
drawInfo.m_Color = color;
drawInfo.m_DrawPanel = aPanel;
drawInfo.m_Mask_margin = mask_margin;
drawInfo.m_ShowNCMark = brd->IsElementVisible( PCB_VISIBLE( NO_CONNECTS_VISIBLE ) );
drawInfo.m_IsPrinting = screen->m_IsPrinting;
SetAlpha( &color, 170 );
/* Get the pad clearance. This has a meaning only for Pcbnew.
* for CvPcb (and GerbView) GetClearance() creates debug errors because
* there is no net classes so a call to GetClearance() is made only when
* needed (never needed in CvPcb nor in GerbView)
*/
drawInfo.m_PadClearance = DisplayIsol ? GetClearance() : 0;
/* Draw the pad number */
if( frame && !frame->m_DisplayPadNum )
drawInfo.m_Display_padnum = false;
if( ( DisplayOpt.DisplayNetNamesMode == 0 ) || ( DisplayOpt.DisplayNetNamesMode == 2 ) )
drawInfo.m_Display_netname = false;
// Display net names is restricted to pads that are on the active layer
// in hight contrast mode display
if( ( aDraw_mode & GR_ALLOW_HIGHCONTRAST ) &&
!IsOnLayer( screen->m_Active_Layer ) && DisplayOpt.ContrastModeDisplay )
drawInfo.m_Display_netname = false;
DrawShape( aPanel->GetClipBox(), aDC, drawInfo );
}
/**
* Function AddClearanceAreasPolygonsToPolysList
* Supports a min thickness area constraint.
* Add non copper areas polygons (pads and tracks with clearance)
* to the filled copper area found
* in BuildFilledPolysListData after calculating filled areas in a zone
* Non filled copper areas are pads and track and their clearance areas
* The filled copper area must be computed just before.
* BuildFilledPolysListData() call this function just after creating the
* filled copper area polygon (without clearance areas)
* to do that this function:
* 1 - Creates the main outline (zone outline) using a correction to shrink the resulting area
* with m_ZoneMinThickness/2 value.
* The result is areas with a margin of m_ZoneMinThickness/2
* When drawing outline with segments having a thickness of m_ZoneMinThickness, the
* outlines will match exactly the initial outlines
* 3 - Add all non filled areas (pads, tracks) in group B with a clearance of m_Clearance +
* m_ZoneMinThickness/2
* in a buffer
* - If Thermal shapes are wanted, add non filled area, in order to create these thermal shapes
* 4 - calculates the polygon A - B
* 5 - put resulting list of polygons (filled areas) in m_FilledPolysList
* This zone contains pads with the same net.
* 6 - Remove insulated copper islands
* 7 - If Thermal shapes are wanted, remove unconnected stubs in thermal shapes:
* creates a buffer of polygons corresponding to stubs to remove
* sub them to the filled areas.
* Remove new insulated copper islands
*/
void ZONE_CONTAINER::AddClearanceAreasPolygonsToPolysList( BOARD* aPcb )
{
// Set the number of segments in arc approximations
if( m_ArcToSegmentsCount == ARC_APPROX_SEGMENTS_COUNT_HIGHT_DEF )
s_CircleToSegmentsCount = ARC_APPROX_SEGMENTS_COUNT_HIGHT_DEF;
else
s_CircleToSegmentsCount = ARC_APPROX_SEGMENTS_COUNT_LOW_DEF;
/* calculates the coeff to compensate radius reduction of holes clearance
* due to the segment approx.
* For a circle the min radius is radius * cos( 2PI / s_CircleToSegmentsCount / 2)
* s_Correction is 1 /cos( PI/s_CircleToSegmentsCount )
*/
s_Correction = 1.0 / cos( M_PI / s_CircleToSegmentsCount );
// This KI_POLYGON_SET is the area(s) to fill, with m_ZoneMinThickness/2
KI_POLYGON_SET polyset_zone_solid_areas;
int margin = m_ZoneMinThickness / 2;
/* First, creates the main polygon (i.e. the filled area using only one outline)
* to reserve a m_ZoneMinThickness/2 margin around the outlines and holes
* this margin is the room to redraw outlines with segments having a width set to
* m_ZoneMinThickness
* so m_ZoneMinThickness is the min thickness of the filled zones areas
* the main polygon is stored in polyset_zone_solid_areas
*/
CopyPolygonsFromFilledPolysListToKiPolygonList( polyset_zone_solid_areas );
polyset_zone_solid_areas -= margin;
if( polyset_zone_solid_areas.size() == 0 )
return;
/* Calculates the clearance value that meet DRC requirements
* from m_ZoneClearance and clearance from the corresponding netclass
* We have a "local" clearance in zones because most of time
* clearance between a zone and others items is bigger than the netclass clearance
* this is more true for small clearance values
* Note also the "local" clearance is used for clearance between non copper items
* or items like texts on copper layers
*/
int zone_clearance = std::max( m_ZoneClearance, GetClearance() );
zone_clearance += margin;
/* store holes (i.e. tracks and pads areas as polygons outlines)
* in a polygon list
*/
/* items ouside the zone bounding box are skipped
* the bounding box is the zone bounding box + the biggest clearance found in Netclass list
*/
EDA_RECT item_boundingbox;
EDA_RECT zone_boundingbox = GetBoundingBox();
int biggest_clearance = aPcb->GetDesignSettings().GetBiggestClearanceValue();
biggest_clearance = std::max( biggest_clearance, zone_clearance );
zone_boundingbox.Inflate( biggest_clearance );
/*
* First : Add pads. Note: pads having the same net as zone are left in zone.
* Thermal shapes will be created later if necessary
*/
int item_clearance;
// static to avoid unnecessary memory allocation when filling many zones.
static CPOLYGONS_LIST cornerBufferPolysToSubstract;
cornerBufferPolysToSubstract.RemoveAllContours();
/* Use a dummy pad to calculate hole clerance when a pad is not on all copper layers
* and this pad has a hole
* This dummy pad has the size and shape of the hole
* Therefore, this dummy pad is a circle or an oval.
* A pad must have a parent because some functions expect a non null parent
* to find the parent board, and some other data
*/
MODULE dummymodule( aPcb ); // Creates a dummy parent
D_PAD dummypad( &dummymodule );
for( MODULE* module = aPcb->m_Modules; module; module = module->Next() )
{
D_PAD* nextpad;
for( D_PAD* pad = module->Pads(); pad != NULL; pad = nextpad )
{
nextpad = pad->Next(); // pad pointer can be modified by next code, so
// calculate the next pad here
if( !pad->IsOnLayer( GetLayer() ) )
{
/* Test for pads that are on top or bottom only and have a hole.
* There are curious pads but they can be used for some components that are
* inside the board (in fact inside the hole. Some photo diodes and Leds are
* like this)
*/
if( pad->GetDrillSize().x == 0 && pad->GetDrillSize().y == 0 )
continue;
// Use a dummy pad to calculate a hole shape that have the same dimension as
// the pad hole
dummypad.SetSize( pad->GetDrillSize() );
dummypad.SetOrientation( pad->GetOrientation() );
dummypad.SetShape( pad->GetDrillShape() == PAD_DRILL_OBLONG ?
PAD_OVAL : PAD_CIRCLE );
dummypad.SetPosition( pad->GetPosition() );
pad = &dummypad;
}
// Note: netcode <=0 means not connected item
if( ( pad->GetNetCode() != GetNetCode() ) || ( pad->GetNetCode() <= 0 ) )
{
item_clearance = pad->GetClearance() + margin;
item_boundingbox = pad->GetBoundingBox();
item_boundingbox.Inflate( item_clearance );
if( item_boundingbox.Intersects( zone_boundingbox ) )
{
int clearance = std::max( zone_clearance, item_clearance );
pad->TransformShapeWithClearanceToPolygon( cornerBufferPolysToSubstract,
clearance,
s_CircleToSegmentsCount,
s_Correction );
}
continue;
}
if( ( GetPadConnection( pad ) == PAD_NOT_IN_ZONE )
|| ( pad->GetShape() == PAD_TRAPEZOID ) )
// PAD_TRAPEZOID shapes are not in zones because they are used in microwave apps
// and i think it is good that shapes are not changed by thermal pads or others
{
int gap = zone_clearance;
int thermalGap = GetThermalReliefGap( pad );
gap = std::max( gap, thermalGap );
item_boundingbox = pad->GetBoundingBox();
if( item_boundingbox.Intersects( zone_boundingbox ) )
{
pad->TransformShapeWithClearanceToPolygon( cornerBufferPolysToSubstract,
gap,
s_CircleToSegmentsCount,
s_Correction );
}
}
}
}
/* Add holes (i.e. tracks and vias areas as polygons outlines)
* in cornerBufferPolysToSubstract
*/
for( TRACK* track = aPcb->m_Track; track; track = track->Next() )
{
if( !track->IsOnLayer( GetLayer() ) )
continue;
if( track->GetNetCode() == GetNetCode() && (GetNetCode() != 0) )
continue;
item_clearance = track->GetClearance() + margin;
item_boundingbox = track->GetBoundingBox();
if( item_boundingbox.Intersects( zone_boundingbox ) )
{
int clearance = std::max( zone_clearance, item_clearance );
track->TransformShapeWithClearanceToPolygon( cornerBufferPolysToSubstract,
clearance,
s_CircleToSegmentsCount,
s_Correction );
}
}
/* Add module edge items that are on copper layers
* Pcbnew allows these items to be on copper layers in microwave applictions
* This is a bad thing, but must be handled here, until a better way is found
*/
for( MODULE* module = aPcb->m_Modules; module; module = module->Next() )
{
for( BOARD_ITEM* item = module->GraphicalItems(); item; item = item->Next() )
{
if( !item->IsOnLayer( GetLayer() ) && !item->IsOnLayer( Edge_Cuts ) )
continue;
if( item->Type() != PCB_MODULE_EDGE_T )
continue;
item_boundingbox = item->GetBoundingBox();
if( item_boundingbox.Intersects( zone_boundingbox ) )
{
( (EDGE_MODULE*) item )->TransformShapeWithClearanceToPolygon(
cornerBufferPolysToSubstract, zone_clearance,
s_CircleToSegmentsCount, s_Correction );
}
}
}
// Add graphic items (copper texts) and board edges
for( BOARD_ITEM* item = aPcb->m_Drawings; item; item = item->Next() )
{
if( item->GetLayer() != GetLayer() && item->GetLayer() != Edge_Cuts )
continue;
switch( item->Type() )
{
case PCB_LINE_T:
( (DRAWSEGMENT*) item )->TransformShapeWithClearanceToPolygon(
cornerBufferPolysToSubstract,
zone_clearance, s_CircleToSegmentsCount, s_Correction );
break;
case PCB_TEXT_T:
( (TEXTE_PCB*) item )->TransformBoundingBoxWithClearanceToPolygon(
cornerBufferPolysToSubstract, zone_clearance );
break;
default:
break;
}
}
// Add zones outlines having an higher priority and keepout
for( int ii = 0; ii < GetBoard()->GetAreaCount(); ii++ )
{
ZONE_CONTAINER* zone = GetBoard()->GetArea( ii );
if( zone->GetLayer() != GetLayer() )
continue;
if( !zone->GetIsKeepout() && zone->GetPriority() <= GetPriority() )
continue;
if( zone->GetIsKeepout() && ! zone->GetDoNotAllowCopperPour() )
continue;
// A highter priority zone or keepout area is found: remove its area
item_boundingbox = zone->GetBoundingBox();
if( !item_boundingbox.Intersects( zone_boundingbox ) )
continue;
// Add the zone outline area.
// However if the zone has the same net as the current zone,
// do not add clearance.
// the zone will be connected to the current zone, but filled areas
// will use different parameters (clearance, thermal shapes )
bool addclearance = GetNetCode() != zone->GetNetCode();
int clearance = zone_clearance;
if( zone->GetIsKeepout() )
{
addclearance = true;
clearance = m_ZoneMinThickness / 2;
}
zone->TransformOutlinesShapeWithClearanceToPolygon(
cornerBufferPolysToSubstract,
clearance, addclearance );
}
// Remove thermal symbols
for( MODULE* module = aPcb->m_Modules; module; module = module->Next() )
{
for( D_PAD* pad = module->Pads(); pad != NULL; pad = pad->Next() )
{
// Rejects non-standard pads with tht-only thermal reliefs
if( GetPadConnection( pad ) == THT_THERMAL
&& pad->GetAttribute() != PAD_STANDARD )
continue;
if( GetPadConnection( pad ) != THERMAL_PAD
&& GetPadConnection( pad ) != THT_THERMAL )
continue;
if( !pad->IsOnLayer( GetLayer() ) )
continue;
if( pad->GetNetCode() != GetNetCode() )
continue;
item_boundingbox = pad->GetBoundingBox();
int thermalGap = GetThermalReliefGap( pad );
item_boundingbox.Inflate( thermalGap, thermalGap );
if( item_boundingbox.Intersects( zone_boundingbox ) )
{
CreateThermalReliefPadPolygon( cornerBufferPolysToSubstract,
*pad, thermalGap,
GetThermalReliefCopperBridge( pad ),
m_ZoneMinThickness,
s_CircleToSegmentsCount,
s_Correction, s_thermalRot );
}
}
}
// cornerBufferPolysToSubstract contains polygons to substract.
// polyset_zone_solid_areas contains the main filled area
// Calculate now actual solid areas
if( cornerBufferPolysToSubstract.GetCornersCount() > 0 )
{
KI_POLYGON_SET polyset_holes;
cornerBufferPolysToSubstract.ExportTo( polyset_holes );
// Remove holes from initial area.:
polyset_zone_solid_areas -= polyset_holes;
}
// put solid areas in m_FilledPolysList:
m_FilledPolysList.RemoveAllContours();
CopyPolygonsFromKiPolygonListToFilledPolysList( polyset_zone_solid_areas );
// Remove insulated islands:
if( GetNetCode() > 0 )
TestForCopperIslandAndRemoveInsulatedIslands( aPcb );
// Now we remove all unused thermal stubs.
cornerBufferPolysToSubstract.RemoveAllContours();
// Test thermal stubs connections and add polygons to remove unconnected stubs.
// (this is a refinement for thermal relief shapes)
if( GetNetCode() > 0 )
BuildUnconnectedThermalStubsPolygonList( cornerBufferPolysToSubstract, aPcb, this,
s_Correction, s_thermalRot );
// remove copper areas corresponding to not connected stubs
if( cornerBufferPolysToSubstract.GetCornersCount() )
{
KI_POLYGON_SET polyset_holes;
cornerBufferPolysToSubstract.ExportTo( polyset_holes );
// Remove unconnected stubs
polyset_zone_solid_areas -= polyset_holes;
// put these areas in m_FilledPolysList
m_FilledPolysList.RemoveAllContours();
CopyPolygonsFromKiPolygonListToFilledPolysList( polyset_zone_solid_areas );
if( GetNetCode() > 0 )
TestForCopperIslandAndRemoveInsulatedIslands( aPcb );
}
cornerBufferPolysToSubstract.RemoveAllContours();
}
void VIA::Draw( EDA_DRAW_PANEL* panel, wxDC* aDC, GR_DRAWMODE aDrawMode, const wxPoint& aOffset )
{
wxCHECK_RET( panel != NULL, wxT( "VIA::Draw panel cannot be NULL." ) );
int radius;
PCB_LAYER_ID curr_layer = ( (PCB_SCREEN*) panel->GetScreen() )->m_Active_Layer;
int fillvia = 0;
PCB_BASE_FRAME* frame = (PCB_BASE_FRAME*) panel->GetParent();
PCB_SCREEN* screen = frame->GetScreen();
auto displ_opts = (PCB_DISPLAY_OPTIONS*)( frame->GetDisplayOptions() );
if( displ_opts->m_DisplayViaFill == FILLED )
fillvia = 1;
GRSetDrawMode( aDC, aDrawMode );
BOARD * brd = GetBoard();
COLOR4D color = frame->Settings().Colors().GetItemColor( LAYER_VIAS + GetViaType() );
if( brd->IsElementVisible( LAYER_VIAS + GetViaType() ) == false
&& !( aDrawMode & GR_HIGHLIGHT ) )
return;
// Only draw the via if at least one of the layers it crosses is being displayed
if( !( brd->GetVisibleLayers() & GetLayerSet() ).any() )
return;
if( displ_opts->m_ContrastModeDisplay )
{
if( !IsOnLayer( curr_layer ) )
color = COLOR4D( DARKDARKGRAY );
}
if( ( aDrawMode & GR_HIGHLIGHT ) && !( aDrawMode & GR_AND ) )
color.SetToLegacyHighlightColor();
color.a = 0.588;
radius = m_Width >> 1;
// for small via size on screen (radius < 4 pixels) draw a simplified shape
int radius_in_pixels = aDC->LogicalToDeviceXRel( radius );
bool fast_draw = false;
// Vias are drawn as a filled circle or a double circle. The hole will be drawn later
int drill_radius = GetDrillValue() / 2;
int inner_radius = radius - aDC->DeviceToLogicalXRel( 2 );
if( radius_in_pixels < MIN_VIA_DRAW_SIZE )
{
fast_draw = true;
fillvia = false;
}
if( fillvia )
{
GRFilledCircle( panel->GetClipBox(), aDC, m_Start + aOffset, radius, color );
}
else
{
GRCircle( panel->GetClipBox(), aDC, m_Start + aOffset, radius, 0, color );
if ( fast_draw )
return;
GRCircle( panel->GetClipBox(), aDC, m_Start + aOffset, inner_radius, 0, color );
}
if( fillvia )
{
bool blackpenstate = false;
if( screen->m_IsPrinting )
{
blackpenstate = GetGRForceBlackPenState();
GRForceBlackPen( false );
color = WHITE;
}
else
{
color = BLACK; // or DARKGRAY;
}
if( (aDrawMode & GR_XOR) == 0)
GRSetDrawMode( aDC, GR_COPY );
// Draw hole if the radius is > 1pixel.
if( aDC->LogicalToDeviceXRel( drill_radius ) > 1 )
GRFilledCircle( panel->GetClipBox(), aDC, m_Start.x + aOffset.x,
m_Start.y + aOffset.y, drill_radius, 0, color, color );
if( screen->m_IsPrinting )
GRForceBlackPen( blackpenstate );
}
else
{
if( drill_radius < inner_radius ) // We can show the via hole
GRCircle( panel->GetClipBox(), aDC, m_Start + aOffset, drill_radius, 0, color );
}
if( ShowClearance( displ_opts, this ) )
{
GRCircle( panel->GetClipBox(), aDC, m_Start + aOffset, radius + GetClearance(), 0, color );
}
// for Micro Vias, draw a partial cross : X on component layer, or + on copper layer
// (so we can see 2 superimposed microvias ):
if( GetViaType() == VIA_MICROVIA )
{
int ax, ay, bx, by;
if( IsOnLayer( B_Cu ) )
{
ax = radius; ay = 0;
bx = drill_radius; by = 0;
}
else
{
ax = ay = (radius * 707) / 1000;
bx = by = (drill_radius * 707) / 1000;
}
// lines '|' or '\'
GRLine( panel->GetClipBox(), aDC, m_Start.x + aOffset.x - ax,
m_Start.y + aOffset.y - ay,
m_Start.x + aOffset.x - bx,
m_Start.y + aOffset.y - by, 0, color );
GRLine( panel->GetClipBox(), aDC, m_Start.x + aOffset.x + bx,
m_Start.y + aOffset.y + by,
m_Start.x + aOffset.x + ax,
m_Start.y + aOffset.y + ay, 0, color );
// lines - or '/'
GRLine( panel->GetClipBox(), aDC, m_Start.x + aOffset.x + ay,
m_Start.y + aOffset.y - ax,
m_Start.x + aOffset.x + by,
m_Start.y + aOffset.y - bx, 0, color );
GRLine( panel->GetClipBox(), aDC, m_Start.x + aOffset.x - by,
m_Start.y + aOffset.y + bx,
m_Start.x + aOffset.x - ay,
m_Start.y + aOffset.y + ax, 0, color );
}
// for Buried Vias, draw a partial line : orient depending on layer pair
// (so we can see superimposed buried vias ):
if( GetViaType() == VIA_BLIND_BURIED )
{
int ax = 0, ay = radius, bx = 0, by = drill_radius;
PCB_LAYER_ID layer_top, layer_bottom;
LayerPair( &layer_top, &layer_bottom );
// lines for the top layer
RotatePoint( &ax, &ay, layer_top * 3600.0 / brd->GetCopperLayerCount( ) );
RotatePoint( &bx, &by, layer_top * 3600.0 / brd->GetCopperLayerCount( ) );
GRLine( panel->GetClipBox(), aDC, m_Start.x + aOffset.x - ax,
m_Start.y + aOffset.y - ay,
m_Start.x + aOffset.x - bx,
m_Start.y + aOffset.y - by, 0, color );
// lines for the bottom layer
ax = 0; ay = radius; bx = 0; by = drill_radius;
RotatePoint( &ax, &ay, layer_bottom * 3600.0 / brd->GetCopperLayerCount( ) );
RotatePoint( &bx, &by, layer_bottom * 3600.0 / brd->GetCopperLayerCount( ) );
GRLine( panel->GetClipBox(), aDC, m_Start.x + aOffset.x - ax,
m_Start.y + aOffset.y - ay,
m_Start.x + aOffset.x - bx,
m_Start.y + aOffset.y - by, 0, color );
}
// Display the short netname:
if( GetNetCode() == NETINFO_LIST::UNCONNECTED )
return;
if( displ_opts->m_DisplayNetNamesMode == 0 || displ_opts->m_DisplayNetNamesMode == 1 )
return;
NETINFO_ITEM* net = GetNet();
if( net == NULL )
return;
int len = net->GetShortNetname().Len();
if( len > 0 )
{
// calculate a good size for the text
int tsize = m_Width / len;
if( aDC->LogicalToDeviceXRel( tsize ) >= MIN_TEXT_SIZE )
{
tsize = (tsize * 7) / 10; // small reduction to give a better look, inside via
if( (aDrawMode & GR_XOR) == 0 )
GRSetDrawMode( aDC, GR_COPY );
EDA_RECT* clipbox = panel->GetClipBox();
DrawGraphicHaloText( clipbox, aDC, m_Start,
color, WHITE, BLACK, net->GetShortNetname(), 0,
wxSize( tsize, tsize ),
GR_TEXT_HJUSTIFY_CENTER, GR_TEXT_VJUSTIFY_CENTER,
tsize / 7, false, false );
}
}
}
void TRACK::Draw( EDA_DRAW_PANEL* panel, wxDC* aDC, GR_DRAWMODE aDrawMode,
const wxPoint& aOffset )
{
BOARD* brd = GetBoard();
auto frame = static_cast<PCB_BASE_FRAME*> ( panel->GetParent() );
auto color = frame->Settings().Colors().GetLayerColor( m_Layer );
if( ( !brd->IsLayerVisible( m_Layer ) || !brd->IsElementVisible( LAYER_TRACKS ) )
&& !( aDrawMode & GR_HIGHLIGHT ) )
return;
#ifdef USE_WX_OVERLAY
// If dragged not draw in OnPaint otherwise remains impressed in wxOverlay
if( (m_Flags & IS_DRAGGED) && aDC->IsKindOf(wxCLASSINFO(wxPaintDC)))
return;
#endif
auto displ_opts = (PCB_DISPLAY_OPTIONS*)( panel->GetDisplayOptions() );
if( ( aDrawMode & GR_ALLOW_HIGHCONTRAST ) && displ_opts->m_ContrastModeDisplay )
{
PCB_LAYER_ID curr_layer = ( (PCB_SCREEN*) panel->GetScreen() )->m_Active_Layer;
if( !IsOnLayer( curr_layer ) )
color = COLOR4D( DARKDARKGRAY );
}
if( ( aDrawMode & GR_HIGHLIGHT ) && !( aDrawMode & GR_AND ) )
color.SetToLegacyHighlightColor();
color.a = 0.588;
GRSetDrawMode( aDC, aDrawMode );
// Draw track as line if width <= 1pixel:
if( aDC->LogicalToDeviceXRel( m_Width ) <= 1 )
{
GRLine( panel->GetClipBox(), aDC, m_Start + aOffset, m_End + aOffset, m_Width, color );
return;
}
if( !displ_opts->m_DisplayPcbTrackFill || GetState( FORCE_SKETCH ) )
{
GRCSegm( panel->GetClipBox(), aDC, m_Start + aOffset, m_End + aOffset, m_Width, color );
}
else
{
GRFillCSegm( panel->GetClipBox(), aDC, m_Start.x + aOffset.x,
m_Start.y + aOffset.y,
m_End.x + aOffset.x, m_End.y + aOffset.y, m_Width, color );
}
if( panel->GetScreen()->m_IsPrinting )
return;
// Show clearance for tracks, not for zone segments
if( ShowClearance( displ_opts, this ) )
{
GRCSegm( panel->GetClipBox(), aDC, m_Start + aOffset, m_End + aOffset,
m_Width + (GetClearance() * 2), color );
}
DrawShortNetname( panel, aDC, aDrawMode, color );
}
