/**
* Performs CPU related initialization at the recovery entry point
*
* This function processes the MSR and PCI register tables.
*
* @param[in] CpuRecoveryParams Required input parameters for recovery CPU
* initialization.
*
* @retval AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
AmdCpuRecovery (
IN AMD_CPU_RECOVERY_PARAMS *CpuRecoveryParams
)
{
UINT8 i;
CPU_LOGICAL_ID CpuLogicalId;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
REGISTER_TABLE **RegisterTableList[2];
REGISTER_TABLE **RegisterTable;
TABLE_CORE_SELECTOR Selector;
REGISTER_TABLE **TableHandle;
GetLogicalIdOfCurrentCore (&CpuLogicalId, &CpuRecoveryParams->StdHeader);
GetCpuServicesFromLogicalId (&CpuLogicalId, &FamilySpecificServices, &CpuRecoveryParams->StdHeader);
RegisterTableList[0] = FamilySpecificServices->RegisterTableListBeforeApLaunch;
RegisterTableList[1] = FamilySpecificServices->RegisterTableListAfterApLaunch;
for (i = 0; i < 2; i++) {
for (Selector = AllCores; Selector < TableCoreSelectorMax; Selector++) {
if (IsCoreSelector (Selector, &CpuRecoveryParams->StdHeader)) {
// If the current core is the selected type of core, work the table list for tables for that type of core.
TableHandle = NULL;
RegisterTable = GetNextRegisterTable (Selector, RegisterTableList[i], &TableHandle, &CpuRecoveryParams->StdHeader);
while (*RegisterTable != NULL) {
SetRegistersFromTable (&CpuRecoveryParams->PlatformConfig, RegisterTable, &CpuRecoveryParams->StdHeader);
RegisterTable = GetNextRegisterTable (Selector, RegisterTableList[i], &TableHandle, &CpuRecoveryParams->StdHeader);
}
} else {
// Once a selector does not match the current core, quit looking.
break;
}
}
}
LoadMicrocodePatch (&CpuRecoveryParams->StdHeader);
return (AGESA_SUCCESS);
}
/**
* Support routine for F10PmAfterReset to perform MSR initialization on all
* cores of a family 10h socket.
*
* This function implements steps 2 - 24 on each core.
*
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
STATIC
F10PmAfterResetCore (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 Socket;
UINT32 Module;
UINT32 Ignored;
UINT32 PsMaxVal;
UINT32 LocalPciRegister;
UINT64 LocalMsrRegister;
UINT64 SavedMsr;
UINT64 CurrentLimitMsr;
PCI_ADDR PciAddress;
GO_TO_STEP GoToStep;
AGESA_STATUS IgnoredSts;
CPU_LOGICAL_ID LogicalId;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
// Step 2 If MSR C001_0071[CurNbDid] = 0, set MSR C001_001F[GfxNbPstateDis]
GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
GetCpuServicesFromLogicalId (&LogicalId, &FamilySpecificServices, StdHeader);
if ((LogicalId.Revision & (AMD_F10_C3 | AMD_F10_DA_C2)) != 0) {
LibAmdMsrRead (MSR_COFVID_STS, &LocalMsrRegister, StdHeader);
if (((COFVID_STS_MSR *) &LocalMsrRegister)->CurNbDid == 0) {
LibAmdMsrRead (NB_CFG, &LocalMsrRegister, StdHeader);
LocalMsrRegister |= BIT62;
LibAmdMsrWrite (NB_CFG, &LocalMsrRegister, StdHeader);
}
}
GoToStep = EXIT_SEQUENCE;
LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &CurrentLimitMsr, StdHeader);
PsMaxVal = (UINT32) (((PSTATE_CURLIM_MSR *) &CurrentLimitMsr)->PstateMaxVal);
// Step 3 If MSRC001_0071[CurPstate] != F3xDC[PstateMaxVal], go to step 20
LibAmdMsrRead (MSR_COFVID_STS, &LocalMsrRegister, StdHeader);
if (((COFVID_STS_MSR *) &LocalMsrRegister)->CurPstate !=
((PSTATE_CURLIM_MSR *) &CurrentLimitMsr)->PstateMaxVal) {
GoToStep = STEP20;
} else {
// Step 4 If F3xDC[PstateMaxVal] = 0 || F3xDC[PstateMaxVal] != 4, go to step 7
if ((PsMaxVal == 0) || (PsMaxVal != 4)) {
GoToStep = STEP7;
} else {
// Step 5 If MSRC001_0061[CurPstateLimit] <= F3xDC[PstateMaxVal]-1, go to step 17
if (((PSTATE_CURLIM_MSR *) &CurrentLimitMsr)->CurPstateLimit <=
(((PSTATE_CURLIM_MSR *) &CurrentLimitMsr)->PstateMaxVal - 1)) {
GoToStep = STEP17;
}
}
}
switch (GoToStep) {
default:
case EXIT_SEQUENCE:
// Step 6 Exit the sequence
break;
case STEP7:
// Workaround for S3 ----Save the value of [The PState[4:0] Registers] MSRC001_00[68:64]
// pointed to by F3xDC[PstateMaxVal] + 1
LibAmdMsrRead ((MSR_PSTATE_0 + (PsMaxVal + 1)), &SavedMsr, StdHeader);
// Step 7 Copy the P-state register pointed to by F3xDC[PstateMaxVal] to the P-state
// register pointed to by F3xDC[PstateMaxVal]+1
LibAmdMsrRead ((MSR_PSTATE_0 + PsMaxVal), &LocalMsrRegister, StdHeader);
LibAmdMsrWrite ((MSR_PSTATE_0 + (PsMaxVal + 1)), &LocalMsrRegister, StdHeader);
// Step 8 Write F3xDC[PstateMaxVal]+1 to F3xDC[PstateMaxVal]
IdentifyCore (StdHeader, &Socket, &Module, &Ignored, &IgnoredSts);
GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
PciAddress.Address.Function = FUNC_3;
PciAddress.Address.Register = CPTC2_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->PstateMaxVal = PsMaxVal + 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
// Step 9 Write (the new) F3xDC[PstateMaxVal] to MSRC001_0062[PstateCmd]
FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) (PsMaxVal + 1), (BOOLEAN) FALSE, StdHeader);
// Step 10 Wait for MSRC001_0071[CurCpuFid/CurCpuDid] = CpuFid/CpuDid from the P-state
// register pointed to by (the new) F3xDC[PstateMaxVal]
WaitForCpuFidAndDidToMatch ((UINT32) (PsMaxVal + 1), StdHeader);
// Step 11 Copy (the new) F3xDC[PstateMaxVal]-1 to MSRC001_0062[PstateCmd]
FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) PsMaxVal, (BOOLEAN) FALSE, StdHeader);
// Step 12 Wait for MSRC001_0071[CurCpuFid/CurCpuDid] = CpuFid/CpuDid from the P-state
// register pointed to by (the new) F3xDC[PstateMaxVal]-1
WaitForCpuFidAndDidToMatch (PsMaxVal, StdHeader);
// Step 13 If MSRC001_0071[CurNbDid] = 1, set MSRC001_001F[GfxNbPstateDis]
if ((LogicalId.Revision & (AMD_F10_C3 | AMD_F10_DA_C2)) != 0) {
LibAmdMsrRead (MSR_COFVID_STS, &LocalMsrRegister, StdHeader);
if (((COFVID_STS_MSR *) &LocalMsrRegister)->CurNbDid == 1) {
LibAmdMsrRead (NB_CFG, &LocalMsrRegister, StdHeader);
LocalMsrRegister |= BIT62;
LibAmdMsrWrite (NB_CFG, &LocalMsrRegister, StdHeader);
}
}
// Step 14 If required, transition the NB COF and VID to the NbDid and NbVid from the
// P-state register pointed to by MSRC001_0061[CurPstateLimit] using the NB COF
// and VID transition sequence after a warm reset
// Step 15 Write 0 to PstateEn of the P-state register pointed to by (the new) F3xDC[PstateMaxVal]
// Workaround for S3----Restore the value of [The PState[4:0] Registers] MSRC001_00[68:64]
// pointed to by F3xDC[PstateMaxVal] + 1
((PSTATE_MSR *) &SavedMsr)->PsEnable = 0;
LibAmdMsrWrite ((MSR_PSTATE_0 + (PsMaxVal + 1)), &SavedMsr, StdHeader);
// Step 16 Write (the new) F3xDC[PstateMaxVal]-1 to F3xDC[PstateMaxVal]
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->PstateMaxVal = PsMaxVal;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
break;
case STEP17:
// Step 17 Copy F3xDC[PstateMaxVal]-1 to MSRC001_0062[PstateCmd]
FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) (PsMaxVal - 1), (BOOLEAN) FALSE, StdHeader);
// Step 18 Wait for MSRC001_0071[CurCpuFid/CurCpuDid] = CpuFid/CpuDid from the P-state
// register pointed to by F3xDC[PstateMaxVal]-1
WaitForCpuFidAndDidToMatch ((UINT32) (PsMaxVal - 1), StdHeader);
// Step 19 If MSR C001_0071[CurNbDid] = 0, set MSR C001_001F[GfxNbPstateDis]
if ((LogicalId.Revision & (AMD_F10_C3 | AMD_F10_DA_C2)) != 0) {
LibAmdMsrRead (MSR_COFVID_STS, &LocalMsrRegister, StdHeader);
if (((COFVID_STS_MSR *) &LocalMsrRegister)->CurNbDid == 0) {
LibAmdMsrRead (NB_CFG, &LocalMsrRegister, StdHeader);
LocalMsrRegister |= BIT62;
LibAmdMsrWrite (NB_CFG, &LocalMsrRegister, StdHeader);
}
}
// Fall through from step 19 to step 20
case STEP20:
// Step 20 Copy F3xDC[PstateMaxVal] to MSRC001_0062[PstateCmd]
FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) PsMaxVal, (BOOLEAN) FALSE, StdHeader);
// Step 21 Wait for MSRC001_0071[CurCpuFid/CurCpuDid] = CpuFid/CpuDid from the P-state
// register pointed to by F3xDC[PstateMaxVal]
WaitForCpuFidAndDidToMatch (PsMaxVal, StdHeader);
// Step 22 If MSR C001_0071[CurNbDid] = 1, set MSR C001_001F[GfxNbPstateDis] and exit
// the sequence
if ((LogicalId.Revision & (AMD_F10_C3 | AMD_F10_DA_C2)) != 0) {
LibAmdMsrRead (MSR_COFVID_STS, &LocalMsrRegister, StdHeader);
if (((COFVID_STS_MSR *) &LocalMsrRegister)->CurNbDid == 1) {
LibAmdMsrRead (NB_CFG, &LocalMsrRegister, StdHeader);
LocalMsrRegister |= BIT62;
LibAmdMsrWrite (NB_CFG, &LocalMsrRegister, StdHeader);
break;
}
}
// Step 23 Issue an LDTSTOP and exit the sequence
// Step 24 If required, transition the NB COF and VID to the NbDid and NbVid from the
// P-state register pointed to by F3xDC[PstateMaxVal] using the NB COF and VID
// transition sequence after a warm reset
break;
}
}