int
hal_enable_profile_timer(int resolution)
{
// Run periodic timer interrupt for profile
cyg_uint16 piscr;
int period = resolution / 100;
// Attach pit arbiter.
HAL_INTERRUPT_ATTACH (PIT_IRQ,
&hal_arbitration_isr_pit, ID_PIT, 0);
HAL_INTERRUPT_UNMASK (PIT_IRQ);
// Attach pit isr.
HAL_INTERRUPT_ATTACH (CYGNUM_HAL_INTERRUPT_SIU_PIT, &isr_pit,
ID_PIT, 0);
HAL_INTERRUPT_SET_LEVEL (CYGNUM_HAL_INTERRUPT_SIU_PIT, PIT_IRQ_LEVEL);
HAL_INTERRUPT_UNMASK (CYGNUM_HAL_INTERRUPT_SIU_PIT);
// Set period.
HAL_WRITE_UINT32 (CYGARC_REG_IMM_PITC,
(2*period) << CYGARC_REG_IMM_PITC_COUNT_SHIFT);
// Enable.
HAL_READ_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
piscr |= CYGARC_REG_IMM_PISCR_PTE;
HAL_WRITE_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
return resolution;
}
static int
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
static int irq_state = 0;
channel_data_t* chan = (channel_data_t*)__ch_data;
int ret = 0;
CYGARC_HAL_SAVE_GP();
switch (__func) {
case __COMMCTL_GETBAUD:
ret = chan->baud_rate;
break;
case __COMMCTL_SETBAUD:
{
va_list ap;
va_start(ap, __func);
ret = chan->baud_rate;
chan->baud_rate = va_arg(ap, cyg_int32);
init_serial_channel(chan);
va_end(ap);
}
break;
case __COMMCTL_IRQ_ENABLE:
HAL_INTERRUPT_SET_LEVEL(chan->imb3_vector, chan->level);
HAL_INTERRUPT_UNMASK(chan->imb3_vector);
HAL_INTERRUPT_UNMASK(chan->siu_vector);
irq_state = 1;
break;
case __COMMCTL_IRQ_DISABLE:
ret = irq_state;
irq_state = 0;
HAL_INTERRUPT_MASK(chan->imb3_vector);
HAL_INTERRUPT_MASK(chan->siu_vector);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = chan->siu_vector;
break;
case __COMMCTL_SET_TIMEOUT:
{
va_list ap;
va_start(ap, __func);
ret = chan->msec_timeout;
chan->msec_timeout = va_arg(ap, cyg_uint32);
va_end(ap);
}
break;
default:
break;
}
CYGARC_HAL_RESTORE_GP();
return ret;
}
externC hal_mpc5xx_arbitration_data *
hal_mpc5xx_remove_arbitration_isr(cyg_uint32 apriority)
{
hal_mpc5xx_arbitration_data * result = 0;
// Find the SIU vector from the priority
CYG_ADDRWORD vector = 2*(1 + apriority);
if(vector < CYGNUM_HAL_INTERRUPT_SIU_LVL7)
{
result = (hal_mpc5xx_arbitration_data *)(hal_interrupt_objects[vector]);
HAL_INTERRUPT_DETACH(vector, hal_interrupt_handlers[vector]);
}
else
{
#ifdef CYGSEM_HAL_POWERPC_MPC5XX_IMB3_ARBITER
// Prevent anything from coming through while manipulating the list
HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_LVL7);
result = mpc5xx_remove(imb3_data_head, apriority);
// If something was removed, update the list.
if(result) imb3_data_head = result->reserved;
HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_SIU_LVL7);
#else
result = (hal_mpc5xx_arbitration_data *)(hal_interrupt_objects[CYGNUM_HAL_INTERRUPT_SIU_LVL7]);
HAL_INTERRUPT_DETACH(CYGNUM_HAL_INTERRUPT_SIU_LVL7, hal_interrupt_handlers[CYGNUM_HAL_INTERRUPT_SIU_LVL7]);
#endif
}
return result;
}
// Profiling timer setup
int hal_enable_profile_timer(int resolution)
{
cyg_uint32 period;
// Calculate how many timer ticks the requested resolution in
// microseconds equates to. We do this calculation in 64 bit
// arithmetic to avoid overflow.
period = (cyg_uint32)((((cyg_uint64)resolution) *
((cyg_uint64)CYGNUM_HAL_ARM_AT91_CLOCK_SPEED))/32000000LL);
CYG_ASSERT(period < 0x10000, "Invalid profile timer resolution"); // 16 bits only
// Attach ISR
HAL_INTERRUPT_ATTACH(HAL_INTERRUPT_PROFILE, &profile_isr, 0x1111, 0);
HAL_INTERRUPT_UNMASK(HAL_INTERRUPT_PROFILE);
// Disable counter
HAL_WRITE_UINT32(AT91_TC+AT91_TC_PROFILE+AT91_TC_CCR, AT91_TC_CCR_CLKDIS);
// Set registers
HAL_WRITE_UINT32(AT91_TC+AT91_TC_PROFILE+AT91_TC_CMR, AT91_TC_CMR_CPCTRG | // Reset counter on CPC
AT91_TC_CMR_CLKS_MCK32); // Use MCLK/32
HAL_WRITE_UINT32(AT91_TC+AT91_TC_PROFILE+AT91_TC_RC, period);
// Start timer
HAL_WRITE_UINT32(AT91_TC+AT91_TC_PROFILE+AT91_TC_CCR, AT91_TC_CCR_TRIG | AT91_TC_CCR_CLKEN);
// Enable timer interrupt
HAL_WRITE_UINT32(AT91_TC+AT91_TC_PROFILE+AT91_TC_IER, AT91_TC_IER_CPC);
return resolution;
}
static int
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
int ret = 0;
struct port_info *info = (struct port_info *)__ch_data;
switch (__func) {
case __COMMCTL_IRQ_ENABLE:
HAL_INTERRUPT_UNMASK(info->intnum);
info->irq_state = 1;
break;
case __COMMCTL_IRQ_DISABLE:
ret = info->irq_state;
info->irq_state = 0;
HAL_INTERRUPT_MASK(info->intnum);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = info->intnum;
break;
case __COMMCTL_SET_TIMEOUT:
{
va_list ap;
va_start(ap, __func);
ret = msec_timeout;
msec_timeout = va_arg(ap, cyg_uint32);
va_end(ap);
}
default:
break;
}
return ret;
}
void
hasp_mpc5xxx_i2c_init()
{
initReset(); // initialise the reset pin
resetHigh();
cyg_drv_mutex_init(&i2c_lock);
cyg_drv_cond_init(&i2c_wait, &i2c_lock);
cyg_drv_interrupt_create(i2c_intr_vector,
0,
(cyg_addrword_t) 0,
&mpc5xxx_i2c_isr,
&mpc5xxx_i2c_dsr,
&(i2c_interrupt_handle),
&(i2c_interrupt_data));
cyg_drv_interrupt_attach(i2c_interrupt_handle);
HAL_WRITE_UINT32(I2C_0_FDR_REG, 0x89000000); // Set clock to 100MHz / 352
HAL_WRITE_UINT32(I2C_0_ADDRESS_REG, 0x00000000); // Set MPC5xxx slave address, not useful to us
HAL_WRITE_UINT32(I2C_0_CONTROL_REG, I2C_ENABLE); // Enable the I2C device but do not start any transfers and leave interrupts disabled.
HAL_WRITE_UINT32(I2C_0_STATUS_REG, 0x00000000); // Clear any pending conditions including interrupts.
HAL_INTERRUPT_UNMASK(i2c_intr_vector); // Interrupts can now be safely unmasked
i2c_flag = 0;
resetLow();
}
externC void
hal_variant_IRQ_init(void)
{
#ifdef CYGSEM_HAL_POWERPC_MPC860_CPM_ENABLE
// Attach first-level CPM arbiter to the configured SIU level and
// enable CPM interrupts.
#define ID_CPM 0xDEAD
#define CYGPRI_SIU_LVL (CYGNUM_HAL_INTERRUPT_SIU_LVL0 \
+CYGHWR_HAL_POWERPC_MPC860_CPM_LVL*2)
HAL_INTERRUPT_ATTACH (CYGPRI_SIU_LVL, &hal_arbitration_isr_cpm, ID_CPM, 0);
HAL_INTERRUPT_UNMASK (CYGPRI_SIU_LVL);
HAL_INTERRUPT_SET_LEVEL (CYGNUM_HAL_INTERRUPT_SIU_CPM,
CYGHWR_HAL_POWERPC_MPC860_CPM_LVL);
HAL_INTERRUPT_UNMASK (CYGNUM_HAL_INTERRUPT_SIU_CPM);
#endif
}
void
watchdogInt(void) {
HAL_INTERRUPT_ATTACH(CYGNUM_HAL_INTERRUPT_WATCHDOG,
wd_ISR,
NULL, NULL);
HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_WATCHDOG);
diag_printf("Watchdog Int installed!!!\n");
}
// -------------------------------------------------------------------------
// Variant specific interrupt setup
externC void
hal_variant_IRQ_init(void)
{
#ifdef CYGSEM_HAL_POWERPC_MPC5XX_IMB3_ARBITER
HAL_INTERRUPT_ATTACH(CYGNUM_HAL_INTERRUPT_SIU_LVL7, hal_arbitration_imb3, &imb3_data_head, 0);
HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_SIU_LVL7);
#endif
}
static int
cyg_hal_plf_scif_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
static int irq_state = 0;
channel_data_t* chan = (channel_data_t*)__ch_data;
cyg_uint8 scr;
int ret = 0;
CYGARC_HAL_SAVE_GP();
switch (__func) {
case __COMMCTL_IRQ_ENABLE:
irq_state = 1;
HAL_INTERRUPT_UNMASK(chan->isr_vector);
HAL_READ_UINT8(chan->base+_REG_SCSCR, scr);
scr |= CYGARC_REG_SCIF_SCSCR_RIE;
HAL_WRITE_UINT8(chan->base+_REG_SCSCR, scr);
break;
case __COMMCTL_IRQ_DISABLE:
ret = irq_state;
irq_state = 0;
HAL_INTERRUPT_UNMASK(chan->isr_vector);
HAL_READ_UINT8(chan->base+_REG_SCSCR, scr);
scr &= ~CYGARC_REG_SCIF_SCSCR_RIE;
HAL_WRITE_UINT8(chan->base+_REG_SCSCR, scr);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = chan->isr_vector;
break;
case __COMMCTL_SET_TIMEOUT:
{
va_list ap;
va_start(ap, __func);
ret = chan->msec_timeout;
chan->msec_timeout = va_arg(ap, cyg_uint32);
va_end(ap);
}
default:
break;
}
CYGARC_HAL_RESTORE_GP();
return ret;
}
static int
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
static int irq_state = 0;
channel_data_t* chan = (channel_data_t*)__ch_data;
int ret = 0;
CYGARC_HAL_SAVE_GP();
switch (__func) {
case __COMMCTL_GETBAUD:
ret = chan->baud_rate;
break;
case __COMMCTL_SETBAUD:
{
va_list ap;
va_start(ap, __func);
ret = chan->baud_rate;
chan->baud_rate = va_arg(ap, cyg_int32);
init_serial_channel(chan);
va_end(ap);
}
break;
case __COMMCTL_IRQ_ENABLE:
// Just enable the interrupt on the IMB3. The debugged application is
// must make sure that the interrupt is properly decoded
HAL_INTERRUPT_UNMASK(chan->imb3_vector);
irq_state = 1;
break;
case __COMMCTL_IRQ_DISABLE:
// Same remark as above
ret = irq_state;
irq_state = 0;
HAL_INTERRUPT_MASK(chan->imb3_vector);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = chan->imb3_vector;
break;
case __COMMCTL_SET_TIMEOUT:
{
va_list ap;
va_start(ap, __func);
ret = chan->msec_timeout;
chan->msec_timeout = va_arg(ap, cyg_uint32);
va_end(ap);
}
break;
default:
break;
}
CYGARC_HAL_RESTORE_GP();
return ret;
}
static int
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
static int irq_state = 0;
channel_data_t* chan = (channel_data_t*)__ch_data;
cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
cyg_uint16 ser_port_reg;
int ret = 0;
va_list ap;
CYGARC_HAL_SAVE_GP();
va_start(ap, __func);
switch (__func) {
case __COMMCTL_GETBAUD:
ret = chan->baud_rate;
break;
case __COMMCTL_SETBAUD:
chan->baud_rate = va_arg(ap, cyg_int32);
// Should we verify this value here?
cyg_hal_plf_serial_init_channel(chan);
ret = 0;
break;
case __COMMCTL_IRQ_ENABLE:
irq_state = 1;
HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
HAL_INTERRUPT_UNMASK(chan->isr_vector);
HAL_READ_UINT16(FREESCALE_ESCI_CR12(base), ser_port_reg);
ser_port_reg |= FREESCALE_ESCI_CR12_RIE;
HAL_WRITE_UINT16(FREESCALE_ESCI_CR12(base), ser_port_reg);
break;
case __COMMCTL_IRQ_DISABLE:
ret = irq_state;
irq_state = 0;
HAL_INTERRUPT_MASK(chan->isr_vector);
HAL_READ_UINT16(FREESCALE_ESCI_CR12(base), ser_port_reg);
ser_port_reg &= ~(cyg_uint16)FREESCALE_ESCI_CR12_RIE;
HAL_WRITE_UINT16(FREESCALE_ESCI_CR12(base), ser_port_reg);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = chan->isr_vector;
break;
case __COMMCTL_SET_TIMEOUT:
ret = chan->msec_timeout;
chan->msec_timeout = va_arg(ap, cyg_uint32);
default:
break;
}
va_end(ap);
CYGARC_HAL_RESTORE_GP();
return ret;
}
static int
cyg_hal_plf_serial_control(void* __ch_data, __comm_control_cmd_t __func, ...)
{
static int irq_state = 0;
channel_data_t* chan = (channel_data_t*)__ch_data;
volatile cyg_uint32* pulBase = chan->pulBase;
int ret = 0;
cyg_uint8 status;
CYGARC_HAL_SAVE_GP();
switch (__func)
{
case __COMMCTL_IRQ_ENABLE:
irq_state = 1;
// Ensure that only Receive ints are generated.
status = pulBase[REL_Adr_uartcr / sizeof(cyg_uint8)];
status |= (MSK_uartcr_RTIE | MSK_uartcr_RIE);
pulBase[REL_Adr_uartcr / sizeof(cyg_uint8)] = status;
HAL_INTERRUPT_UNMASK(chan->isr_vector);
break;
case __COMMCTL_IRQ_DISABLE:
ret = irq_state;
irq_state = 0;
status = pulBase[REL_Adr_uartcr / sizeof(cyg_uint8)];
status &= ~(MSK_uartcr_RTIE | MSK_uartcr_TIE | MSK_uartcr_RIE | MSK_uartcr_MSIE);
pulBase[REL_Adr_uartcr / sizeof(cyg_uint8)] = status;
HAL_INTERRUPT_MASK(chan->isr_vector);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = chan->isr_vector;
break;
case __COMMCTL_SET_TIMEOUT:
{
va_list ap;
va_start(ap, __func);
ret = chan->msec_timeout;
chan->msec_timeout = va_arg(ap, cyg_uint32);
va_end(ap);
}
default:
break;
}
CYGARC_HAL_RESTORE_GP();
return ret;
}
static void hal_ctrlc_isr_init(void)
{
// cyg_uint16 cr;
// HAL_READ_UINT16( SERIAL_CR, cr );
// cr |= LCR_RXE;
// HAL_WRITE_UINT16( SERIAL_CR, cr );
HAL_INTERRUPT_SET_LEVEL( CYGHWR_HAL_GDB_PORT_VECTOR, 4 );
HAL_INTERRUPT_UNMASK( CYGHWR_HAL_GDB_PORT_VECTOR );
}
externC void
hal_mpc5xx_remove_arbitration_isr(hal_mpc5xx_arbitration_data * adata)
{
#ifdef CYGSEM_HAL_POWERPC_MPC5XX_IMB3_ARBITER
// Prevent anything from coming through while manipulating the list
HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_LVL7);
imb3_data_head = mpc5xx_remove(imb3_data_head, adata);
HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_SIU_LVL7);
#endif
}
static int CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
channel_data_t* chan = (channel_data_t*)__ch_data;
CYG_ADDRESS uart_p = ((channel_data_t*)__ch_data)->base;
cyg_uint8 ser_port_reg;
int ret = 0;
va_list ap;
CYGARC_HAL_SAVE_GP();
va_start(ap, __func);
switch (__func) {
case __COMMCTL_IRQ_ENABLE:
chan->irq_state = 1;
HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
HAL_INTERRUPT_UNMASK(chan->isr_vector);
HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg);
ser_port_reg |= CYGHWR_DEV_FREESCALE_UART_C2_RIE;
HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg);
break;
case __COMMCTL_IRQ_DISABLE:
ret = chan->irq_state;
chan->irq_state = 0;
HAL_INTERRUPT_MASK(chan->isr_vector);
HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg);
ser_port_reg &= ~(cyg_uint8)CYGHWR_DEV_FREESCALE_UART_C2_RIE;
HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = chan->isr_vector;
break;
case __COMMCTL_SET_TIMEOUT:
ret = chan->msec_timeout;
chan->msec_timeout = va_arg(ap, cyg_uint32);
case __COMMCTL_GETBAUD:
ret = chan->baud_rate;
break;
case __COMMCTL_SETBAUD:
chan->baud_rate = va_arg(ap, cyg_int32);
// Should we verify this value here?
cyg_hal_plf_serial_init_channel(chan);
ret = 0;
break;
default:
break;
}
va_end(ap);
CYGARC_HAL_RESTORE_GP();
return ret;
}
static int
net_io_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
static int vector = 0;
int ret = 0;
static int irq_state = 0;
CYGARC_HAL_SAVE_GP();
switch (__func) {
case __COMMCTL_IRQ_ENABLE:
irq_state = 1;
if (vector == 0) {
vector = eth_drv_int_vector();
}
HAL_INTERRUPT_UNMASK(vector);
break;
case __COMMCTL_IRQ_DISABLE:
ret = irq_state;
irq_state = 0;
if (vector == 0) {
vector = eth_drv_int_vector();
}
HAL_INTERRUPT_MASK(vector);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = vector;
break;
case __COMMCTL_SET_TIMEOUT:
{
va_list ap;
va_start(ap, __func);
ret = _timeout;
_timeout = va_arg(ap, cyg_uint32);
va_end(ap);
break;
}
case __COMMCTL_FLUSH_OUTPUT:
net_io_flush();
break;
case __COMMCTL_ENABLE_LINE_FLUSH:
flush_output_lines = true;
break;
case __COMMCTL_DISABLE_LINE_FLUSH:
flush_output_lines = false;
break;
default:
break;
}
CYGARC_HAL_RESTORE_GP();
return ret;
}
externC void
hal_variant_IRQ_init(void)
{
HAL_INTERRUPT_MASK (CYGNUM_EXPANSION);
/* clear the mask register */
HAL_WRITE_UINT32(INTR_MASK_REG, 0); /* all expansion interrupts are masked */
HAL_INTERRUPT_ATTACH (CYGNUM_EXPANSION, &hal_extended_isr, 0, 0);
HAL_INTERRUPT_UNMASK (CYGNUM_EXPANSION);
}
void hal_clock_initialize(cyg_uint32 period)
{
*PXA2X0_OSMR0 = period; // Load match value
clock_period = period;
*PXA2X0_OSCR = 0; // Start the counter
*PXA2X0_OSSR = PXA2X0_OSSR_TIMER0; // Clear any pending interrupt
*PXA2X0_OIER |= PXA2X0_OIER_TIMER0; // Enable timer 0 interrupt
HAL_INTERRUPT_UNMASK( CYGNUM_HAL_INTERRUPT_TIMER0 ); // Unmask timer 0 interrupt
}
static int
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
static int irq_state = 0;
channel_data_t* chan = (channel_data_t*)__ch_data;
int ret = 0;
CYGARC_HAL_SAVE_GP();
switch (__func) {
case __COMMCTL_IRQ_ENABLE:
irq_state = 1;
HAL_WRITE_UINT8(chan->base+CYG_DEV_IER, SIO_IER_RCV);
HAL_INTERRUPT_UNMASK(chan->isr_vector);
break;
case __COMMCTL_IRQ_DISABLE:
ret = irq_state;
irq_state = 0;
HAL_WRITE_UINT8(chan->base+CYG_DEV_IER, 0);
HAL_INTERRUPT_MASK(chan->isr_vector);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = chan->isr_vector;
break;
case __COMMCTL_SET_TIMEOUT:
{
va_list ap;
va_start(ap, __func);
ret = chan->msec_timeout;
chan->msec_timeout = va_arg(ap, cyg_uint32);
va_end(ap);
}
case __COMMCTL_GETBAUD:
ret = chan->baud_rate;
break;
case __COMMCTL_SETBAUD:
{
va_list ap;
va_start(ap, __func);
chan->baud_rate = va_arg(ap, cyg_int32);
va_end(ap);
ret = set_baud(chan);
break;
}
default:
break;
}
CYGARC_HAL_RESTORE_GP();
return ret;
}
externC void cyg_drv_interrupt_unmask_intunsafe( cyg_vector_t vector )
{
CYG_REPORT_FUNCTION();
CYG_REPORT_FUNCARG1("vector=%d", vector);
CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector");
CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector");
HAL_INTERRUPT_UNMASK( vector );
CYG_REPORT_RETURN();
}
static int
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
static int irq_state = 0;
channel_data_t* chan = (channel_data_t*)__ch_data;
int ret = -1;
cyg_uint8 ier;
va_list ap;
CYGARC_HAL_SAVE_GP();
va_start(ap, __func);
switch (__func) {
case __COMMCTL_GETBAUD:
ret = chan->baud_rate;
break;
case __COMMCTL_SETBAUD:
chan->baud_rate = va_arg(ap, cyg_int32);
// Should we verify this value here?
init_channel(chan);
ret = 0;
break;
case __COMMCTL_IRQ_ENABLE:
HAL_INTERRUPT_UNMASK(chan->isr_vector);
HAL_INTERRUPT_SET_LEVEL(chan->isr_vector, 1);
HAL_READ_UINT8(chan->base+PXA2X0_UART_IER, ier);
ier |= PXA2X0_UART_IER_RAVIE;
HAL_WRITE_UINT8(chan->base+PXA2X0_UART_IER, ier);
irq_state = 1;
break;
case __COMMCTL_IRQ_DISABLE:
ret = irq_state;
irq_state = 0;
HAL_INTERRUPT_MASK(chan->isr_vector);
HAL_READ_UINT8(chan->base+PXA2X0_UART_IER, ier);
ier &= ~PXA2X0_UART_IER_RAVIE;
HAL_WRITE_UINT8(chan->base+PXA2X0_UART_IER, ier);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = chan->isr_vector;
break;
case __COMMCTL_SET_TIMEOUT:
ret = chan->msec_timeout;
chan->msec_timeout = va_arg(ap, cyg_uint32);
break;
default:
break;
}
va_end(ap);
CYGARC_HAL_RESTORE_GP();
return ret;
}
externC void
hal_mpc5xx_install_arbitration_isr(hal_mpc5xx_arbitration_data * adata)
{
CYG_ADDRWORD vector = 2*(1 + adata->priority);
if(vector < CYGNUM_HAL_INTERRUPT_SIU_LVL7)
{
HAL_INTERRUPT_ATTACH(vector, adata->arbiter, adata->data, 0);
HAL_INTERRUPT_UNMASK(vector);
}
else
{
#ifdef CYGSEM_HAL_POWERPC_MPC5XX_IMB3_ARBITER
// Prevent anything from coming through while manipulating
// the list
HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_LVL7);
imb3_data_head = mpc5xx_insert(imb3_data_head, adata);
HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_SIU_LVL7);
#else
HAL_INTERRUPT_ATTACH(CYGNUM_HAL_INTERRUPT_SIU_LVL7, adata->arbiter, adata->data, 0);
HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_SIU_LVL7);
#endif
}
}
static int
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
static int irq_state = 0;
channel_data_t* chan = (channel_data_t*)__ch_data;
int ret = 0;
cyg_uint8 status;
CYGARC_HAL_SAVE_GP();
switch (__func) {
case __COMMCTL_IRQ_ENABLE:
irq_state = 1;
// Ensure that only Receive ints are generated.
status = IO_READ(chan->base + AMBA_UARTCR);
status |= (AMBA_UARTCR_RTIE | AMBA_UARTCR_RIE);
HAL_WRITE_UINT32(chan->base + AMBA_UARTCR, status);
HAL_INTERRUPT_UNMASK(chan->isr_vector);
break;
case __COMMCTL_IRQ_DISABLE:
ret = irq_state;
irq_state = 0;
status = IO_READ(chan->base + AMBA_UARTCR);
status &= ~(AMBA_UARTCR_RTIE | AMBA_UARTCR_TIE | AMBA_UARTCR_RIE | AMBA_UARTCR_MSIE);
HAL_WRITE_UINT32(chan->base + AMBA_UARTCR, status);
HAL_INTERRUPT_MASK(chan->isr_vector);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = chan->isr_vector;
break;
case __COMMCTL_SET_TIMEOUT:
{
va_list ap;
va_start(ap, __func);
ret = chan->msec_timeout;
chan->msec_timeout = va_arg(ap, cyg_uint32);
va_end(ap);
}
default:
break;
}
CYGARC_HAL_RESTORE_GP();
return ret;
}
static int cyg_hal_plf_duart_control(void *__ch_data,
__comm_control_cmd_t __func, ...)
{
static int irq_state = 0;
channel_data_t* chan = (channel_data_t*)__ch_data;
uart_width ier;
int ret = 0;
CYGARC_HAL_SAVE_GP();
switch (__func) {
case __COMMCTL_IRQ_ENABLE:
HAL_INTERRUPT_UNMASK(chan->isr_vector);
HAL_INTERRUPT_SET_LEVEL(chan->isr_vector, 1);
HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
ier |= SIO_IER_ERDAI;
HAL_WRITE_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
irq_state = 1;
break;
case __COMMCTL_IRQ_DISABLE:
ret = irq_state;
irq_state = 0;
HAL_INTERRUPT_MASK(chan->isr_vector);
HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
ier &= ~SIO_IER_ERDAI;
HAL_WRITE_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = chan->isr_vector;
break;
case __COMMCTL_SET_TIMEOUT:
{
va_list ap;
va_start(ap, __func);
ret = chan->msec_timeout;
chan->msec_timeout = va_arg(ap, cyg_uint32);
va_end(ap);
}
break;
default:
break;
}
CYGARC_HAL_RESTORE_GP();
return ret;
}
externC void cyg_drv_interrupt_unmask( cyg_vector_t vector )
{
CYG_INTERRUPT_STATE old_ints;
CYG_REPORT_FUNCTION();
CYG_REPORT_FUNCARG1("vector=%d", vector);
CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector");
CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector");
HAL_DISABLE_INTERRUPTS(old_ints);
HAL_INTERRUPT_UNMASK( vector );
HAL_RESTORE_INTERRUPTS(old_ints);
CYG_REPORT_RETURN();
}
static int
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
static int irq_state = 0;
cyg_uint32 intm;
channel_data_t* chan = (channel_data_t*)__ch_data;
cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
int ret = 0;
CYGARC_HAL_SAVE_GP();
switch (__func) {
case __COMMCTL_IRQ_ENABLE:
irq_state = 1;
HAL_READ_UINT32(base+AAEC_UART_INTM, intm);
intm |= AAEC_UART_INT_RIS|AAEC_UART_INT_RTIS;
HAL_WRITE_UINT32(base+AAEC_UART_INTM, intm);
HAL_INTERRUPT_UNMASK(chan->isr_vector);
break;
case __COMMCTL_IRQ_DISABLE:
ret = irq_state;
irq_state = 0;
HAL_READ_UINT32(base+AAEC_UART_INTM, intm);
intm &= ~(AAEC_UART_INT_RIS|AAEC_UART_INT_RTIS);
HAL_WRITE_UINT32(base+AAEC_UART_INTM, intm);
HAL_INTERRUPT_MASK(chan->isr_vector);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = chan->isr_vector;
break;
case __COMMCTL_SET_TIMEOUT:
{
va_list ap;
va_start(ap, __func);
ret = chan->msec_timeout;
chan->msec_timeout = va_arg(ap, cyg_uint32);
va_end(ap);
}
default:
break;
}
CYGARC_HAL_RESTORE_GP();
return ret;
}
externC void
hal_variant_IRQ_init(void)
{
// Mask off everything. This guarantees that we can safely install a handler on the decrementer
// later on
HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_IRQ0);
HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_IRQ1);
HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_IRQ2);
HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_IRQ3);
HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_IRQ4);
HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_IRQ5);
HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_IRQ6);
HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_IRQ7);
HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_LVL0);
HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_LVL1);
HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_LVL2);
HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_LVL3);
HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_LVL4);
HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_LVL5);
HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_LVL6);
HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_LVL7);
#ifdef CYGSEM_HAL_POWERPC_MPC5XX_IMB3_ARBITER
HAL_INTERRUPT_ATTACH(CYGNUM_HAL_INTERRUPT_SIU_LVL7, hal_arbitration_imb3, &imb3_data_head, 0);
HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_SIU_LVL7);
#endif
#if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) \
|| defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT)
// GDB-CTRLC
// Install a default arbiter for serial interrupts. This allows
// to make a boot monitor simply turn on the required Rx interrupt
// and still be delivered the necessary default isr. Without this,
// redboot would be informed of a level interrupt on the SIU instead
// of the Rx interrupt that really happened.
// Make sure the interrupts are set up on the correct level
sci_arbiter.priority = CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI;
sci_arbiter.data = 0;
sci_arbiter.arbiter = hal_arbitration_isr_sci;
hal_mpc5xx_install_arbitration_isr(&sci_arbiter);
HAL_INTERRUPT_SET_LEVEL(CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX, CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI);
HAL_INTERRUPT_SET_LEVEL(CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX, CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI);
#endif
}
static int
cyg_hal_plf_serial_dbg_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
static int irq_state = 0;
channel_data_t* chan = (channel_data_t*)__ch_data;
int ret = 0;
va_list ap;
CYGARC_HAL_SAVE_GP();
va_start(ap, __func);
switch (__func) {
case __COMMCTL_GETBAUD:
ret = chan->baud_rate;
break;
case __COMMCTL_SETBAUD:
chan->baud_rate = va_arg(ap, cyg_int32);
// Should we verify this value here?
cyg_hal_plf_serial_dbg_init_channel(chan);
ret = 0;
break;
case __COMMCTL_IRQ_ENABLE:
irq_state = 1;
HAL_INTERRUPT_UNMASK(chan->isr_vector);
HAL_WRITE_UINT32((chan->base+AT91_DBG_IER), AT91_DBG_CSR_RXRDY);
break;
case __COMMCTL_IRQ_DISABLE:
ret = irq_state;
irq_state = 0;
HAL_WRITE_UINT32((chan->base+AT91_DBG_IDR), AT91_DBG_CSR_RXRDY);
HAL_INTERRUPT_MASK(chan->isr_vector);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = chan->isr_vector;
break;
case __COMMCTL_SET_TIMEOUT:
ret = chan->msec_timeout;
chan->msec_timeout = va_arg(ap, cyg_uint32);
default:
break;
}
CYGARC_HAL_RESTORE_GP();
return ret;
}
static int
cyg_hal_plf_serial_control(channel_data_t *chan, __comm_control_cmd_t func, ...)
{
Xuint16 opt;
int ret = 0;
led(1);
if (!chan->dev_ok) return ret;
switch (func) {
case __COMMCTL_IRQ_ENABLE:
opt = XUartNs550_GetOptions(&chan->dev) | XUN_OPTION_DATA_INTR;
XUartNs550_SetOptions(&chan->dev, opt);
HAL_INTERRUPT_UNMASK(chan->isr_vector);
chan->int_state = 1;
break;
case __COMMCTL_IRQ_DISABLE:
ret = chan->int_state;
chan->int_state = 0;
opt = XUartNs550_GetOptions(&chan->dev) & ~XUN_OPTION_DATA_INTR;
XUartNs550_SetOptions(&chan->dev, opt);
HAL_INTERRUPT_MASK(chan->isr_vector);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = chan->isr_vector;
break;
case __COMMCTL_SET_TIMEOUT:
{
va_list ap;
va_start(ap, func);
ret = chan->msec_timeout;
chan->msec_timeout = va_arg(ap, cyg_uint32);
va_end(ap);
}
default:
break;
}
return ret;
}
