static int __init at32_init_ide_or_cf(struct platform_device *pdev,
unsigned int cs, unsigned int extint)
{
static unsigned int extint_pin_map[4] __initdata = {
GPIO_PIN_PB(25),
GPIO_PIN_PB(26),
GPIO_PIN_PB(27),
GPIO_PIN_PB(28),
};
static bool common_pins_initialized __initdata = false;
unsigned int extint_pin;
int ret;
if (extint >= ARRAY_SIZE(extint_pin_map))
return -EINVAL;
extint_pin = extint_pin_map[extint];
switch (cs) {
case 4:
ret = platform_device_add_resources(pdev,
at32_smc_cs4_resource,
ARRAY_SIZE(at32_smc_cs4_resource));
if (ret)
return ret;
select_peripheral(PE(21), PERIPH_A, 0); /* NCS4 -> OE_N */
set_ebi_sfr_bits(HMATRIX_BIT(CS4A));
break;
case 5:
ret = platform_device_add_resources(pdev,
at32_smc_cs5_resource,
ARRAY_SIZE(at32_smc_cs5_resource));
if (ret)
return ret;
select_peripheral(PE(22), PERIPH_A, 0); /* NCS5 -> OE_N */
set_ebi_sfr_bits(HMATRIX_BIT(CS5A));
break;
default:
return -EINVAL;
}
if (!common_pins_initialized) {
select_peripheral(PE(19), PERIPH_A, 0); /* CFCE1 -> CS0_N */
select_peripheral(PE(20), PERIPH_A, 0); /* CFCE2 -> CS1_N */
select_peripheral(PE(23), PERIPH_A, 0); /* CFRNW -> DIR */
select_peripheral(PE(24), PERIPH_A, 0); /* NWAIT <- IORDY */
common_pins_initialized = true;
}
at32_select_periph(extint_pin, GPIO_PERIPH_A, AT32_GPIOF_DEGLITCH);
pdev->resource[1].start = EIM_IRQ_BASE + extint;
pdev->resource[1].end = pdev->resource[1].start;
return 0;
}
int board_early_init_f(void)
{
/* Enable SDRAM in the EBI mux */
hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
portmux_enable_ebi(32, 23, 0, PORTMUX_DRIVE_HIGH);
sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config);
portmux_enable_usart1(PORTMUX_DRIVE_MIN);
#if defined(CONFIG_MACB)
portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
#endif
#if defined(CONFIG_MMC)
portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
#endif
return 0;
}
