/*************************************************************************
* FUNCTION
* USC_Wake_Up_Init
*
* DESCRIPTION
* This function is used to initialize the us counter variable during waking up to fixed us HW bug.
* ths function is only called by UL1SM_Interrupt (3G wake-up LISR) and L1SM_TDMAInterrupt (2G wake up LISR)
*
* PARAMETERS
* Timer - 0: use TDMA timer, 1: use RTR timer
*
* RETURNS
* none
*
*************************************************************************/
void USC_Wake_Up_Init( kal_uint32 Timer )
{
#if defined(MT6268_S00)
kal_uint32 irq;
irq = LockIRQ();
if( Wake_US_Updated == 0)
{
Wake_USCNTI = HW_READ(USCNTI_VAL);
Wake_Timer = Timer;
Wake_33us_TimeOut = 0;
if( Timer == 0 )
Wake_TimerCnt = HW_READ(US_TD_Timer);
else
Wake_TimerCnt = HW_READ(US_RTR_Timer) & 0x7FFF ;
Wake_US_Updated = 1;
//Wake_Temp_Dur = 0;
//Wake_Timer_Count = 0;
}
RestoreIRQ(irq & 0x000000c0);
#endif
}
void HW_wait_32k_start(void)
{
#if MD_DRV_IS_CENTRALIZED_SMM_CHIP
#ifdef __UE_SIMULATOR__
#undef FRC_CMD_MAGIC_VALUE
#define FRC_CMD_MAGIC_VALUE 0x62760000
#endif
/*CSMM use 26M to calibrate 32K at TOPSM HW module*/
kal_uint32 result;
int count = 0;
int waiting_32k_count = 80000;
kal_uint32 tmp_T0 = 0, tmp_T1 = 0, tmp_D0 = 0, tmp_D1 = 0;
/* Enable FRC for FM. */
HW_WRITE( SM_FRC_CON, (FRC_CMD_MAGIC_VALUE+0x00000001) );
HW_WRITE( SM_FM_CAL, 2 ); /*calibrate 2T 32K, ideal got 1586.9T 26M*/
while(count < waiting_32k_count)
{
/* Enable FM and no need to Unmask FM INT. */
HW_WRITE(SM_FM_CON, 0x11);
/* Polling until FM_EN bit is cleared. */
while((HW_READ(SM_FM_CON) & 0x1)) ;
tmp_T0 = (HW_READ(SM_FM_T0)) & 0xFFFFFF;
tmp_D0 = (HW_READ(SM_FM_T0)) >> 24;
tmp_T1 = (HW_READ(SM_FM_T1)) & 0xFFFFFF;
tmp_D1 = (HW_READ(SM_FM_T1)) >> 24;
if( tmp_T1 > tmp_T0 )
{
result = (tmp_T1*26+tmp_D1) - (tmp_T0*26+tmp_D0);
}
else /* 1MHz FRC wrap case: */
{
result = ((tmp_T1+0x1000000)*26+tmp_D1) - (tmp_T0*26+tmp_D0);
}
if( FM_RESULT_LOWER_BOUND < result && result < FM_RESULT_UPPER_BOUND )
{
/* Clear INT of FM. Need to set bit[4] to mask it. */
HW_WRITE(SM_FM_CON, 0x110);
break;
}
count++;
}
#else
#error "Please implement HW_wait_32k_start() for non-centralized-sleep-mode chip"
#endif
}
static void MD_DRV_WAIT_TIME_QB( short time_qb )
{
unsigned short last_qb, cur_qb;
short qb_diff, qb_remain;
qb_remain = time_qb;
last_qb = HW_READ( TQ_CURRENT_COUNT );
while( qb_remain>0 )
{ cur_qb = HW_READ( TQ_CURRENT_COUNT );
qb_diff = cur_qb-last_qb;
qb_remain -= (qb_diff<0) ? 1 : qb_diff;
last_qb = cur_qb;
}
}
// These functions may be called at system bootup time,
// so we need to keep the code and data in primary MAUI
void L1D_HW_TDMA_AUX_TIME_SETUP(kal_uint16 event0, kal_uint16 event1)
{
kal_uint16 d16 = (kal_uint16)HW_READ(TDMA_AUXEVENA);
HW_WRITE(TDMA_AUXEV0, event0);
HW_WRITE(TDMA_AUXEV1, event1);
HW_WRITE(TDMA_AUXEVENA, (d16|0x3));
}
int console_init( Console* cons )
{
ptr base = 0;
int status = 0;
uint channel = 0;
uint control = 0;
base = console_getbase( cons );
channel = cons->channel == CONSOLE_1 ? COM1 : COM2;
/* Reset port first */
cons->write_bytes = 0;
cons->read_bytes = 0;
status = bwsetspeed( channel, cons->speed );
control = HW_READ( base, UART_LCRH_OFFSET );
if( cons->fifo ){
control |= FEN_MASK;
} else {
control &= ( ~FEN_MASK );
}
if( cons->dbl_stop ){
control |= STP2_MASK;
}
HW_WRITE( base, UART_LCRH_OFFSET, control );
ASSERT( status == ERR_NONE );
/* Leave no garbage */
console_drain( cons );
return ERR_NONE;
}
static void MD_DRV_L1D_DisableAllIRQ( void )
{
HW_WRITE( EVENT_ENA(0), (HW_READ(EVENT_ENA(0))&0x0000)|MD_DRV_EVTENA0_SLOW_EN_SEL );
HW_WRITE( EVENT_ENA(1), (HW_READ(EVENT_ENA(1))&0x0080) );
HW_WRITE( EVENT_ENA(2), 0x0000 );
HW_WRITE( EVENT_ENA(3), 0x0000 );
HW_WRITE( EVENT_ENA(4), 0x0000 );
HW_WRITE( EVENT_ENA(5), 0x0000 );
HW_WRITE( EVENT_ENA(6), 0x0000 );
#if MD_DRV_IS_TXPC_CL_AUXADC_SUPPORT
HW_WRITE( EVENT_ENA(7), (HW_READ(EVENT_ENA(7))&0x0003) );
#endif
#if MD_DRV_IS_CHIP_MT6290 || MD_DRV_IS_CHIP_MT6595 || MD_DRV_IS_CHIP_MT6752_MD1 || MD_DRV_IS_CHIP_MT6752_MD2 || MD_DRV_IS_CHIP_MT6735
HW_WRITE( EVENT_ENA(8), 0x0000 );
HW_WRITE( EVENT_ENA(9), 0x0000 );
#endif
}
/*************************************************************************
* FUNCTION
* USC_Get_TimeStamp
*
* DESCRIPTION
* This function calculate the frame number.
*
* PARAMETERS
* none
*
* RETURNS
* Frame number since system power up
*
*************************************************************************/
kal_uint32 DEVDRV_LS_INTSRAM_ROCODE USC_Get_TimeStamp( void )
{
#if defined(__ALIGN_2G_CLOCK__)
kal_uint32 uscnti,curFrame,_savedMask;
_savedMask = SaveAndSetIRQMask();
uscnti= ust_get_current_time();
if (uscnti >= Pre_USCNTI) {
curFrame = USCNT_TO_FRAME( uscnti - Pre_USCNTI ); // dur/3250/(120/26)
} else {
curFrame = USCNT_TO_FRAME((USCNT_WRAP - Pre_USCNTI) + uscnti);
}
FrameCount += curFrame;
Pre_USCNTI += FRAME_TO_USCNT(curFrame);
if( Pre_USCNTI > USCNT_WRAP )
{
Pre_USCNTI -= USCNT_WRAP;
}
RestoreIRQMask(_savedMask);
return FrameCount;
#else
kal_uint32 uscnti,curFrame,_savedMask;
_savedMask = SaveAndSetIRQMask();
#if defined(__HW_OSTICK_CNT__)
HW_WRITE(OST_CMD, CMD_MAGIC_VALUE | 0x02);
curFrame = HW_READ(OST_TIMER_CNT_R);
#else
uscnti= ust_get_current_time();
if (uscnti >= Pre_USCNTI) {
Total_USCNTI += (uscnti - Pre_USCNTI);
} else {
Total_USCNTI += ((USCNT_WRAP - Pre_USCNTI) + uscnti);
}
Pre_USCNTI = uscnti;
curFrame = USCNT_TO_FRAME(Total_USCNTI);
#endif
RestoreIRQMask(_savedMask);
return curFrame;
#endif
}
int watchdog_init()
{
uchar* ctrl_addr = ( uchar* )HW_ADDR( WATCHDOG_CTRL, 0 );
watchdog_refresh();
/* Timeout 8 seconds */
*ctrl_addr = 0x07;
DEBUG_PRINT( DBG_WATCHDOG, "watchdog initialized to %c\n", ( uchar* )HW_READ( WATCHDOG_CTRL, 0 ) );
return ERR_NONE;
}
/*************************************************************************
* FUNCTION
* HW_TDMA_Enable_CTIRQ1
*
* DESCRIPTION
* This function enable TDMA module CTIRQ1.
*
* PARAMETERS
*
* RETURNS
* None
*
* GLOBALS AFFECTED
*
*************************************************************************/
void HW_TDMA_Enable_CTIRQ1(void)
{
kal_uint32 dX;
HW_TDMA_Start();
HW_WRITE(CTIRQ1, MD_DRV_TQ_CTIRQ1);
HW_WRITE(TQ_WRAP, MD_DRV_TQ_WRAP_COUNT-1);
HW_WRITE(TQ_EVENT_VALID, MD_DRV_TQ_VALIDATE_COUNT);
dX = HW_READ(EVENT_ENA(0));
dX |= 0x2;
HW_WRITE(EVENT_ENA(0), dX);
}
int clk_value( uint clk, uint* val )
{
ptr base = clk_getbase( clk );
ASSERT( val );
clkLastVal[ clk ] = HW_READ( base, TIMER_VAL_OFFSET );
*val = clkLastVal[ clk ];
// DEBUG_PRINT( "read clk %u\n", *val );
return ERR_NONE;
}
void L1D_Xmode_Latch(void)
{
unsigned short d16;
unsigned short ctrl = 0x1C3F; // SCTRL_IMOD(0,29);
unsigned long data = 0x0FBDD4D0; // CW251[D19]:DCXO_XMODE_LATCH = 0x1
volatile long addr;
unsigned long BSI_base80 = 0x83070000;
unsigned long dummy_read;
/* init BSI */
HW_WRITE( PDN_CLR2, PDN_CON_BSI );
HW_WRITE( PDN_CLR4, PDN_CON_BSI );
d16 = HW_READ( ((APBADDR) (BSI_base80+0x0C08)) ); // BSI_IO_CON
d16 &= ~( 0x1<<8 ); /* clear RESET_MODE (bit 8) */
HW_WRITE( ((APBADDR) (BSI_base80+0x0C08)), d16 ); // BSI_IO_CON
/* immediately send BSI */
HW_WRITE( ((APBADDR32)(BSI_base80+0x0000)), 0x0008001 ); // HW_WRITE( BSI_CON, SCTRL_IMOD_MAIN );
addr = (long)((APBADDR) (BSI_base80+0x0004)); // BSI_Dn_CON(0);
HW_WRITE( (APBADDR)addr, ctrl ); addr += 4;
HW_WRITE( (APBADDR32)(addr), (data) ); // HW_WRITE_BSI_DATA( addr, data );
dummy_read = HW_READ( (APBADDR32)(addr) );
HW_WRITE( ((APBADDR) (BSI_base80+0x0508)), 0x8000 ); // HW_WRITE( GSM_BSI_ACTUPT, 0x8000 );
dummy_read = HW_READ( (APBADDR32)(addr) );
(void)dummy_read;
HW_WRITE( ((APBADDR32)(BSI_base80+0x0000)), 0x8401 ); // HW_WRITE( BSI_CON, SCTRL_IMOD_SEND );
/* immediately mode end */
HW_WRITE( ((APBADDR32)(BSI_base80+0x0000)), 0x0008001 ); // HW_WRITE( BSI_CON, SCTRL_MAIN );
HW_WRITE( ((APBADDR32)(BSI_base80+0x0500)), 0xFFFFFFFF ); // MT6280 is 42
HW_WRITE( ((APBADDR32)(BSI_base80+0x0504)), 0x000003FF );
}
/*************************************************************************
* FUNCTION
* USC_Get_Int
*
* DESCRIPTION
* This function is used to get the integer value of us counter to fix the us counter hw bug.
*
* PARAMETERS
* none
*
* RETURNS
* compensated us counter value.
*
*************************************************************************/
kal_uint32 USC_Get_Int(void)
{
#if defined(MT6268_S00)
kal_uint32 ret_val,irq,duration;
irq = LockIRQ();
if( Wake_33us_TimeOut == 0 )
{
if ( Wake_Timer == 1 )
{
//Wake_Timer_Tick[Wake_Timer_Count] = (*US_RTR_Timer & 0x7FFF ) ;
if( (HW_READ(US_RTR_Timer) & 0x7FFF ) >= Wake_TimerCnt )
{
//duration = ( (*US_RTR_Timer & 0x7FFF ) - Wake_TimerCnt )*325/3072 ;
duration = (( (*US_RTR_Timer & 0x7FFF ) - Wake_TimerCnt )*6933)>>16;
}
else
{
//duration = ( 0x7FFF - Wake_TimerCnt + (*US_RTR_Timer & 0x7FFF ) )*325/3072;
duration = (( 0x7FFF - Wake_TimerCnt + (HW_READ(US_RTR_Timer) & 0x7FFF ) )*6933)>>16;
}
}
unsigned int uVtc_get_detect(void)
{
uio_handle Vtc_handle;
unsigned int detectedSize = 0;
assert(gVtcInfo.isInitialized == XIL_COMPONENT_IS_READY);
uio_get_Handler(&gVtcInfo, &Vtc_handle);
assert(Vtc_handle.IsReady == XIL_COMPONENT_IS_READY);
detectedSize = HW_READ(Vtc_handle.Control_bus_BaseAddress, VTC_DETECT);
uio_release_handle(&gVtcInfo,&Vtc_handle);
return detectedSize;
}
int clk_reset( uint clk, uint initial )
{
ptr base = clk_getbase( clk );
uint ctrlVal = 0;
int status;
ctrlVal = HW_READ( base, TIMER_CTRL_OFFSET );
status = clk_disable( clk );
ASSERT( status == ERR_NONE );
HW_WRITE( base, TIMER_LDR_OFFSET, initial );
status = clk_enable_direct( clk, ctrlVal );
ASSERT( status == ERR_NONE );
return ERR_NONE;
}
/* Receive one byte through the UART port.
Set block to 1 to busy wait until ready bit is set.
*/
static inline int console_receive( Console* cons, uchar* data, uint blocking )
{
ptr base = console_getbase( cons );
do {
if( console_ready_read( cons ) ){
*data = (uchar)HW_READ( base, UART_DATA_OFFSET );
cons->read_bytes += 1;
break;
} else if( blocking ){
continue;
} else {
return ERR_CONSOLE_NOT_READY;
}
} while( 1 );
return ERR_NONE;
}
void Frequency_hopping_enable( void )
{
#if MD_DRV_IS_UDVT_FH_SUPPORT
int d16;
sFHset FHset = { (1 << FREE_RUN_BASE), 0 }; // -1%
/*Enable DDS. Let RG_MDDS_EN[0] = 1*/
/*It is done in INT_SetPLL()*/
/*Power on TDMA*/
HW_TDMA_Start();
/*Init TQ_WRAP and Event validate*/
HW_WRITE( TQ_WRAP, MD_DRV_TQ_WRAP_COUNT-1 );
HW_WRITE( TQ_EVENT_VALID, MD_DRV_TQ_VALIDATE_COUNT );
/*Low index of FH_table_UDVT first*/
d16 = HW_READ(TDMA_FHCON(0));
d16 &= TDMA_FHCON0_MASK;
HW_WRITE( TDMA_FHCON(0), d16 );
/*MNPLL free run range*/
L1D_SET_MNPLL_FREE_RUN_RANGE();
/*EFPLL free run range*/
L1D_SET_EFPLL_FREE_RUN_RANGE();
/*MNPLL FH type*/
L1D_SET_MNPLL_FH_TYPE();
/*EFPLL FH type*/
L1D_SET_EFPLL_FH_TYPE();
/*Reset FH TDMA timer*/
ReSet_MPLLFH_FHSTR();
/*init frequency hopping table*/
FH_init_FHtable();
FH_set_fhset( 0, &FHset );
HW_WRITE( TQ_BIAS_CONT, 0 );
HW_WRITE( TDMA_FHSTR(0), 0 );
#endif
}
int clk_speed( uint clk, uint* speed )
{
ptr base = clk_getbase( clk );
uint srcSel = 0;
uint clkSpeed = 0;
srcSel = HW_READ( base, TIMER_CTRL_OFFSET ) & TIMER_CLKSEL_MASK;
switch( srcSel ){
case 0:
// SEL unset, 2kHz clock
clkSpeed = CLK_SRC_2KHZ_SPEED;
break;
case TIMER_CLKSEL_MASK:
// SEL set, 508 kHz clock
clkSpeed = CLK_SRC_508KHZ_SPEED;
break;
}
*speed = clkSpeed;
return ERR_NONE;
}
kal_uint16 L1D_HW_TDMA_GET_TQWRAP( void )
{
return HW_READ(TQ_WRAP);
}
kal_uint16 L1D_TDMA_GET_TQCNT( void )
{
return HW_READ(TQ_CURRENT_COUNT);
}
kal_uint32 L1D_HW_TDMA_GET_32KCNT( void )
{
return HW_READ(RTCCOUNT);
}
