/* * Description: * Read from RX FIFO * Round read size to block size, * and make sure data transfer will be done in one command. * * Parameters: * pintfhdl a pointer of intf_hdl * addr port ID * cnt size to read * rmem address to put data * * Return: * _SUCCESS(1) Success * _FAIL(0) Fail */ static u32 sdio_read_port( struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *mem) { PADAPTER padapter = pintfhdl->padapter; PSDIO_DATA psdio= &adapter_to_dvobj(padapter)->intf_data; HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); s32 err; HalSdioGetCmdAddr8723ASdio(padapter, addr, pHalData->SdioRxFIFOCnt++, &addr); cnt = _RND4(cnt); if (cnt > psdio->block_transfer_len) cnt = _RND(cnt, psdio->block_transfer_len); // cnt = sdio_align_size(cnt); err = _sd_read(pintfhdl, addr, cnt, mem); //err = sd_read(pintfhdl, addr, cnt, mem); if (err) return _FAIL; return _SUCCESS; }
u32 SdioLocalCmd53Read4Byte(PADAPTER padapter, u32 addr) { PSDIO_DATA psdio; u8 bMacPwrCtrlOn; u32 val; val = 0; psdio = &adapter_to_dvobj(padapter)->intf_data; HalSdioGetCmdAddr8723ASdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr); rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); if ((_FALSE == bMacPwrCtrlOn) #ifdef CONFIG_LPS_LCLK || (_TRUE == padapter->pwrctrlpriv.bFwCurrentInPSMode) #endif ) { sd_cmd52_read(psdio, addr, 4, (u8*)&val); val = le32_to_cpu(val); } else val = sd_read32(psdio, addr, NULL); return val; }
void SdioLocalCmd52Write1Byte(PADAPTER padapter, u32 addr, u8 v) { struct intf_hdl * pintfhdl; pintfhdl=&padapter->iopriv.intf; HalSdioGetCmdAddr8723ASdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr); sd_cmd52_write(pintfhdl, addr, 1, &v); }
void SdioLocalCmd52Write4Byte(PADAPTER padapter, u32 addr, u32 v) { struct intf_hdl * pintfhdl; pintfhdl=&padapter->iopriv.intf; HalSdioGetCmdAddr8723ASdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr); v = cpu_to_le32(v); sd_cmd52_write(pintfhdl, addr, 4, (u8*)&v); }
void SdioLocalCmd52Write1Byte(PADAPTER padapter, u32 addr, u8 v) { PSDIO_DATA psdio; psdio = &adapter_to_dvobj(padapter)->intf_data; HalSdioGetCmdAddr8723ASdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr); sd_cmd52_write(psdio, addr, 1, &v); }
void SdioLocalCmd52Write2Byte(PADAPTER padapter, u32 addr, u16 v) { PSDIO_DATA psdio; psdio = &adapter_to_dvobj(padapter)->intf_data; HalSdioGetCmdAddr8723ASdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr); v = cpu_to_le16(v); sd_cmd52_write(psdio, addr, 2, (u8*)&v); }
void SdioLocalCmd52Write4Byte(PADAPTER padapter, u32 addr, u32 v) { PSDIO_DATA psdio; psdio = &padapter->dvobjpriv.intf_data; HalSdioGetCmdAddr8723ASdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr); v = cpu_to_le32(v); sd_cmd52_write(psdio, addr, 4, (u8*)&v); }
/* * Description: * Read from RX FIFO * Round read size to block size, * and make sure data transfer will be done in one command. * * Parameters: * pintfhdl a pointer of intf_hdl * addr port ID * cnt size to read * rmem address to put data * * Return: * _SUCCESS(1) Success * _FAIL(0) Fail */ static u32 sdio_read_port( struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *mem) { PADAPTER padapter; PSDIO_DATA psdio; PHAL_DATA_TYPE phal; u32 oldcnt; #ifdef SDIO_DYNAMIC_ALLOC_MEM u8 *oldmem; #endif s32 err; padapter = pintfhdl->padapter; psdio = &adapter_to_dvobj(padapter)->intf_data; phal = GET_HAL_DATA(padapter); HalSdioGetCmdAddr8723ASdio(padapter, addr, phal->SdioRxFIFOCnt++, &addr); oldcnt = cnt; if (cnt > psdio->block_transfer_len) cnt = _RND(cnt, psdio->block_transfer_len); // cnt = sdio_align_size(cnt); if (oldcnt != cnt) { #ifdef SDIO_DYNAMIC_ALLOC_MEM oldmem = mem; mem = rtw_malloc(cnt); if (mem == NULL) { DBG_8192C(KERN_WARNING "%s: allocate memory %d bytes fail!\n", __func__, cnt); mem = oldmem; oldmem == NULL; } #else // in this case, caller should gurante the buffer is big enough // to receive data after alignment #endif } err = _sd_read(psdio, addr, cnt, mem); #ifdef SDIO_DYNAMIC_ALLOC_MEM if ((oldcnt != cnt) && (oldmem)) { _rtw_memcpy(oldmem, mem, oldcnt); rtw_mfree(mem, cnt); } #endif if (err) return _FAIL; return _SUCCESS; }
u8 SdioLocalCmd52Read1Byte(PADAPTER padapter, u32 addr) { struct intf_hdl * pintfhdl; u8 val = 0; pintfhdl=&padapter->iopriv.intf; HalSdioGetCmdAddr8723ASdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr); sd_cmd52_read(pintfhdl, addr, 1, &val); return val; }
u8 SdioLocalCmd52Read1Byte(PADAPTER padapter, u32 addr) { PSDIO_DATA psdio; u8 val = 0; psdio = &adapter_to_dvobj(padapter)->intf_data; HalSdioGetCmdAddr8723ASdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr); sd_cmd52_read(psdio, addr, 1, &val); return val; }
u16 SdioLocalCmd52Read2Byte(PADAPTER padapter, u32 addr) { struct intf_hdl * pintfhdl; u16 val = 0; pintfhdl=&padapter->iopriv.intf; HalSdioGetCmdAddr8723ASdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr); sd_cmd52_read(pintfhdl, addr, 2, (u8*)&val); val = le16_to_cpu(val); return val; }
u16 SdioLocalCmd52Read2Byte(PADAPTER padapter, u32 addr) { PSDIO_DATA psdio; u16 val = 0; psdio = &padapter->dvobjpriv.intf_data; HalSdioGetCmdAddr8723ASdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr); sd_cmd52_read(psdio, addr, 2, (u8*)&val); val = le16_to_cpu(val); return val; }
u32 SdioLocalCmd52Read4Byte(PADAPTER padapter, u32 addr) { PSDIO_DATA psdio; u32 val = 0; psdio = &adapter_to_dvobj(padapter)->intf_data; HalSdioGetCmdAddr8723ASdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr); sd_cmd52_read(psdio, addr, 4, (u8*)&val); val = le32_to_cpu(val); return val; }
/* * Todo: align address to 4 bytes. */ s32 sdio_local_write( PADAPTER padapter, u32 addr, u32 cnt, u8 *pbuf) { PSDIO_DATA psdio; u8 bMacPwrCtrlOn; s32 err; u8 *ptmpbuf; #ifdef CONFIG_DEBUG_RTL819X if(addr & 0x3) DBG_8192C("%s, address must be 4 bytes alignment\n", __FUNCTION__); if(cnt & 0x3) DBG_8192C("%s, size must be the multiple of 4 \n", __FUNCTION__); #endif psdio = &padapter->dvobjpriv.intf_data; HalSdioGetCmdAddr8723ASdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr); padapter->HalFunc.GetHwRegHandler(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); if ((_FALSE == bMacPwrCtrlOn) #ifdef CONFIG_LPS_LCLK || (_TRUE == padapter->pwrctrlpriv.bFwCurrentInPSMode) #endif ) { err = sd_cmd52_write(psdio, addr, cnt, pbuf); return err; } ptmpbuf = (u8*)rtw_malloc(cnt); if(!ptmpbuf) return (-1); _rtw_memcpy(ptmpbuf, pbuf, cnt); err = sd_write(psdio, addr, cnt, ptmpbuf); if (ptmpbuf) rtw_mfree(ptmpbuf, cnt); return err; }
/* * Todo: align address to 4 bytes. */ s32 sdio_local_write( PADAPTER padapter, u32 addr, u32 cnt, u8 *pbuf) { struct intf_hdl * pintfhdl; u8 bMacPwrCtrlOn; s32 err; u8 *ptmpbuf; if(addr & 0x3) DBG_8192C("%s, address must be 4 bytes alignment\n", __FUNCTION__); if(cnt & 0x3) DBG_8192C("%s, size must be the multiple of 4 \n", __FUNCTION__); pintfhdl=&padapter->iopriv.intf; HalSdioGetCmdAddr8723ASdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr); rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); if ((_FALSE == bMacPwrCtrlOn) #ifdef CONFIG_LPS_LCLK || (_TRUE == adapter_to_pwrctl(padapter)->bFwCurrentInPSMode) #endif ) { err = sd_cmd52_write(pintfhdl, addr, cnt, pbuf); return err; } ptmpbuf = (u8*)rtw_malloc(cnt); if(!ptmpbuf) return (-1); _rtw_memcpy(ptmpbuf, pbuf, cnt); err = sd_write(pintfhdl, addr, cnt, ptmpbuf); if (ptmpbuf) rtw_mfree(ptmpbuf, cnt); return err; }
/* * Todo: align address to 4 bytes. */ s32 sdio_local_read( PADAPTER padapter, u32 addr, u32 cnt, u8 *pbuf) { PSDIO_DATA psdio; u8 bMacPwrCtrlOn; s32 err; u8 *ptmpbuf; u32 n; psdio = &adapter_to_dvobj(padapter)->intf_data; HalSdioGetCmdAddr8723ASdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr); rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); if ((_FALSE == bMacPwrCtrlOn) #ifdef CONFIG_LPS_LCLK || (_TRUE == padapter->pwrctrlpriv.bFwCurrentInPSMode) #endif ) { err = sd_cmd52_read(psdio, addr, cnt, pbuf); return err; } n = RND4(cnt); ptmpbuf = (u8*)rtw_malloc(n); if (!ptmpbuf) return (-1); err = sd_read(psdio, addr, n, ptmpbuf); if (!err) _rtw_memcpy(pbuf, ptmpbuf, cnt); if (ptmpbuf) rtw_mfree(ptmpbuf, n); return err; }
/* * Todo: align address to 4 bytes. */ s32 _sdio_local_read( PADAPTER padapter, u32 addr, u32 cnt, u8 *pbuf) { struct intf_hdl * pintfhdl; u8 bMacPwrCtrlOn; s32 err; u8 *ptmpbuf; u32 n; pintfhdl=&padapter->iopriv.intf; HalSdioGetCmdAddr8723ASdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr); rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); if ((_FALSE == bMacPwrCtrlOn) #ifdef CONFIG_LPS_LCLK // || (_TRUE == adapter_to_pwrctl(padapter)->bFwCurrentInPSMode) #endif ) { err = _sd_cmd52_read(pintfhdl, addr, cnt, pbuf); return err; } n = RND4(cnt); ptmpbuf = (u8*)rtw_malloc(n); if(!ptmpbuf) return (-1); err = _sd_read(pintfhdl, addr, n, ptmpbuf); if (!err) _rtw_memcpy(pbuf, ptmpbuf, cnt); if(ptmpbuf) rtw_mfree(ptmpbuf, n); return err; }
/* * Todo: align address to 4 bytes. */ s32 _sdio_local_read( PADAPTER padapter, u32 addr, u32 cnt, u8 *pbuf) { PSDIO_DATA psdio; u8 bMacPwrCtrlOn; s32 err; u8 *ptmpbuf; u32 n; psdio = &adapter_to_dvobj(padapter)->intf_data; HalSdioGetCmdAddr8723ASdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr); rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); if (_FALSE == bMacPwrCtrlOn) { err = _sd_cmd52_read(psdio, addr, cnt, pbuf); return err; } n = RND4(cnt); ptmpbuf = (u8*)rtw_malloc(n); if (!ptmpbuf) return (-1); err = _sd_read(psdio, addr, n, ptmpbuf); if (!err) _rtw_memcpy(pbuf, ptmpbuf, cnt); if (ptmpbuf) rtw_mfree(ptmpbuf, n); return err; }
u32 SdioLocalCmd53Read4Byte(PADAPTER padapter, u32 addr) { struct intf_hdl * pintfhdl; u8 bMacPwrCtrlOn; u32 val=0; pintfhdl=&padapter->iopriv.intf; HalSdioGetCmdAddr8723ASdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr); rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); if ((_FALSE == bMacPwrCtrlOn) #ifdef CONFIG_LPS_LCLK || (_TRUE == adapter_to_pwrctl(padapter)->bFwCurrentInPSMode) #endif ) { sd_cmd52_read(pintfhdl, addr, 4, (u8*)&val); val = le32_to_cpu(val); } else val = sd_read32(pintfhdl, addr, NULL); return val; }
void sd_int_dpc(PADAPTER padapter) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); if (pHalData->sdio_hisr & SDIO_HISR_CPWM1) { struct reportpwrstate_parm report; _sdio_local_read(padapter, SDIO_REG_HCPWM1, 1, &report.state); #ifdef CONFIG_LPS_LCLK //88e's cpwm value only change BIT0, so driver need to add PS_STATE_S2 for LPS flow. //modify by Thomas. 2012/4/2. report.state |= PS_STATE_S2; //cpwm_int_hdl(padapter, &report); _set_workitem(&padapter->pwrctrlpriv.cpwm_event); #endif } if (pHalData->sdio_hisr & SDIO_HISR_TXERR) { u8 *status; u32 addr; status = _rtw_malloc(4); if (status) { addr = REG_TXDMA_STATUS; HalSdioGetCmdAddr8723ASdio(padapter, WLAN_IOREG_DEVICE_ID, addr, &addr); _sd_read(&padapter->dvobjpriv.intf_data, addr, 4, status); _sd_write(&padapter->dvobjpriv.intf_data, addr, 4, status); printk("%s: SDIO_HISR_TXERR (0x%08x)\n", __func__, le32_to_cpu(*(u32*)status)); _rtw_mfree(status, 4); } else { printk("%s: SDIO_HISR_TXERR, but can't allocate memory to read status!\n", __func__); } } if (pHalData->sdio_hisr & SDIO_HISR_TXBCNOK) { printk("%s: SDIO_HISR_TXBCNOK\n", __func__); } if (pHalData->sdio_hisr & SDIO_HISR_TXBCNERR) { printk("%s: SDIO_HISR_TXBCNERR\n", __func__); } if (pHalData->sdio_hisr & SDIO_HISR_C2HCMD) { printk("%s: C2H Command\n", __func__); } if (pHalData->sdio_hisr & SDIO_HISR_RX_REQUEST) { struct recv_buf *precvbuf; //printk("%s: RX Request, size=%d\n", __func__, phal->SdioRxFIFOSize); pHalData->sdio_hisr ^= SDIO_HISR_RX_REQUEST; #ifdef CONFIG_MAC_LOOPBACK_DRIVER sd_recv_loopback(padapter, pHalData->SdioRxFIFOSize); #else //Sometimes rx length will be zero. driver need to use cmd53 read again. if(pHalData->SdioRxFIFOSize == 0) { u8 data[4]; _sdio_local_read(padapter, SDIO_REG_RX0_REQ_LEN, 4, data); pHalData->SdioRxFIFOSize = le16_to_cpu(*(u16*)data); } if(pHalData->SdioRxFIFOSize) { precvbuf = sd_recv_rxfifo(padapter, pHalData->SdioRxFIFOSize); if (precvbuf) sd_rxhandler(padapter, precvbuf); pHalData->SdioRxFIFOSize = 0; } #endif } }
void sd_int_dpc(PADAPTER padapter) { struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); struct intf_hdl * pintfhdl=&padapter->iopriv.intf; #ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT if (pHalData->sdio_hisr & SDIO_HISR_AVAL) { //_irqL irql; u8 freepage[4]; _sdio_local_read(padapter, SDIO_REG_FREE_TXPG, 4, freepage); //_enter_critical_bh(&pHalData->SdioTxFIFOFreePageLock, &irql); //_rtw_memcpy(pHalData->SdioTxFIFOFreePage, freepage, 4); //_exit_critical_bh(&pHalData->SdioTxFIFOFreePageLock, &irql); //DBG_871X("SDIO_HISR_AVAL, Tx Free Page = 0x%x%x%x%x\n", // freepage[0], // freepage[1], // freepage[2], // freepage[3]); _rtw_up_sema(&(padapter->xmitpriv.xmit_sema)); } #endif if (pHalData->sdio_hisr & SDIO_HISR_CPWM1) { struct reportpwrstate_parm report; #ifdef CONFIG_LPS_RPWM_TIMER u8 bcancelled; _cancel_timer(&(adapter_to_pwrctl(padapter)->pwr_rpwm_timer), &bcancelled); #endif // CONFIG_LPS_RPWM_TIMER _sdio_local_read(padapter, SDIO_REG_HCPWM1, 1, &report.state); #ifdef CONFIG_LPS_LCLK //88e's cpwm value only change BIT0, so driver need to add PS_STATE_S2 for LPS flow. //modify by Thomas. 2012/4/2. #ifdef CONFIG_EXT_CLK //for sprd if(report.state & BIT(4)) //indicate FW entering 32k { u8 chk_cnt = 0; do{ if(_sdio_read8(padapter, 0x90)&BIT(0))//FW in 32k already { if(pwrpriv->rpwm < PS_STATE_S2) { //DBG_871X("disable ext clk when FW in LPS-32K already!\n"); EnableGpio5ClockReq(padapter, _TRUE, 0); } break; } chk_cnt++; }while(chk_cnt<10); if(chk_cnt==10) { DBG_871X("polling fw in 32k already, fail!\n"); } } else //indicate fw leaving 32K #endif //CONFIG_EXT_CLK { report.state |= PS_STATE_S2; //cpwm_int_hdl(padapter, &report); _set_workitem(&(pwrpriv->cpwm_event)); } #endif } #ifdef CONFIG_WOWLAN if (pHalData->sdio_hisr & SDIO_HISR_CPWM2) { u32 value; value = rtw_read32(padapter, SDIO_LOCAL_BASE+SDIO_REG_HISR); DBG_871X_LEVEL(_drv_always_, "Reset SDIO HISR(0x%08x) original:0x%08x\n", SDIO_LOCAL_BASE+SDIO_REG_HISR, value); value |= BIT19; rtw_write32(padapter, SDIO_LOCAL_BASE+SDIO_REG_HISR, value); value = rtw_read8(padapter, SDIO_LOCAL_BASE+SDIO_REG_HIMR+2); DBG_871X_LEVEL(_drv_always_, "Reset SDIO HIMR CPWM2(0x%08x) original:0x%02x\n", SDIO_LOCAL_BASE+SDIO_REG_HIMR + 2, value); } #endif if (pHalData->sdio_hisr & SDIO_HISR_TXERR) { u8 *status; u32 addr; status = rtw_malloc(4); if (status) { addr = REG_TXDMA_STATUS; HalSdioGetCmdAddr8723ASdio(padapter, WLAN_IOREG_DEVICE_ID, addr, &addr); _sd_read(pintfhdl, addr, 4, status); _sd_write(pintfhdl, addr, 4, status); DBG_8192C("%s: SDIO_HISR_TXERR (0x%08x)\n", __func__, le32_to_cpu(*(u32*)status)); rtw_mfree(status, 4); } else { DBG_8192C("%s: SDIO_HISR_TXERR, but can't allocate memory to read status!\n", __func__); } } #ifdef CONFIG_INTERRUPT_BASED_TXBCN #ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT if (pHalData->sdio_hisr & SDIO_HISR_BCNERLY_INT) #endif #ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR if (pHalData->sdio_hisr & (SDIO_HISR_TXBCNOK|SDIO_HISR_TXBCNERR)) #endif { struct mlme_priv *pmlmepriv = &padapter->mlmepriv; #if 0 //for debug if (pHalData->sdio_hisr & SDIO_HISR_BCNERLY_INT) DBG_8192C("%s: SDIO_HISR_BCNERLY_INT\n", __func__); if (pHalData->sdio_hisr & SDIO_HISR_TXBCNOK) DBG_8192C("%s: SDIO_HISR_TXBCNOK\n", __func__); if (pHalData->sdio_hisr & SDIO_HISR_TXBCNERR) DBG_8192C("%s: SDIO_HISR_TXBCNERR\n", __func__); #endif if(check_fwstate(pmlmepriv, WIFI_AP_STATE)) { //send_beacon(padapter); if(pmlmepriv->update_bcn == _TRUE) { //tx_beacon_hdl(padapter, NULL); set_tx_beacon_cmd(padapter); } } #ifdef CONFIG_CONCURRENT_MODE if(check_buddy_fwstate(padapter, WIFI_AP_STATE)) { //send_beacon(padapter); if(padapter->pbuddy_adapter->mlmepriv.update_bcn == _TRUE) { //tx_beacon_hdl(padapter, NULL); set_tx_beacon_cmd(padapter->pbuddy_adapter); } } #endif } #endif //CONFIG_INTERRUPT_BASED_TXBCN #ifdef CONFIG_EXT_CLK if (pHalData->sdio_hisr & SDIO_HISR_BCNERLY_INT) { struct mlme_priv *pmlmepriv = &padapter->mlmepriv; if(check_fwstate(pmlmepriv, _FW_LINKED) && check_fwstate(pmlmepriv, WIFI_STATION_STATE)) { //DBG_8192C("BCNERLY_INT for enabling ext clk\n"); EnableGpio5ClockReq(padapter, _TRUE, 1); } } #endif //CONFIG_EXT_CLK if (pHalData->sdio_hisr & SDIO_HISR_C2HCMD) { DBG_8192C("%s: C2H Command\n", __func__); } if (pHalData->sdio_hisr & SDIO_HISR_RX_REQUEST) { struct recv_buf *precvbuf; //DBG_8192C("%s: RX Request, size=%d\n", __func__, phal->SdioRxFIFOSize); pHalData->sdio_hisr ^= SDIO_HISR_RX_REQUEST; #ifdef CONFIG_MAC_LOOPBACK_DRIVER sd_recv_loopback(padapter, pHalData->SdioRxFIFOSize); #else do { //Sometimes rx length will be zero. driver need to use cmd53 read again. if(pHalData->SdioRxFIFOSize == 0) { u8 data[4]; _sdio_local_read(padapter, SDIO_REG_RX0_REQ_LEN, 4, data); pHalData->SdioRxFIFOSize = le16_to_cpu(*(u16*)data); } if(pHalData->SdioRxFIFOSize) { precvbuf = sd_recv_rxfifo(padapter, pHalData->SdioRxFIFOSize); pHalData->SdioRxFIFOSize = 0; if (precvbuf) sd_rxhandler(padapter, precvbuf); else break; } else break; #ifdef CONFIG_SDIO_DISABLE_RXFIFO_POLLING_LOOP } while (0); #else } while (1); #endif #endif }
void sd_int_dpc(PADAPTER padapter) { HAL_DATA_TYPE *phal; struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); phal = GET_HAL_DATA(padapter); if (phal->sdio_hisr & SDIO_HISR_CPWM1) { struct reportpwrstate_parm report; #ifdef CONFIG_LPS_RPWM_TIMER u8 bcancelled; _cancel_timer(&padapter->pwrctrlpriv.pwr_rpwm_timer, &bcancelled); #endif // CONFIG_LPS_RPWM_TIMER _sdio_local_read(padapter, SDIO_REG_HCPWM1, 1, &report.state); #ifdef CONFIG_LPS_LCLK //cpwm_int_hdl(padapter, &report); _set_workitem(&padapter->pwrctrlpriv.cpwm_event); #endif } if (phal->sdio_hisr & SDIO_HISR_TXERR) { u8 *status; u32 addr; status = rtw_malloc(4); if (status) { addr = REG_TXDMA_STATUS; HalSdioGetCmdAddr8723ASdio(padapter, WLAN_IOREG_DEVICE_ID, addr, &addr); _sd_read(&dvobj->intf_data, addr, 4, status); _sd_write(&dvobj->intf_data, addr, 4, status); DBG_8192C("%s: SDIO_HISR_TXERR (0x%08x)\n", __func__, le32_to_cpu(*(u32*)status)); rtw_mfree(status, 4); } else { DBG_8192C("%s: SDIO_HISR_TXERR, but can't allocate memory to read status!\n", __func__); } } if (phal->sdio_hisr & SDIO_HISR_TXBCNOK) { DBG_8192C("%s: SDIO_HISR_TXBCNOK\n", __func__); } if (phal->sdio_hisr & SDIO_HISR_TXBCNERR) { DBG_8192C("%s: SDIO_HISR_TXBCNERR\n", __func__); } if (phal->sdio_hisr & SDIO_HISR_C2HCMD) { struct c2h_evt_hdr *c2h_evt; if ((c2h_evt = (struct c2h_evt_hdr *)rtw_zmalloc(16)) != NULL) { if (c2h_evt_read(padapter, (u8 *)c2h_evt) == _SUCCESS) { if (c2h_id_filter_ccx_8723a(c2h_evt->id)) { /* Handle CCX report here */ rtw_hal_c2h_handler(padapter, c2h_evt); rtw_mfree((u8*)c2h_evt, 16); } else { rtw_c2h_wk_cmd(padapter, (u8 *)c2h_evt); } } else { rtw_mfree((u8*)c2h_evt, 16); } } else { /* Error handling for malloc fail */ if (rtw_cbuf_push(padapter->evtpriv.c2h_queue, (void*)NULL) != _SUCCESS) DBG_871X("%s rtw_cbuf_push fail\n", __func__); _set_workitem(&padapter->evtpriv.c2h_wk); } } if (phal->sdio_hisr & SDIO_HISR_RX_REQUEST) { struct recv_buf *precvbuf; u16 val=0; // DBG_8192C("%s: RX Request, size=%d\n", __func__, phal->SdioRxFIFOSize); phal->sdio_hisr ^= SDIO_HISR_RX_REQUEST; do{ if (phal->SdioRxFIFOSize == 0) { _sdio_local_read(padapter, SDIO_REG_RX0_REQ_LEN, 2, (u8*)&val); phal->SdioRxFIFOSize = le16_to_cpu(val); DBG_8192C("%s: RX_REQUEST, read RXFIFOsize again size=%d\n", __func__, phal->SdioRxFIFOSize); } if (phal->SdioRxFIFOSize != 0) { #ifdef CONFIG_MAC_LOOPBACK_DRIVER sd_recv_loopback(padapter, phal->SdioRxFIFOSize); #else precvbuf = sd_recv_rxfifo(padapter, phal->SdioRxFIFOSize); if (precvbuf) sd_rxhandler(padapter, precvbuf); else break; #endif } _sdio_local_read(padapter, SDIO_REG_RX0_REQ_LEN, 2, (u8*)&val); phal->SdioRxFIFOSize = le16_to_cpu(val); }while(phal->SdioRxFIFOSize !=0); } }