INIT_FUNCTION
VOID
NTAPI
HalpInitBusHandlers(VOID)
{
/* Register the HAL Bus Handler support */
HalpRegisterInternalBusHandlers();
}
BOOLEAN
HalInitSystem (
IN ULONG Phase,
IN PLOADER_PARAMETER_BLOCK LoaderBlock
)
/*++
Routine Description:
This function initializes the Hardware Architecture Layer (HAL) for a
Power PC system.
Arguments:
Phase - Supplies the initialization phase (zero or one).
LoaderBlock - Supplies a pointer to a loader parameter block.
Return Value:
A value of TRUE is returned is the initialization was successfully
complete. Otherwise a value of FALSE is returend.
--*/
{
extern KSPIN_LOCK NVRAM_Spinlock;
PKPRCB Prcb;
//
// Initialize the HAL components based on the phase of initialization
// and the processor number.
//
Prcb = PCR->Prcb;
if ((Phase == 0) || (Prcb->Number != 0)) {
if (Prcb->Number == 0)
HalpSetSystemType( LoaderBlock );
//
// Phase 0 initialization.
//
// N.B. Phase 0 initialization is executed on all processors.
//
//
// Get access to I/O space, check if I/O space has already been
// mapped by debbuger initialization.
//
if (HalpIoControlBase == NULL) {
HalpIoControlBase = (PVOID)KePhase0MapIo(IO_CONTROL_PHYSICAL_BASE, 0x20000);
if ( !HalpIoControlBase ) {
return FALSE;
}
}
//
// Initialize the display adapter. Must be done early
// so KeBugCheck() will be able to display
//
if (!HalpInitializeDisplay(LoaderBlock))
return FALSE;
// Verify that the processor block major version number conform
// to the system that is being loaded.
//
if (Prcb->MajorVersion != PRCB_MAJOR_VERSION) {
KeBugCheck(MISMATCHED_HAL);
}
//
// If processor 0 is being initialized, then initialize various
// variables, spin locks, and the display adapter.
//
if (Prcb->Number == 0) {
//
// Initialize Spinlock for NVRAM
//
KeInitializeSpinLock( &NVRAM_Spinlock );
//
// Set the interval clock increment value.
//
HalpCurrentTimeIncrement = MAXIMUM_INCREMENT;
HalpNewTimeIncrement = MAXIMUM_INCREMENT;
KeSetTimeIncrement(MAXIMUM_INCREMENT, MINIMUM_INCREMENT);
//
// Initialize all spin locks.
//
#if defined(_MP_PPC_)
KeInitializeSpinLock(&HalpBeepLock);
KeInitializeSpinLock(&HalpDisplayAdapterLock);
KeInitializeSpinLock(&HalpSystemInterruptLock);
#endif
HalpRegisterAddressUsage (&HalpDefaultIoSpace);
//
// Calibrate execution stall
//
HalpCalibrateStall();
//
// Patch KeFlushWriteBuffer to the optimum code sequence
//
HalpPatch_KeFlushWriteBuffer();
//
// Size the L2 cache
//
L2_Cache_Size = HalpSizeL2Cache();
PCR->SecondLevelIcacheSize = L2_Cache_Size << 10;
PCR->SecondLevelDcacheSize = L2_Cache_Size << 10;
//
// Compute size of PCI Configuration Space mapping
//
HalpPciConfigSize = PAGE_SIZE * ((1 << (HalpPciMaxSlots-2)) + 1);
//
// Fill in handlers for APIs which this HAL supports
//
HalQuerySystemInformation = HaliQuerySystemInformation;
HalSetSystemInformation = HaliSetSystemInformation;
HalRegisterBusHandler = HaliRegisterBusHandler;
HalHandlerForBus = HaliHandlerForBus;
HalHandlerForConfigSpace = HaliHandlerForConfigSpace;
}
//
// InitializeInterrupts
//
if (!HalpInitializeInterrupts())
return FALSE;
//
// return success
//
return TRUE;
} else {
if (Phase != 1)
return(FALSE);
//
// Phase 1 initialization.
//
// N.B. Phase 1 initialization is only executed on processor 0.
//
HalpRegisterInternalBusHandlers ();
if (!HalpAllocateMapBuffer()) {
return FALSE;
}
//
// Map I/O space and create ISA data structures.
//
if (!HalpMapIoSpace()) {
return FALSE;
}
if (!HalpCreateSioStructures()) {
return FALSE;
}
HalpCheckHardwareRevisionLevels();
HalpEnableL2Cache();
HalpEnableEagleSettings();
HalpDumpHardwareState();
HalpCopyROMs();
return TRUE;
}
}
