static int __init hdmi_probe(struct platform_device *pdev)
{
__inf("hdmi_probe call\n");
memset(&ghdmi, 0, sizeof(hdmi_info_t));
ghdmi.dev = &pdev->dev;
Hdmi_init();
return 0;
}
static int __init hdmi_probe(struct platform_device *pdev)
{
struct resource *res;
int size;
int ret = 0;
__inf("hdmi_probe call\n");
memset(&ghdmi, 0, sizeof(hdmi_info_t));
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (res == NULL)
{
__wrn("platform_get_resource fail\n");
ret = -ENXIO;
goto hdmi_error;
}
size = (res->end - res->start) + 1;
ghdmi.mem = request_mem_region(res->start, size, pdev->name);
if (ghdmi.mem == NULL)
{
__wrn("request_mem_region fail\n");
ret = -ENOENT;
goto hdmi_error;
}
ghdmi.io = ioremap(res->start, size);
if (ghdmi.io == NULL)
{
__wrn("ioremap() fail\n");
ret = -ENXIO;
goto release_mem0;
}
__inf("HDMI base 0x%08x\n", (__u32)ghdmi.io);
Hdmi_init();
Fb_Init(1);
return 0;
release_mem0:
release_resource(ghdmi.mem);
kfree(ghdmi.mem);
hdmi_error:
return ret;
}
static int __devinit hdmi_probe(struct platform_device *pdev)
{
__inf("hdmi_probe call\n");
memset(&ghdmi, 0, sizeof(hdmi_info_t));
ghdmi.base_hdmi = 0xf1c16000;
Hdmi_init();
Fb_Init(1);
return 0;
}
s32 drv_disp_init(void)
{
#ifdef CONFIG_FPGA
return 0;
#else
__disp_bsp_init_para para;
sunxi_pwm_init();
memset(¶, 0, sizeof(__disp_bsp_init_para));
#if defined(CONFIG_ARCH_SUN9IW1P1)
para.reg_base[DISP_MOD_BE0] = BE0_BASE;
para.reg_size[DISP_MOD_BE0] = 0x9fc;
para.reg_base[DISP_MOD_BE1] = BE1_BASE;
para.reg_size[DISP_MOD_BE1] = 0x9fc;
para.reg_base[DISP_MOD_BE2] = BE2_BASE;
para.reg_size[DISP_MOD_BE2] = 0x9fc;
para.reg_base[DISP_MOD_FE0] = FE0_BASE;
para.reg_size[DISP_MOD_FE0] = 0x22c;
para.reg_base[DISP_MOD_FE1] = FE1_BASE;
para.reg_size[DISP_MOD_FE1] = 0x22c;
para.reg_base[DISP_MOD_FE2] = FE2_BASE;
para.reg_size[DISP_MOD_FE2] = 0x22c;
para.reg_base[DISP_MOD_LCD0] = LCD0_BASE;
para.reg_size[DISP_MOD_LCD0] = 0x3fc;
para.reg_base[DISP_MOD_LCD1] = LCD1_BASE;
para.reg_size[DISP_MOD_LCD1] = 0x3fc;
para.reg_base[DISP_MOD_CCMU] = CCMPLL_BASE;
para.reg_size[DISP_MOD_CCMU] = 0x2dc;
para.reg_base[DISP_MOD_PIOC] = PIO_BASE;
para.reg_size[DISP_MOD_PIOC] = 0x27c;
para.reg_base[DISP_MOD_PWM] = PWM03_BASE;
para.reg_size[DISP_MOD_PWM] = 0x3c;
para.reg_base[DISP_MOD_DEU0] = DEU0_BASE;
para.reg_size[DISP_MOD_DEU0] = 0x60;
para.reg_base[DISP_MOD_DEU1] = DEU1_BASE;
para.reg_size[DISP_MOD_DEU1] = 0x60;
para.reg_base[DISP_MOD_CMU0] = BE0_BASE;
para.reg_size[DISP_MOD_CMU0] = 0xfc;
para.reg_base[DISP_MOD_CMU1] = BE1_BASE;
para.reg_size[DISP_MOD_CMU1] = 0xfc;
para.reg_base[DISP_MOD_DRC0] = DRC0_BASE;
para.reg_size[DISP_MOD_DRC0] = 0xfc;
para.reg_base[DISP_MOD_DRC1] = DRC1_BASE;
para.reg_size[DISP_MOD_DRC1] = 0xfc;
para.reg_base[DISP_MOD_DSI0] = MIPI_DSI0_BASE;
para.reg_size[DISP_MOD_DSI0] = 0x2fc;
para.reg_base[DISP_MOD_DSI0_DPHY] = MIPI_DSI0_DPHY_BASE;
para.reg_size[DISP_MOD_DSI0_DPHY] = 0xfc;
para.reg_base[DISP_MOD_HDMI] = HDMI_BASE;
para.reg_size[DISP_MOD_HDMI] = 0xfc;
para.reg_base[DISP_MOD_TOP] = REGS_AHB2_BASE;
para.reg_size[DISP_MOD_TOP] = 0xfc;
para.irq_no[DISP_MOD_BE0] = AW_IRQ_DEBE0;
para.irq_no[DISP_MOD_BE1] = AW_IRQ_DEBE1;
para.irq_no[DISP_MOD_BE2] = AW_IRQ_DEBE2;
para.irq_no[DISP_MOD_FE0] = AW_IRQ_DEFE0;
para.irq_no[DISP_MOD_FE1] = AW_IRQ_DEFE1;
para.irq_no[DISP_MOD_DRC0] = AW_IRQ_DRC01;
para.irq_no[DISP_MOD_DRC1] = AW_IRQ_DEU01;
para.irq_no[DISP_MOD_LCD0] = AW_IRQ_LCD0;
para.irq_no[DISP_MOD_LCD1] = AW_IRQ_LCD1;
para.irq_no[DISP_MOD_DSI0] = AW_IRQ_MIPIDSI;
para.irq_no[DISP_MOD_EDP] = AW_IRQ_EDP;
#elif defined(CONFIG_ARCH_SUN8IW5P1)
para.reg_base[DISP_MOD_BE0] = DEBE0_BASE;
para.reg_size[DISP_MOD_BE0] = 0xfc;
para.reg_base[DISP_MOD_FE0] = DEFE0_BASE;
para.reg_size[DISP_MOD_FE0] = 0x22c;
para.reg_base[DISP_MOD_LCD0] = LCD0_BASE;
para.reg_size[DISP_MOD_LCD0] = 0x3fc;
para.reg_base[DISP_MOD_DRC0] = DRC0_BASE;
para.reg_size[DISP_MOD_DRC0] = 0xfc;
para.reg_base[DISP_MOD_DSI0] = MIPI_DSI0_BASE;
para.reg_size[DISP_MOD_DSI0] = 0x2fc;
para.reg_base[DISP_MOD_DSI0_DPHY] = MIPI_DSI0PHY_BASE;
para.reg_size[DISP_MOD_DSI0_DPHY] = 0xfc;
para.reg_base[DISP_MOD_CCMU] = CCM_BASE;
para.reg_size[DISP_MOD_CCMU] = 0x2dc;
para.reg_base[DISP_MOD_PIOC] = PIO_BASE;
para.reg_size[DISP_MOD_PIOC] = 0x27c;
para.reg_base[DISP_MOD_PWM] = PWM03_BASE;
para.reg_size[DISP_MOD_PWM] = 0x3c;
para.reg_base[DISP_MOD_WB0] = DRC0_BASE+ 0x200;
para.reg_size[DISP_MOD_WB0] = 0x2fc;
para.reg_base[DISP_MOD_SAT0] = SAT0_BASE;
para.reg_size[DISP_MOD_SAT0] = 0x2fc;
para.irq_no[DISP_MOD_BE0] = AW_IRQ_DEBE0;
para.irq_no[DISP_MOD_LCD0] = AW_IRQ_LCD0;
para.irq_no[DISP_MOD_DSI0] = AW_IRQ_MIPIDSI;
#endif
memset(&g_disp_drv, 0, sizeof(disp_drv_info));
bsp_disp_init(¶);
#if (defined(CONFIG_ARCH_TV) && defined(CONFIG_ARCH_SUN9IW1P1))
gm7121_module_init();
#endif //#if defined(CONFIG_ARCH_TV)
#if ((defined CONFIG_SUN6I) || (defined CONFIG_ARCH_SUN8IW1P1) || (defined CONFIG_ARCH_SUN9IW1P1))
Hdmi_init();
#endif
bsp_disp_open();
lcd_init();
init_flag = 1;
__inf("DRV_DISP_Init end\n");
return 0;
#endif
}
s32 drv_disp_init(void)
{
#ifdef CONFIG_FPGA
return 0;
#else
disp_bsp_init_para para;
int disp, num_screens;
drv_disp_check_spec();
sunxi_pwm_init();
disp_sys_clk_init();
memset(¶, 0, sizeof(disp_bsp_init_para));
para.reg_base[DISP_MOD_DE] = DE_BASE;
para.reg_size[DISP_MOD_DE] = DE_SIZE;
para.reg_base[DISP_MOD_LCD0] = LCD0_BASE;
para.reg_size[DISP_MOD_LCD0] = 0x3fc;
#ifdef DISP_DEVICE_NUM
#if DISP_DEVICE_NUM == 2
para.reg_base[DISP_MOD_LCD1] = LCD1_BASE;
para.reg_size[DISP_MOD_LCD1] = 0x3fc;
#endif
#else
# error "DEVICE_NUM undefined!"
#endif
#ifdef SUPPORT_DSI
para.reg_base[DISP_MOD_DSI0] = MIPI_DSI0_BASE;
para.reg_size[DISP_MOD_DSI0] = 0x2fc;
#endif
para.irq_no[DISP_MOD_DE] = AW_IRQ_DEIRQ0;
para.irq_no[DISP_MOD_LCD0] = AW_IRQ_LCD0;
#if defined(DISP_DEVICE_NUM)
#if DISP_DEVICE_NUM == 2
para.irq_no[DISP_MOD_LCD1] = AW_IRQ_LCD1;
#endif
#else
# error "DEVICE_NUM undefined!"
#endif
#if defined(SUPPORT_DSI)
para.irq_no[DISP_MOD_DSI0] = AW_IRQ_MIPIDSI;
#endif
memset(&g_disp_drv, 0, sizeof(disp_drv_info));
bsp_disp_init(¶);
num_screens = bsp_disp_feat_get_num_screens();
for(disp=0; disp<num_screens; disp++) {
g_disp_drv.mgr[disp] = disp_get_layer_manager(disp);
}
#if defined(SUPPORT_HDMI)
Hdmi_init();
#endif
#if defined(SUPPORT_TV)
tv_init();
#endif
#if defined(CONFIG_USE_AC200)
tv_ac200_init();
#endif
bsp_disp_open();
lcd_init();
#if defined(CVBS_MODE_USED_GM7121)
gm7121_module_init();
#endif
init_flag = 1;
printf("DRV_DISP_Init end\n");
return 0;
#endif
}