static void
i915_emit_invarient_state(struct intel_context *intel)
{
BATCH_LOCALS;
BEGIN_BATCH(200, 0);
OUT_BATCH(_3DSTATE_AA_CMD |
AA_LINE_ECAAR_WIDTH_ENABLE |
AA_LINE_ECAAR_WIDTH_1_0 |
AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);
OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
OUT_BATCH(0);
OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
OUT_BATCH(0);
OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
OUT_BATCH(0);
/* Don't support texture crossbar yet */
OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS |
CSB_TCB(0, 0) |
CSB_TCB(1, 1) |
CSB_TCB(2, 2) |
CSB_TCB(3, 3) |
CSB_TCB(4, 4) | CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7));
OUT_BATCH(_3DSTATE_RASTER_RULES_CMD |
ENABLE_POINT_RASTER_RULE |
OGL_POINT_RASTER_RULE |
ENABLE_LINE_STRIP_PROVOKE_VRTX |
ENABLE_TRI_FAN_PROVOKE_VRTX |
LINE_STRIP_PROVOKE_VRTX(1) |
TRI_FAN_PROVOKE_VRTX(2) | ENABLE_TEXKILL_3D_4D | TEXKILL_4D);
/* Need to initialize this to zero.
*/
OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | (1));
OUT_BATCH(0);
/* XXX: Use this */
OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD);
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(_3DSTATE_DEPTH_SUBRECT_DISABLE);
OUT_BATCH(_3DSTATE_LOAD_INDIRECT | 0); /* disable indirect state */
OUT_BATCH(0);
/* Don't support twosided stencil yet */
OUT_BATCH(_3DSTATE_BACKFACE_STENCIL_OPS | BFO_ENABLE_STENCIL_TWO_SIDE | 0);
ADVANCE_BATCH();
}
void gen2_render_copyfunc(struct intel_batchbuffer *batch,
drm_intel_context *context,
struct igt_buf *src, unsigned src_x, unsigned src_y,
unsigned width, unsigned height,
struct igt_buf *dst, unsigned dst_x, unsigned dst_y)
{
gen2_emit_invariant(batch);
gen2_emit_copy_pipeline(batch);
gen2_emit_target(batch, dst);
gen2_emit_texture(batch, src, 0);
OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 |
I1_LOAD_S(2) | I1_LOAD_S(3) | I1_LOAD_S(8) | 2);
OUT_BATCH(1<<12);
OUT_BATCH(S3_CULLMODE_NONE | S3_VERTEXHAS_XY);
OUT_BATCH(S8_ENABLE_COLOR_BUFFER_WRITE);
OUT_BATCH(_3DSTATE_VERTEX_FORMAT_2_CMD | TEXCOORDFMT_2D << 0);
OUT_BATCH(PRIM3D_INLINE | PRIM3D_RECTLIST | (3*4 -1));
emit_vertex(batch, dst_x + width);
emit_vertex(batch, dst_y + height);
emit_vertex_normalized(batch, src_x + width, igt_buf_width(src));
emit_vertex_normalized(batch, src_y + height, igt_buf_height(src));
emit_vertex(batch, dst_x);
emit_vertex(batch, dst_y + height);
emit_vertex_normalized(batch, src_x, igt_buf_width(src));
emit_vertex_normalized(batch, src_y + height, igt_buf_height(src));
emit_vertex(batch, dst_x);
emit_vertex(batch, dst_y);
emit_vertex_normalized(batch, src_x, igt_buf_width(src));
emit_vertex_normalized(batch, src_y, igt_buf_height(src));
intel_batchbuffer_flush(batch);
}
static void
i915_emit_invarient_state(struct intel_context *intel)
{
BATCH_LOCALS;
BEGIN_BATCH(17);
OUT_BATCH(_3DSTATE_AA_CMD |
AA_LINE_ECAAR_WIDTH_ENABLE |
AA_LINE_ECAAR_WIDTH_1_0 |
AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);
OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
OUT_BATCH(0);
OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
OUT_BATCH(0);
OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
OUT_BATCH(0);
/* Don't support texture crossbar yet */
OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS |
CSB_TCB(0, 0) |
CSB_TCB(1, 1) |
CSB_TCB(2, 2) |
CSB_TCB(3, 3) |
CSB_TCB(4, 4) | CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7));
/* Need to initialize this to zero.
*/
OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | (0));
OUT_BATCH(0);
OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD);
OUT_BATCH(0);
OUT_BATCH(0);
/* XXX: Use this */
OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
OUT_BATCH(_3DSTATE_DEPTH_SUBRECT_DISABLE);
OUT_BATCH(_3DSTATE_LOAD_INDIRECT | 0); /* disable indirect state */
OUT_BATCH(0);
ADVANCE_BATCH();
}
void
i915_vertex_flush(intel_screen_private *intel)
{
if (intel->prim_offset == 0)
return;
intel->batch_ptr[intel->prim_offset] |= intel->vertex_count;
intel->prim_offset = 0;
if (intel->needs_render_ca_pass) {
OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(6) | 0);
OUT_BATCH(i915_get_blend_cntl(PictOpAdd,
intel->render_mask_picture,
intel->render_dest_picture->format));
i915_composite_emit_shader(intel, PictOpAdd);
OUT_BATCH(PRIM3D_RECTLIST | PRIM3D_INDIRECT_SEQUENTIAL | intel->vertex_count);
OUT_BATCH(intel->vertex_index);
}
intel->vertex_index += intel->vertex_count;
intel->vertex_count = 0;
}
/* Push the state into the sarea and/or texture memory.
*/
void
i915_emit_hardware_state(struct i915_context *i915 )
{
/* XXX: there must be an easier way */
const unsigned dwords = ( 14 +
7 +
I915_MAX_DYNAMIC +
8 +
2 + I915_TEX_UNITS*3 +
2 + I915_TEX_UNITS*3 +
2 + I915_MAX_CONSTANT*4 +
#if 0
i915->current.program_len +
#else
i915->fs->program_len +
#endif
6
) * 3/2; /* plus 50% margin */
const unsigned relocs = ( I915_TEX_UNITS +
3
) * 3/2; /* plus 50% margin */
#if 0
debug_printf("i915_emit_hardware_state: %d dwords, %d relocs\n", dwords, relocs);
#endif
if(!BEGIN_BATCH(dwords, relocs)) {
FLUSH_BATCH(NULL);
assert(BEGIN_BATCH(dwords, relocs));
}
/* 14 dwords, 0 relocs */
if (i915->hardware_dirty & I915_HW_INVARIENT)
{
OUT_BATCH(_3DSTATE_AA_CMD |
AA_LINE_ECAAR_WIDTH_ENABLE |
AA_LINE_ECAAR_WIDTH_1_0 |
AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);
OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
OUT_BATCH(0);
OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
OUT_BATCH(0);
OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
OUT_BATCH(0);
OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS |
CSB_TCB(0, 0) |
CSB_TCB(1, 1) |
CSB_TCB(2, 2) |
CSB_TCB(3, 3) |
CSB_TCB(4, 4) |
CSB_TCB(5, 5) |
CSB_TCB(6, 6) |
CSB_TCB(7, 7));
OUT_BATCH(_3DSTATE_RASTER_RULES_CMD |
ENABLE_POINT_RASTER_RULE |
OGL_POINT_RASTER_RULE |
ENABLE_LINE_STRIP_PROVOKE_VRTX |
ENABLE_TRI_FAN_PROVOKE_VRTX |
LINE_STRIP_PROVOKE_VRTX(1) |
TRI_FAN_PROVOKE_VRTX(2) |
ENABLE_TEXKILL_3D_4D |
TEXKILL_4D);
/* Need to initialize this to zero.
*/
OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | (0));
OUT_BATCH(0);
OUT_BATCH(_3DSTATE_DEPTH_SUBRECT_DISABLE);
/* disable indirect state for now
*/
OUT_BATCH(_3DSTATE_LOAD_INDIRECT | 0);
OUT_BATCH(0);
}
/* 7 dwords, 1 relocs */
if (i915->hardware_dirty & I915_HW_IMMEDIATE)
{
OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 |
I1_LOAD_S(0) |
I1_LOAD_S(1) |
I1_LOAD_S(2) |
I1_LOAD_S(4) |
I1_LOAD_S(5) |
I1_LOAD_S(6) |
(5));
if(i915->vbo)
OUT_RELOC(i915->vbo,
I915_BUFFER_ACCESS_READ,
i915->current.immediate[I915_IMMEDIATE_S0]);
else
/* FIXME: we should not do this */
OUT_BATCH(0);
OUT_BATCH(i915->current.immediate[I915_IMMEDIATE_S1]);
OUT_BATCH(i915->current.immediate[I915_IMMEDIATE_S2]);
OUT_BATCH(i915->current.immediate[I915_IMMEDIATE_S4]);
OUT_BATCH(i915->current.immediate[I915_IMMEDIATE_S5]);
OUT_BATCH(i915->current.immediate[I915_IMMEDIATE_S6]);
}
/* I915_MAX_DYNAMIC dwords, 0 relocs */
if (i915->hardware_dirty & I915_HW_DYNAMIC)
{
int i;
for (i = 0; i < I915_MAX_DYNAMIC; i++) {
OUT_BATCH(i915->current.dynamic[i]);
}
}
/* 8 dwords, 2 relocs */
if (i915->hardware_dirty & I915_HW_STATIC)
{
struct pipe_surface *cbuf_surface = i915->framebuffer.cbufs[0];
struct pipe_surface *depth_surface = i915->framebuffer.zsbuf;
if (cbuf_surface) {
unsigned cpitch = cbuf_surface->stride;
unsigned ctile = BUF_3D_USE_FENCE;
if (cbuf_surface->texture &&
((struct i915_texture*)(cbuf_surface->texture))->tiled) {
ctile = BUF_3D_TILED_SURFACE;
}
OUT_BATCH(_3DSTATE_BUF_INFO_CMD);
OUT_BATCH(BUF_3D_ID_COLOR_BACK |
BUF_3D_PITCH(cpitch) | /* pitch in bytes */
ctile);
OUT_RELOC(cbuf_surface->buffer,
I915_BUFFER_ACCESS_WRITE,
cbuf_surface->offset);
}
/* What happens if no zbuf??
*/
if (depth_surface) {
unsigned zpitch = depth_surface->stride;
unsigned ztile = BUF_3D_USE_FENCE;
if (depth_surface->texture &&
((struct i915_texture*)(depth_surface->texture))->tiled) {
ztile = BUF_3D_TILED_SURFACE;
}
OUT_BATCH(_3DSTATE_BUF_INFO_CMD);
OUT_BATCH(BUF_3D_ID_DEPTH |
BUF_3D_PITCH(zpitch) | /* pitch in bytes */
ztile);
OUT_RELOC(depth_surface->buffer,
I915_BUFFER_ACCESS_WRITE,
depth_surface->offset);
}
{
unsigned cformat, zformat = 0;
if (cbuf_surface)
cformat = cbuf_surface->format;
else
cformat = PIPE_FORMAT_A8R8G8B8_UNORM; /* arbitrary */
cformat = translate_format(cformat);
if (depth_surface)
zformat = translate_depth_format( i915->framebuffer.zsbuf->format );
OUT_BATCH(_3DSTATE_DST_BUF_VARS_CMD);
OUT_BATCH(DSTORG_HORT_BIAS(0x8) | /* .5 */
DSTORG_VERT_BIAS(0x8) | /* .5 */
LOD_PRECLAMP_OGL |
TEX_DEFAULT_COLOR_OGL |
cformat |
zformat );
}
}
#if 01
/* texture images */
/* 2 + I915_TEX_UNITS*3 dwords, I915_TEX_UNITS relocs */
if (i915->hardware_dirty & (I915_HW_MAP | I915_HW_SAMPLER))
{
const uint nr = i915->current.sampler_enable_nr;
if (nr) {
const uint enabled = i915->current.sampler_enable_flags;
uint unit;
uint count = 0;
OUT_BATCH(_3DSTATE_MAP_STATE | (3 * nr));
OUT_BATCH(enabled);
for (unit = 0; unit < I915_TEX_UNITS; unit++) {
if (enabled & (1 << unit)) {
struct pipe_buffer *buf =
i915->texture[unit]->buffer;
uint offset = 0;
assert(buf);
count++;
OUT_RELOC(buf,
I915_BUFFER_ACCESS_READ,
offset);
OUT_BATCH(i915->current.texbuffer[unit][0]); /* MS3 */
OUT_BATCH(i915->current.texbuffer[unit][1]); /* MS4 */
}
}
assert(count == nr);
}
}
#endif
#if 01
/* samplers */
/* 2 + I915_TEX_UNITS*3 dwords, 0 relocs */
if (i915->hardware_dirty & I915_HW_SAMPLER)
{
if (i915->current.sampler_enable_nr) {
int i;
OUT_BATCH( _3DSTATE_SAMPLER_STATE |
(3 * i915->current.sampler_enable_nr) );
OUT_BATCH( i915->current.sampler_enable_flags );
for (i = 0; i < I915_TEX_UNITS; i++) {
if (i915->current.sampler_enable_flags & (1<<i)) {
OUT_BATCH( i915->current.sampler[i][0] );
OUT_BATCH( i915->current.sampler[i][1] );
OUT_BATCH( i915->current.sampler[i][2] );
}
}
}
}
#endif
/* constants */
/* 2 + I915_MAX_CONSTANT*4 dwords, 0 relocs */
if (i915->hardware_dirty & I915_HW_PROGRAM)
{
/* Collate the user-defined constants with the fragment shader's
* immediates according to the constant_flags[] array.
*/
const uint nr = i915->fs->num_constants;
if (nr) {
uint i;
OUT_BATCH( _3DSTATE_PIXEL_SHADER_CONSTANTS | (nr * 4) );
OUT_BATCH( (1 << (nr - 1)) | ((1 << (nr - 1)) - 1) );
for (i = 0; i < nr; i++) {
const uint *c;
if (i915->fs->constant_flags[i] == I915_CONSTFLAG_USER) {
/* grab user-defined constant */
c = (uint *) i915->current.constants[PIPE_SHADER_FRAGMENT][i];
}
else {
/* emit program constant */
c = (uint *) i915->fs->constants[i];
}
#if 0 /* debug */
{
float *f = (float *) c;
printf("Const %2d: %f %f %f %f %s\n", i, f[0], f[1], f[2], f[3],
(i915->fs->constant_flags[i] == I915_CONSTFLAG_USER
? "user" : "immediate"));
}
#endif
OUT_BATCH(*c++);
OUT_BATCH(*c++);
OUT_BATCH(*c++);
OUT_BATCH(*c++);
}
}
}
/* Fragment program */
/* i915->current.program_len dwords, 0 relocs */
if (i915->hardware_dirty & I915_HW_PROGRAM)
{
uint i;
/* we should always have, at least, a pass-through program */
assert(i915->fs->program_len > 0);
for (i = 0; i < i915->fs->program_len; i++) {
OUT_BATCH(i915->fs->program[i]);
}
}
/* drawing surface size */
/* 6 dwords, 0 relocs */
{
uint w, h;
boolean k = framebuffer_size(&i915->framebuffer, &w, &h);
(void)k;
assert(k);
OUT_BATCH(_3DSTATE_DRAW_RECT_CMD);
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(((w - 1) & 0xffff) | ((h - 1) << 16));
OUT_BATCH(0);
OUT_BATCH(0);
}
i915->hardware_dirty = 0;
}
static void i915_emit_composite_setup(ScrnInfoPtr scrn)
{
intel_screen_private *intel = intel_get_screen_private(scrn);
int op = intel->i915_render_state.op;
PicturePtr mask_picture = intel->render_mask_picture;
PicturePtr dest_picture = intel->render_dest_picture;
PixmapPtr mask = intel->render_mask;
PixmapPtr dest = intel->render_dest;
Bool is_solid_src, is_solid_mask;
int tex_count, t;
intel->needs_render_state_emit = FALSE;
IntelEmitInvarientState(scrn);
intel->last_3d = LAST_3D_RENDER;
is_solid_src = intel->render_source_is_solid;
is_solid_mask = intel->render_mask_is_solid;
tex_count = 0;
tex_count += ! is_solid_src;
tex_count += mask && ! is_solid_mask;
assert(intel->in_batch_atomic);
if (tex_count != 0) {
OUT_BATCH(_3DSTATE_MAP_STATE | (3 * tex_count));
OUT_BATCH((1 << tex_count) - 1);
for (t = 0; t < tex_count; t++) {
OUT_RELOC_PIXMAP(intel->texture[t], I915_GEM_DOMAIN_SAMPLER, 0, 0);
OUT_BATCH(intel->mapstate[3*t + 1]);
OUT_BATCH(intel->mapstate[3*t + 2]);
}
OUT_BATCH(_3DSTATE_SAMPLER_STATE | (3 * tex_count));
OUT_BATCH((1 << tex_count) - 1);
for (t = 0; t < tex_count; t++) {
OUT_BATCH(intel->samplerstate[3*t + 0]);
OUT_BATCH(intel->samplerstate[3*t + 1]);
OUT_BATCH(intel->samplerstate[3*t + 2]);
}
}
if (is_solid_src) {
OUT_BATCH (_3DSTATE_DFLT_DIFFUSE_CMD);
OUT_BATCH (intel->render_source_solid);
}
if (mask && is_solid_mask) {
OUT_BATCH (_3DSTATE_DFLT_SPEC_CMD);
OUT_BATCH (intel->render_mask_solid);
}
/* BUF_INFO is an implicit flush, so avoid if the target has not changed.
* XXX However for reasons unfathomed, correct rendering in KDE requires
* at least a MI_FLUSH | INHIBIT_RENDER_CACHE_FLUSH here.
*/
if (1 || dest != intel->render_current_dest) {
uint32_t tiling_bits;
intel_batch_do_flush(scrn);
if (intel_pixmap_tiled(dest)) {
tiling_bits = BUF_3D_TILED_SURFACE;
if (intel_get_pixmap_private(dest)->tiling
== I915_TILING_Y)
tiling_bits |= BUF_3D_TILE_WALK_Y;
} else
tiling_bits = 0;
OUT_BATCH(_3DSTATE_BUF_INFO_CMD);
OUT_BATCH(BUF_3D_ID_COLOR_BACK | tiling_bits |
BUF_3D_PITCH(intel_pixmap_pitch(dest)));
OUT_RELOC_PIXMAP(dest, I915_GEM_DOMAIN_RENDER,
I915_GEM_DOMAIN_RENDER, 0);
OUT_BATCH(_3DSTATE_DST_BUF_VARS_CMD);
OUT_BATCH(intel->i915_render_state.dst_format);
/* draw rect is unconditional */
OUT_BATCH(_3DSTATE_DRAW_RECT_CMD);
OUT_BATCH(0x00000000);
OUT_BATCH(0x00000000); /* ymin, xmin */
OUT_BATCH(DRAW_YMAX(dest->drawable.height - 1) |
DRAW_XMAX(dest->drawable.width - 1));
/* yorig, xorig (relate to color buffer?) */
OUT_BATCH(0x00000000);
intel->render_current_dest = dest;
}
{
uint32_t ss2;
ss2 = ~0;
t = 0;
if (! is_solid_src) {
ss2 &= ~S2_TEXCOORD_FMT(t, TEXCOORDFMT_NOT_PRESENT);
ss2 |= S2_TEXCOORD_FMT(t,
intel_transform_is_affine(intel->transform[t]) ?
TEXCOORDFMT_2D : TEXCOORDFMT_4D);
t++;
}
if (mask && ! is_solid_mask) {
ss2 &= ~S2_TEXCOORD_FMT(t, TEXCOORDFMT_NOT_PRESENT);
ss2 |= S2_TEXCOORD_FMT(t,
intel_transform_is_affine(intel->transform[t]) ?
TEXCOORDFMT_2D : TEXCOORDFMT_4D);
t++;
}
if (intel->needs_render_ca_pass) {
OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(2) | 0);
OUT_BATCH(ss2);
} else {
OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(2) | I1_LOAD_S(6) | 1);
OUT_BATCH(ss2);
OUT_BATCH(i915_get_blend_cntl(op, mask_picture, dest_picture->format));
}
}
if (! intel->needs_render_ca_pass)
i915_composite_emit_shader(intel, op);
}
void
i915_composite(PixmapPtr dest, int srcX, int srcY, int maskX, int maskY,
int dstX, int dstY, int w, int h)
{
ScrnInfoPtr scrn = xf86Screens[dest->drawable.pScreen->myNum];
intel_screen_private *intel = intel_get_screen_private(scrn);
/* 28 + 16 + 10 + 20 + 32 + 16 */
intel_batch_start_atomic(scrn, 150);
if (intel->needs_render_state_emit)
i915_emit_composite_setup(scrn);
if (intel->needs_render_vertex_emit ||
intel_vertex_space(intel) < 3*4*intel->floats_per_vertex) {
i915_vertex_flush(intel);
if (intel_vertex_space(intel) < 256) {
intel_next_vertex(intel);
OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 |
I1_LOAD_S(0) | I1_LOAD_S(1) | 1);
OUT_RELOC(intel->vertex_bo, I915_GEM_DOMAIN_VERTEX, 0, 0);
OUT_BATCH((intel->floats_per_vertex << S1_VERTEX_WIDTH_SHIFT) |
(intel->floats_per_vertex << S1_VERTEX_PITCH_SHIFT));
intel->vertex_index = 0;
} else if (intel->floats_per_vertex != intel->last_floats_per_vertex){
OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 |
I1_LOAD_S(1) | 0);
OUT_BATCH((intel->floats_per_vertex << S1_VERTEX_WIDTH_SHIFT) |
(intel->floats_per_vertex << S1_VERTEX_PITCH_SHIFT));
intel->vertex_index =
(intel->vertex_used + intel->floats_per_vertex - 1) / intel->floats_per_vertex;
intel->vertex_used = intel->vertex_index * intel->floats_per_vertex;
}
intel->last_floats_per_vertex = intel->floats_per_vertex;
intel->needs_render_vertex_emit = FALSE;
}
if (intel->prim_offset == 0) {
if (intel->needs_render_ca_pass) {
OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(6) | 0);
OUT_BATCH(i915_get_blend_cntl(PictOpOutReverse,
intel->render_mask_picture,
intel->render_dest_picture->format));
i915_composite_emit_shader(intel, PictOpOutReverse);
}
intel->prim_offset = intel->batch_used;
OUT_BATCH(PRIM3D_RECTLIST | PRIM3D_INDIRECT_SEQUENTIAL);
OUT_BATCH(intel->vertex_index);
}
intel->vertex_count += 3;
intel->prim_emit(intel,
srcX, srcY,
maskX, maskY,
dstX, dstY,
w, h);
intel_batch_end_atomic(scrn);
}
BOOL copybox3d( GMABitMap_t *bm_dst, GMABitMap_t *bm_src,
ULONG dst_x,ULONG dst_y,ULONG dst_width, ULONG dst_height,
ULONG src_x,ULONG src_y,ULONG src_width, ULONG src_height )
{
uint32_t dst_format;
uint32_t src_format;
if( !copybox3d_supported() )
{
return FALSE;
}
// buffers in gfx memory ?
if( ! (bm_src->fbgfx && bm_src->fbgfx) )
{
return FALSE;
}
// Max texture size, src and dst must be differend (at least if overlaps)
if( bm_src->pitch/4 > 2048 || bm_src->height > 2048 || bm_dst == bm_src )
{
return FALSE;
}
// src pitch must be long aligmented.
if( bm_src->pitch & 0x3 )
{
bug("[IntelGMA] copybox3d: ERROR bm_src->pitch=%d/n",bm_src->pitch);
return FALSE;
}
if(bm_src->bpp == 4)
{
src_format = MAPSURF_32BIT | MT_32BIT_ARGB8888;
}
else if(bm_src->bpp == 2)
{
src_format = MAPSURF_16BIT | MT_16BIT_RGB565;
}
else
{
bug("[IntelGMA] copybox3d: ERROR src_bpp=%d/n",bm_src->bpp);
return FALSE;
}
if(bm_dst->bpp == 4)
{
dst_format = COLOR_BUF_ARGB8888;
}
else if(bm_dst->bpp == 2)
{
dst_format = COLOR_BUF_RGB565;
}
else
{
bug("[IntelGMA] copybox3d: ERROR dst_bpp=%d/n",bm_dst->bpp);
return FALSE;
}
D(bug("[IntelGMA:HW] %s()\n", __func__));
LOCK_HW
START_RING(72);
/* invariant state */
OUT_RING( _3DSTATE_AA_CMD |
AA_LINE_ECAAR_WIDTH_ENABLE |
AA_LINE_ECAAR_WIDTH_1_0 |
AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0 );
OUT_RING( _3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD |
IAB_MODIFY_ENABLE |
IAB_MODIFY_FUNC | (BLENDFUNC_ADD << IAB_FUNC_SHIFT) |
IAB_MODIFY_SRC_FACTOR | (BLENDFACT_ONE <<
IAB_SRC_FACTOR_SHIFT) |
IAB_MODIFY_DST_FACTOR | (BLENDFACT_ZERO <<
IAB_DST_FACTOR_SHIFT) );
OUT_RING( _3DSTATE_DFLT_DIFFUSE_CMD );
OUT_RING( 0 );
OUT_RING( _3DSTATE_DFLT_SPEC_CMD );
OUT_RING( 0 );
OUT_RING( _3DSTATE_DFLT_Z_CMD );
OUT_RING( 0 );
OUT_RING( _3DSTATE_COORD_SET_BINDINGS |
CSB_TCB(0, 0) |
CSB_TCB(1, 1) |
CSB_TCB(2, 2) |
CSB_TCB(3, 3) |
CSB_TCB(4, 4) |
CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7) );
OUT_RING( _3DSTATE_RASTER_RULES_CMD |
ENABLE_POINT_RASTER_RULE |
OGL_POINT_RASTER_RULE |
ENABLE_LINE_STRIP_PROVOKE_VRTX |
ENABLE_TRI_FAN_PROVOKE_VRTX |
LINE_STRIP_PROVOKE_VRTX(1) |
TRI_FAN_PROVOKE_VRTX(2) | ENABLE_TEXKILL_3D_4D | TEXKILL_4D );
OUT_RING( _3DSTATE_MODES_4_CMD |
ENABLE_LOGIC_OP_FUNC | LOGIC_OP_FUNC(LOGICOP_COPY) |
ENABLE_STENCIL_WRITE_MASK | STENCIL_WRITE_MASK(0xff) |
ENABLE_STENCIL_TEST_MASK | STENCIL_TEST_MASK(0xff) );
OUT_RING( _3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | I1_LOAD_S(4) | I1_LOAD_S(5) | 2 );
OUT_RING( 0x00000000 ); /* Disable texture coordinate wrap-shortest */
OUT_RING( (1 << S4_POINT_WIDTH_SHIFT) |
S4_LINE_WIDTH_ONE |
S4_CULLMODE_NONE |
S4_VFMT_XY );
OUT_RING( 0x00000000 ); /* Stencil. */
OUT_RING( _3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT );
OUT_RING( _3DSTATE_SCISSOR_RECT_0_CMD );
OUT_RING( 0 );
OUT_RING( 0 );
OUT_RING( _3DSTATE_DEPTH_SUBRECT_DISABLE );
OUT_RING( _3DSTATE_LOAD_INDIRECT | 0 ); /* disable indirect state */
OUT_RING( 0 );
OUT_RING( _3DSTATE_STIPPLE );
OUT_RING( 0x00000000 );
OUT_RING( _3DSTATE_BACKFACE_STENCIL_OPS | BFO_ENABLE_STENCIL_TWO_SIDE | 0 );
/* samler state */
#define TEX_COUNT 1
OUT_RING( _3DSTATE_MAP_STATE | (3 * TEX_COUNT) );
OUT_RING( (1 << TEX_COUNT) - 1 );
// Source buffer
OUT_RING( bm_src->framebuffer );
OUT_RING( src_format |
(bm_src->height - 1) << MS3_HEIGHT_SHIFT |
(bm_src->pitch/bm_src->bpp - 1) << MS3_WIDTH_SHIFT );
OUT_RING( (bm_src->pitch/4 -1) << MS4_PITCH_SHIFT );
OUT_RING( _3DSTATE_SAMPLER_STATE | (3 * TEX_COUNT) );
OUT_RING( (1 << TEX_COUNT) - 1 );
OUT_RING( MIPFILTER_NONE << SS2_MIP_FILTER_SHIFT |
FILTER_NEAREST << SS2_MAG_FILTER_SHIFT |
FILTER_NEAREST << SS2_MIN_FILTER_SHIFT );
OUT_RING( TEXCOORDMODE_WRAP << SS3_TCX_ADDR_MODE_SHIFT |
TEXCOORDMODE_WRAP << SS3_TCY_ADDR_MODE_SHIFT |
0 << SS3_TEXTUREMAP_INDEX_SHIFT );
OUT_RING( 0x00000000 );
/* render target state */
// Destination buffer
OUT_RING( _3DSTATE_BUF_INFO_CMD );
OUT_RING( BUF_3D_ID_COLOR_BACK | bm_dst->pitch );
OUT_RING( bm_dst->framebuffer );
OUT_RING( _3DSTATE_DST_BUF_VARS_CMD );
OUT_RING( dst_format |
DSTORG_HORT_BIAS(0x8) |
DSTORG_VERT_BIAS(0x8) );
/* draw rect is unconditional */
OUT_RING( _3DSTATE_DRAW_RECT_CMD );
OUT_RING( 0x00000000 );
OUT_RING( 0x00000000 ); // ymin, xmin
OUT_RING( DRAW_YMAX(dst_y + dst_height - 1) |
DRAW_XMAX(dst_x + dst_width - 1) );
/* yorig, xorig (relate to color buffer?) */
OUT_RING( 0x00000000 );
/* texfmt */
OUT_RING( _3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(1) | I1_LOAD_S(2) | I1_LOAD_S(6) | 2 );
OUT_RING( (4 << S1_VERTEX_WIDTH_SHIFT) | (4 << S1_VERTEX_PITCH_SHIFT) );
OUT_RING( ~S2_TEXCOORD_FMT(0, TEXCOORDFMT_NOT_PRESENT) |
S2_TEXCOORD_FMT(0, TEXCOORDFMT_2D) );
OUT_RING( S6_CBUF_BLEND_ENABLE | S6_COLOR_WRITE_ENABLE |
BLENDFUNC_ADD << S6_CBUF_BLEND_FUNC_SHIFT |
BLENDFACT_ONE << S6_CBUF_SRC_BLEND_FACT_SHIFT |
BLENDFACT_ZERO << S6_CBUF_DST_BLEND_FACT_SHIFT );
/* pixel shader */
OUT_RING( _3DSTATE_PIXEL_SHADER_PROGRAM | (1 + 3*3 - 2) );
/* decl FS_T0 */
OUT_RING( D0_DCL |
GET_UREG_TYPE(FS_T0) << D0_TYPE_SHIFT |
GET_UREG_NR(FS_T0) << D0_NR_SHIFT |
((GET_UREG_TYPE(FS_T0) != GET_UREG_TYPE_S) ? D0_CHANNEL_ALL : 0) );
OUT_RING( 0 );
OUT_RING( 0 );
/* decl FS_S0 */
OUT_RING( D0_DCL |
(GET_UREG_TYPE(FS_S0) << D0_TYPE_SHIFT) |
(GET_UREG_NR(FS_S0) << D0_NR_SHIFT) |
((GET_UREG_TYPE(FS_S0) != GET_UREG_TYPE_S) ? D0_CHANNEL_ALL : 0) );
OUT_RING( 0 );
OUT_RING( 0 );
/* texld(FS_OC, FS_S0, FS_T0 */
OUT_RING( T0_TEXLD |
(GET_UREG_TYPE(FS_OC) << T0_DEST_TYPE_SHIFT) |
(GET_UREG_NR(FS_OC) << T0_DEST_NR_SHIFT) |
(GET_UREG_NR(FS_S0) << T0_SAMPLER_NR_SHIFT) );
OUT_RING( (GET_UREG_TYPE(FS_T0) << T1_ADDRESS_GET_UREG_TYPE_SHIFT) |
(GET_UREG_NR(FS_T0) << T1_ADDRESS_GET_UREG_NR_SHIFT) );
OUT_RING( 0 );
// rectangle
// 3--x
// | |
// 2--1
OUT_RING( PRIM3D_RECTLIST | (3*4 - 1) );
OUT_RING( pack_float( dst_x + dst_width) );
OUT_RING( pack_float( dst_y + dst_height) );
OUT_RING( pack_float(src_x + src_width) );
OUT_RING( pack_float(src_y + src_height) );
OUT_RING( pack_float( dst_x + 0 ) );
OUT_RING( pack_float( dst_y +dst_height) );
OUT_RING( pack_float(src_x + 0) );
OUT_RING( pack_float(src_y + src_height) );
OUT_RING( pack_float( dst_x + 0 ) );
OUT_RING( pack_float( dst_y + 0 ) );
OUT_RING( pack_float(src_x + 0) );
OUT_RING( pack_float(src_y + 0) );
ADVANCE_RING();
DO_FLUSH();
UNLOCK_HW
return TRUE;
}
void
I915DisplayVideoTextured(ScrnInfoPtr scrn,
intel_adaptor_private *adaptor_priv, int id,
RegionPtr dstRegion,
short width, short height, int video_pitch,
int video_pitch2,
short src_w, short src_h, short drw_w, short drw_h,
PixmapPtr pixmap)
{
intel_screen_private *intel = intel_get_screen_private(scrn);
uint32_t format, ms3, s5, tiling;
BoxPtr pbox = REGION_RECTS(dstRegion);
int nbox_total = REGION_NUM_RECTS(dstRegion);
int nbox_this_time;
int dxo, dyo, pix_xoff, pix_yoff;
PixmapPtr target;
#if 0
ErrorF("I915DisplayVideo: %dx%d (pitch %d)\n", width, height,
video_pitch);
#endif
dxo = dstRegion->extents.x1;
dyo = dstRegion->extents.y1;
if (pixmap->drawable.width > 2048 || pixmap->drawable.height > 2048 ||
!intel_uxa_check_pitch_3d(pixmap)) {
ScreenPtr screen = pixmap->drawable.pScreen;
target = screen->CreatePixmap(screen,
dstRegion->extents.x2 - dxo,
dstRegion->extents.y2 - dyo,
pixmap->drawable.depth,
CREATE_PIXMAP_USAGE_SCRATCH);
if (target == NULL)
return;
if (intel_uxa_get_pixmap_bo(target) == NULL) {
screen->DestroyPixmap(target);
return;
}
pix_xoff = -dxo;
pix_yoff = -dyo;
} else {
target = pixmap;
/* Set up the offset for translating from the given region
* (in screen coordinates) to the backing pixmap.
*/
#ifdef COMPOSITE
pix_xoff = -target->screen_x + target->drawable.x;
pix_yoff = -target->screen_y + target->drawable.y;
#else
pix_xoff = 0;
pix_yoff = 0;
#endif
}
#define BYTES_FOR_BOXES(n) ((200 + (n) * 20) * 4)
#define BOXES_IN_BYTES(s) ((((s)/4) - 200) / 20)
#define BATCH_BYTES(p) ((p)->batch_bo->size - 16)
while (nbox_total) {
nbox_this_time = nbox_total;
if (BYTES_FOR_BOXES(nbox_this_time) > BATCH_BYTES(intel))
nbox_this_time = BOXES_IN_BYTES(BATCH_BYTES(intel));
nbox_total -= nbox_this_time;
intel_batch_start_atomic(scrn, 200 + 20 * nbox_this_time);
IntelEmitInvarientState(scrn);
intel->last_3d = LAST_3D_VIDEO;
/* draw rect -- just clipping */
OUT_BATCH(_3DSTATE_DRAW_RECT_CMD);
OUT_BATCH(DRAW_DITHER_OFS_X(pixmap->drawable.x & 3) |
DRAW_DITHER_OFS_Y(pixmap->drawable.y & 3));
OUT_BATCH(0x00000000); /* ymin, xmin */
/* ymax, xmax */
OUT_BATCH((target->drawable.width - 1) |
(target->drawable.height - 1) << 16);
OUT_BATCH(0x00000000); /* yorigin, xorigin */
OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(2) |
I1_LOAD_S(5) | I1_LOAD_S(6) | 2);
OUT_BATCH(S2_TEXCOORD_FMT(0, TEXCOORDFMT_2D) |
S2_TEXCOORD_FMT(1, TEXCOORDFMT_NOT_PRESENT) |
S2_TEXCOORD_FMT(2, TEXCOORDFMT_NOT_PRESENT) |
S2_TEXCOORD_FMT(3, TEXCOORDFMT_NOT_PRESENT) |
S2_TEXCOORD_FMT(4, TEXCOORDFMT_NOT_PRESENT) |
S2_TEXCOORD_FMT(5, TEXCOORDFMT_NOT_PRESENT) |
S2_TEXCOORD_FMT(6, TEXCOORDFMT_NOT_PRESENT) |
S2_TEXCOORD_FMT(7, TEXCOORDFMT_NOT_PRESENT));
s5 = 0x0;
if (intel->cpp == 2)
s5 |= S5_COLOR_DITHER_ENABLE;
OUT_BATCH(s5); /* S5 - enable bits */
OUT_BATCH((2 << S6_DEPTH_TEST_FUNC_SHIFT) |
(2 << S6_CBUF_SRC_BLEND_FACT_SHIFT) |
(1 << S6_CBUF_DST_BLEND_FACT_SHIFT) |
S6_COLOR_WRITE_ENABLE | (2 << S6_TRISTRIP_PV_SHIFT));
OUT_BATCH(_3DSTATE_CONST_BLEND_COLOR_CMD);
OUT_BATCH(0x00000000);
OUT_BATCH(_3DSTATE_DST_BUF_VARS_CMD);
if (intel->cpp == 2)
format = COLR_BUF_RGB565;
else
format =
COLR_BUF_ARGB8888 | DEPTH_FRMT_24_FIXED_8_OTHER;
OUT_BATCH(LOD_PRECLAMP_OGL |
DSTORG_HORT_BIAS(0x8) |
DSTORG_VERT_BIAS(0x8) | format);
/* front buffer, pitch, offset */
if (intel_uxa_pixmap_tiled(target)) {
tiling = BUF_3D_TILED_SURFACE;
if (intel_uxa_get_pixmap_private(target)->tiling == I915_TILING_Y)
tiling |= BUF_3D_TILE_WALK_Y;
} else
tiling = 0;
OUT_BATCH(_3DSTATE_BUF_INFO_CMD);
OUT_BATCH(BUF_3D_ID_COLOR_BACK | tiling |
BUF_3D_PITCH(intel_pixmap_pitch(target)));
OUT_RELOC_PIXMAP(target, I915_GEM_DOMAIN_RENDER,
I915_GEM_DOMAIN_RENDER, 0);
if (!is_planar_fourcc(id)) {
FS_LOCALS();
OUT_BATCH(_3DSTATE_PIXEL_SHADER_CONSTANTS | 4);
OUT_BATCH(0x0000001); /* constant 0 */
/* constant 0: brightness/contrast */
OUT_BATCH_F(adaptor_priv->brightness / 128.0);
OUT_BATCH_F(adaptor_priv->contrast / 255.0);
OUT_BATCH_F(0.0);
OUT_BATCH_F(0.0);
OUT_BATCH(_3DSTATE_SAMPLER_STATE | 3);
OUT_BATCH(0x00000001);
OUT_BATCH(SS2_COLORSPACE_CONVERSION |
(FILTER_LINEAR << SS2_MAG_FILTER_SHIFT) |
(FILTER_LINEAR << SS2_MIN_FILTER_SHIFT));
OUT_BATCH((TEXCOORDMODE_CLAMP_EDGE <<
SS3_TCX_ADDR_MODE_SHIFT) |
(TEXCOORDMODE_CLAMP_EDGE <<
SS3_TCY_ADDR_MODE_SHIFT) |
(0 << SS3_TEXTUREMAP_INDEX_SHIFT) |
SS3_NORMALIZED_COORDS);
OUT_BATCH(0x00000000);
OUT_BATCH(_3DSTATE_MAP_STATE | 3);
OUT_BATCH(0x00000001); /* texture map #1 */
if (adaptor_priv->buf)
OUT_RELOC(adaptor_priv->buf,
I915_GEM_DOMAIN_SAMPLER, 0,
adaptor_priv->YBufOffset);
else
OUT_BATCH(adaptor_priv->YBufOffset);
ms3 = MAPSURF_422;
switch (id) {
case FOURCC_YUY2:
ms3 |= MT_422_YCRCB_NORMAL;
break;
case FOURCC_UYVY:
ms3 |= MT_422_YCRCB_SWAPY;
break;
}
ms3 |= (height - 1) << MS3_HEIGHT_SHIFT;
ms3 |= (width - 1) << MS3_WIDTH_SHIFT;
OUT_BATCH(ms3);
OUT_BATCH(((video_pitch / 4) - 1) << MS4_PITCH_SHIFT);
FS_BEGIN();
i915_fs_dcl(FS_S0);
i915_fs_dcl(FS_T0);
i915_fs_texld(FS_OC, FS_S0, FS_T0);
if (adaptor_priv->brightness != 0) {
i915_fs_add(FS_OC,
i915_fs_operand_reg(FS_OC),
i915_fs_operand(FS_C0, X, X, X,
ZERO));
}
FS_END();
} else {
FS_LOCALS();
/* For the planar formats, we set up three samplers --
* one for each plane, in a Y8 format. Because I
* couldn't get the special PLANAR_TO_PACKED
* shader setup to work, I did the manual pixel shader:
*
* y' = y - .0625
* u' = u - .5
* v' = v - .5;
*
* r = 1.1643 * y' + 0.0 * u' + 1.5958 * v'
* g = 1.1643 * y' - 0.39173 * u' - 0.81290 * v'
* b = 1.1643 * y' + 2.017 * u' + 0.0 * v'
*
* register assignment:
* r0 = (y',u',v',0)
* r1 = (y,y,y,y)
* r2 = (u,u,u,u)
* r3 = (v,v,v,v)
* OC = (r,g,b,1)
*/
OUT_BATCH(_3DSTATE_PIXEL_SHADER_CONSTANTS | (22 - 2));
OUT_BATCH(0x000001f); /* constants 0-4 */
/* constant 0: normalization offsets */
OUT_BATCH_F(-0.0625);
OUT_BATCH_F(-0.5);
OUT_BATCH_F(-0.5);
OUT_BATCH_F(0.0);
/* constant 1: r coefficients */
OUT_BATCH_F(1.1643);
OUT_BATCH_F(0.0);
OUT_BATCH_F(1.5958);
OUT_BATCH_F(0.0);
/* constant 2: g coefficients */
OUT_BATCH_F(1.1643);
OUT_BATCH_F(-0.39173);
OUT_BATCH_F(-0.81290);
OUT_BATCH_F(0.0);
/* constant 3: b coefficients */
OUT_BATCH_F(1.1643);
OUT_BATCH_F(2.017);
OUT_BATCH_F(0.0);
OUT_BATCH_F(0.0);
/* constant 4: brightness/contrast */
OUT_BATCH_F(adaptor_priv->brightness / 128.0);
OUT_BATCH_F(adaptor_priv->contrast / 255.0);
OUT_BATCH_F(0.0);
OUT_BATCH_F(0.0);
OUT_BATCH(_3DSTATE_SAMPLER_STATE | 9);
OUT_BATCH(0x00000007);
/* sampler 0 */
OUT_BATCH((FILTER_LINEAR << SS2_MAG_FILTER_SHIFT) |
(FILTER_LINEAR << SS2_MIN_FILTER_SHIFT));
OUT_BATCH((TEXCOORDMODE_CLAMP_EDGE <<
SS3_TCX_ADDR_MODE_SHIFT) |
(TEXCOORDMODE_CLAMP_EDGE <<
SS3_TCY_ADDR_MODE_SHIFT) |
(0 << SS3_TEXTUREMAP_INDEX_SHIFT) |
SS3_NORMALIZED_COORDS);
OUT_BATCH(0x00000000);
/* sampler 1 */
OUT_BATCH((FILTER_LINEAR << SS2_MAG_FILTER_SHIFT) |
(FILTER_LINEAR << SS2_MIN_FILTER_SHIFT));
OUT_BATCH((TEXCOORDMODE_CLAMP_EDGE <<
SS3_TCX_ADDR_MODE_SHIFT) |
(TEXCOORDMODE_CLAMP_EDGE <<
SS3_TCY_ADDR_MODE_SHIFT) |
(1 << SS3_TEXTUREMAP_INDEX_SHIFT) |
SS3_NORMALIZED_COORDS);
OUT_BATCH(0x00000000);
/* sampler 2 */
OUT_BATCH((FILTER_LINEAR << SS2_MAG_FILTER_SHIFT) |
(FILTER_LINEAR << SS2_MIN_FILTER_SHIFT));
OUT_BATCH((TEXCOORDMODE_CLAMP_EDGE <<
SS3_TCX_ADDR_MODE_SHIFT) |
(TEXCOORDMODE_CLAMP_EDGE <<
SS3_TCY_ADDR_MODE_SHIFT) |
(2 << SS3_TEXTUREMAP_INDEX_SHIFT) |
SS3_NORMALIZED_COORDS);
OUT_BATCH(0x00000000);
OUT_BATCH(_3DSTATE_MAP_STATE | 9);
OUT_BATCH(0x00000007);
if (adaptor_priv->buf)
OUT_RELOC(adaptor_priv->buf,
I915_GEM_DOMAIN_SAMPLER, 0,
adaptor_priv->YBufOffset);
else
OUT_BATCH(adaptor_priv->YBufOffset);
ms3 = MAPSURF_8BIT | MT_8BIT_I8;
ms3 |= (height - 1) << MS3_HEIGHT_SHIFT;
ms3 |= (width - 1) << MS3_WIDTH_SHIFT;
OUT_BATCH(ms3);
/* check to see if Y has special pitch than normal
* double u/v pitch, e.g i915 XvMC hw requires at
* least 1K alignment, so Y pitch might
* be same as U/V's.*/
if (video_pitch2)
OUT_BATCH(((video_pitch2 / 4) -
1) << MS4_PITCH_SHIFT);
else
OUT_BATCH(((video_pitch * 2 / 4) -
1) << MS4_PITCH_SHIFT);
if (adaptor_priv->buf)
OUT_RELOC(adaptor_priv->buf,
I915_GEM_DOMAIN_SAMPLER, 0,
adaptor_priv->UBufOffset);
else
OUT_BATCH(adaptor_priv->UBufOffset);
ms3 = MAPSURF_8BIT | MT_8BIT_I8;
ms3 |= (height / 2 - 1) << MS3_HEIGHT_SHIFT;
ms3 |= (width / 2 - 1) << MS3_WIDTH_SHIFT;
OUT_BATCH(ms3);
OUT_BATCH(((video_pitch / 4) - 1) << MS4_PITCH_SHIFT);
if (adaptor_priv->buf)
OUT_RELOC(adaptor_priv->buf,
I915_GEM_DOMAIN_SAMPLER, 0,
adaptor_priv->VBufOffset);
else
OUT_BATCH(adaptor_priv->VBufOffset);
ms3 = MAPSURF_8BIT | MT_8BIT_I8;
ms3 |= (height / 2 - 1) << MS3_HEIGHT_SHIFT;
ms3 |= (width / 2 - 1) << MS3_WIDTH_SHIFT;
OUT_BATCH(ms3);
OUT_BATCH(((video_pitch / 4) - 1) << MS4_PITCH_SHIFT);
FS_BEGIN();
/* Declare samplers */
i915_fs_dcl(FS_S0); /* Y */
i915_fs_dcl(FS_S1); /* U */
i915_fs_dcl(FS_S2); /* V */
i915_fs_dcl(FS_T0); /* normalized coords */
/* Load samplers to temporaries. */
i915_fs_texld(FS_R1, FS_S0, FS_T0);
i915_fs_texld(FS_R2, FS_S1, FS_T0);
i915_fs_texld(FS_R3, FS_S2, FS_T0);
/* Move the sampled YUV data in R[123] to the first
* 3 channels of R0.
*/
i915_fs_mov_masked(FS_R0, MASK_X,
i915_fs_operand_reg(FS_R1));
i915_fs_mov_masked(FS_R0, MASK_Y,
i915_fs_operand_reg(FS_R2));
i915_fs_mov_masked(FS_R0, MASK_Z,
i915_fs_operand_reg(FS_R3));
/* Normalize the YUV data */
i915_fs_add(FS_R0, i915_fs_operand_reg(FS_R0),
i915_fs_operand_reg(FS_C0));
/* dot-product the YUV data in R0 by the vectors of
* coefficients for calculating R, G, and B, storing
* the results in the R, G, or B channels of the output
* color. The OC results are implicitly clamped
* at the end of the program.
*/
i915_fs_dp3(FS_OC, MASK_X,
i915_fs_operand_reg(FS_R0),
i915_fs_operand_reg(FS_C1));
i915_fs_dp3(FS_OC, MASK_Y,
i915_fs_operand_reg(FS_R0),
i915_fs_operand_reg(FS_C2));
i915_fs_dp3(FS_OC, MASK_Z,
i915_fs_operand_reg(FS_R0),
i915_fs_operand_reg(FS_C3));
/* Set alpha of the output to 1.0, by wiring W to 1
* and not actually using the source.
*/
i915_fs_mov_masked(FS_OC, MASK_W,
i915_fs_operand_one());
if (adaptor_priv->brightness != 0) {
i915_fs_add(FS_OC,
i915_fs_operand_reg(FS_OC),
i915_fs_operand(FS_C4, X, X, X,
ZERO));
}
FS_END();
}
OUT_BATCH(PRIM3D_RECTLIST | (12 * nbox_this_time - 1));
while (nbox_this_time--) {
int box_x1 = pbox->x1;
int box_y1 = pbox->y1;
int box_x2 = pbox->x2;
int box_y2 = pbox->y2;
float src_scale_x, src_scale_y;
pbox++;
src_scale_x = ((float)src_w / width) / drw_w;
src_scale_y = ((float)src_h / height) / drw_h;
/* vertex data - rect list consists of bottom right,
* bottom left, and top left vertices.
*/
/* bottom right */
OUT_BATCH_F(box_x2 + pix_xoff);
OUT_BATCH_F(box_y2 + pix_yoff);
OUT_BATCH_F((box_x2 - dxo) * src_scale_x);
OUT_BATCH_F((box_y2 - dyo) * src_scale_y);
/* bottom left */
OUT_BATCH_F(box_x1 + pix_xoff);
OUT_BATCH_F(box_y2 + pix_yoff);
OUT_BATCH_F((box_x1 - dxo) * src_scale_x);
OUT_BATCH_F((box_y2 - dyo) * src_scale_y);
/* top left */
OUT_BATCH_F(box_x1 + pix_xoff);
OUT_BATCH_F(box_y1 + pix_yoff);
OUT_BATCH_F((box_x1 - dxo) * src_scale_x);
OUT_BATCH_F((box_y1 - dyo) * src_scale_y);
}
intel_batch_end_atomic(scrn);
}
if (target != pixmap) {
GCPtr gc;
gc = GetScratchGC(pixmap->drawable.depth,
pixmap->drawable.pScreen);
if (gc) {
gc->subWindowMode = ClipByChildren;
if (REGION_NUM_RECTS(dstRegion) > 1) {
RegionPtr tmp;
tmp = REGION_CREATE(pixmap->drawable.pScreen, NULL, 0);
if (tmp) {
REGION_COPY(pixmap->drawable.pScreen, tmp, dstRegion);
gc->funcs->ChangeClip(gc, CT_REGION, tmp, 0);
}
}
ValidateGC(&pixmap->drawable, gc);
gc->ops->CopyArea(&target->drawable, &pixmap->drawable, gc,
0, 0,
target->drawable.width,
target->drawable.height,
-pix_xoff, -pix_yoff);
FreeScratchGC(gc);
}
target->drawable.pScreen->DestroyPixmap(target);
}
intel_uxa_debug_flush(scrn);
}
static void
i915_init_packets(struct i915_context *i915)
{
/* Zero all state */
memset(&i915->state, 0, sizeof(i915->state));
{
I915_STATECHANGE(i915, I915_UPLOAD_CTX);
I915_STATECHANGE(i915, I915_UPLOAD_BLEND);
/* Probably don't want to upload all this stuff every time one
* piece changes.
*/
i915->state.Ctx[I915_CTXREG_LI] = (_3DSTATE_LOAD_STATE_IMMEDIATE_1 |
I1_LOAD_S(2) |
I1_LOAD_S(4) |
I1_LOAD_S(5) | I1_LOAD_S(6) | (3));
i915->state.Ctx[I915_CTXREG_LIS2] = 0;
i915->state.Ctx[I915_CTXREG_LIS4] = 0;
i915->state.Ctx[I915_CTXREG_LIS5] = 0;
if (i915->intel.ctx.Visual.rgbBits == 16)
i915->state.Ctx[I915_CTXREG_LIS5] |= S5_COLOR_DITHER_ENABLE;
i915->state.Ctx[I915_CTXREG_LIS6] = (S6_COLOR_WRITE_ENABLE |
(2 << S6_TRISTRIP_PV_SHIFT));
i915->state.Ctx[I915_CTXREG_STATE4] = (_3DSTATE_MODES_4_CMD |
ENABLE_LOGIC_OP_FUNC |
LOGIC_OP_FUNC(LOGICOP_COPY) |
ENABLE_STENCIL_TEST_MASK |
STENCIL_TEST_MASK(0xff) |
ENABLE_STENCIL_WRITE_MASK |
STENCIL_WRITE_MASK(0xff));
i915->state.Blend[I915_BLENDREG_IAB] =
(_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD | IAB_MODIFY_ENABLE |
IAB_MODIFY_FUNC | IAB_MODIFY_SRC_FACTOR | IAB_MODIFY_DST_FACTOR);
i915->state.Blend[I915_BLENDREG_BLENDCOLOR0] =
_3DSTATE_CONST_BLEND_COLOR_CMD;
i915->state.Blend[I915_BLENDREG_BLENDCOLOR1] = 0;
i915->state.Ctx[I915_CTXREG_BF_STENCIL_MASKS] =
_3DSTATE_BACKFACE_STENCIL_MASKS |
BFM_ENABLE_STENCIL_TEST_MASK |
BFM_ENABLE_STENCIL_WRITE_MASK |
(0xff << BFM_STENCIL_WRITE_MASK_SHIFT) |
(0xff << BFM_STENCIL_TEST_MASK_SHIFT);
i915->state.Ctx[I915_CTXREG_BF_STENCIL_OPS] =
_3DSTATE_BACKFACE_STENCIL_OPS |
BFO_ENABLE_STENCIL_REF |
BFO_ENABLE_STENCIL_FUNCS |
BFO_ENABLE_STENCIL_TWO_SIDE;
}
{
I915_STATECHANGE(i915, I915_UPLOAD_STIPPLE);
i915->state.Stipple[I915_STPREG_ST0] = _3DSTATE_STIPPLE;
}
{
i915->state.Buffer[I915_DESTREG_DV0] = _3DSTATE_DST_BUF_VARS_CMD;
/* scissor */
i915->state.Buffer[I915_DESTREG_SENABLE] =
(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
i915->state.Buffer[I915_DESTREG_SR0] = _3DSTATE_SCISSOR_RECT_0_CMD;
i915->state.Buffer[I915_DESTREG_SR1] = 0;
i915->state.Buffer[I915_DESTREG_SR2] = 0;
}
i915->state.RasterRules[I915_RASTER_RULES] = _3DSTATE_RASTER_RULES_CMD |
ENABLE_POINT_RASTER_RULE |
OGL_POINT_RASTER_RULE |
ENABLE_LINE_STRIP_PROVOKE_VRTX |
ENABLE_TRI_FAN_PROVOKE_VRTX |
LINE_STRIP_PROVOKE_VRTX(1) |
TRI_FAN_PROVOKE_VRTX(2) | ENABLE_TEXKILL_3D_4D | TEXKILL_4D;
#if 0
{
I915_STATECHANGE(i915, I915_UPLOAD_DEFAULTS);
i915->state.Default[I915_DEFREG_C0] = _3DSTATE_DEFAULT_DIFFUSE;
i915->state.Default[I915_DEFREG_C1] = 0;
i915->state.Default[I915_DEFREG_S0] = _3DSTATE_DEFAULT_SPECULAR;
i915->state.Default[I915_DEFREG_S1] = 0;
i915->state.Default[I915_DEFREG_Z0] = _3DSTATE_DEFAULT_Z;
i915->state.Default[I915_DEFREG_Z1] = 0;
}
#endif
/* These will be emitted every at the head of every buffer, unless
* we get hardware contexts working.
*/
i915->state.active = (I915_UPLOAD_PROGRAM |
I915_UPLOAD_STIPPLE |
I915_UPLOAD_CTX |
I915_UPLOAD_BLEND |
I915_UPLOAD_BUFFERS |
I915_UPLOAD_INVARIENT |
I915_UPLOAD_RASTER_RULES);
}
static void i830_emit_composite_state(ScrnInfoPtr scrn)
{
intel_screen_private *intel = intel_get_screen_private(scrn);
uint32_t vf2, tiling_bits;
uint32_t texcoordfmt = 0;
intel->needs_render_state_emit = FALSE;
IntelEmitInvarientState(scrn);
intel->last_3d = LAST_3D_RENDER;
assert(intel->in_batch_atomic);
if (intel_pixmap_tiled(intel->render_dest)) {
tiling_bits = BUF_3D_TILED_SURFACE;
if (intel_get_pixmap_private(intel->render_dest)->tiling
== I915_TILING_Y)
tiling_bits |= BUF_3D_TILE_WALK_Y;
} else
tiling_bits = 0;
OUT_BATCH(_3DSTATE_BUF_INFO_CMD);
OUT_BATCH(BUF_3D_ID_COLOR_BACK | tiling_bits |
BUF_3D_PITCH(intel_pixmap_pitch(intel->render_dest)));
OUT_RELOC_PIXMAP(intel->render_dest,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
OUT_BATCH(_3DSTATE_DST_BUF_VARS_CMD);
OUT_BATCH(intel->render_dest_format);
OUT_BATCH(_3DSTATE_DRAW_RECT_CMD);
OUT_BATCH(0);
OUT_BATCH(0); /* ymin, xmin */
OUT_BATCH(DRAW_YMAX(intel->render_dest->drawable.height - 1) |
DRAW_XMAX(intel->render_dest->drawable.width - 1));
OUT_BATCH(0); /* yorig, xorig */
OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 |
I1_LOAD_S(2) | I1_LOAD_S(3) | I1_LOAD_S(8) | 2);
if (intel->render_mask)
vf2 = 2 << 12; /* 2 texture coord sets */
else
vf2 = 1 << 12;
OUT_BATCH(vf2); /* number of coordinate sets */
OUT_BATCH(S3_CULLMODE_NONE | S3_VERTEXHAS_XY);
OUT_BATCH(S8_ENABLE_COLOR_BLEND | S8_BLENDFUNC_ADD | intel->
s8_blendctl | S8_ENABLE_COLOR_BUFFER_WRITE);
OUT_BATCH(_3DSTATE_INDPT_ALPHA_BLEND_CMD | DISABLE_INDPT_ALPHA_BLEND);
OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_2 |
LOAD_TEXTURE_BLEND_STAGE(0) | 1);
OUT_BATCH(intel->cblend);
OUT_BATCH(intel->ablend);
OUT_BATCH(_3DSTATE_ENABLES_1_CMD | DISABLE_LOGIC_OP |
DISABLE_STENCIL_TEST | DISABLE_DEPTH_BIAS |
DISABLE_SPEC_ADD | DISABLE_FOG | DISABLE_ALPHA_TEST |
ENABLE_COLOR_BLEND | DISABLE_DEPTH_TEST);
/* We have to explicitly say we don't want write disabled */
OUT_BATCH(_3DSTATE_ENABLES_2_CMD | ENABLE_COLOR_MASK |
DISABLE_STENCIL_WRITE | ENABLE_TEX_CACHE |
DISABLE_DITHER | ENABLE_COLOR_WRITE | DISABLE_DEPTH_WRITE);
if (intel_transform_is_affine(intel->render_source_picture->transform))
texcoordfmt |= (TEXCOORDFMT_2D << 0);
else
texcoordfmt |= (TEXCOORDFMT_3D << 0);
if (intel->render_mask) {
if (intel_transform_is_affine
(intel->render_mask_picture->transform))
texcoordfmt |= (TEXCOORDFMT_2D << 2);
else
texcoordfmt |= (TEXCOORDFMT_3D << 2);
}
OUT_BATCH(_3DSTATE_VERTEX_FORMAT_2_CMD | texcoordfmt);
i830_texture_setup(intel->render_source_picture, intel->render_source, 0);
if (intel->render_mask) {
i830_texture_setup(intel->render_mask_picture,
intel->render_mask, 1);
}
}
static void
copy(int fd, uint32_t dst, uint32_t src)
{
uint32_t batch[1024], *b = batch;
struct drm_i915_gem_relocation_entry reloc[2], *r = reloc;
struct drm_i915_gem_exec_object2 obj[3];
struct drm_i915_gem_execbuffer2 exec;
uint32_t handle;
int ret;
/* invariant state */
*b++ = (_3DSTATE_AA_CMD |
AA_LINE_ECAAR_WIDTH_ENABLE |
AA_LINE_ECAAR_WIDTH_1_0 |
AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);
*b++ = (_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD |
IAB_MODIFY_ENABLE |
IAB_MODIFY_FUNC | (BLENDFUNC_ADD << IAB_FUNC_SHIFT) |
IAB_MODIFY_SRC_FACTOR | (BLENDFACT_ONE <<
IAB_SRC_FACTOR_SHIFT) |
IAB_MODIFY_DST_FACTOR | (BLENDFACT_ZERO <<
IAB_DST_FACTOR_SHIFT));
*b++ = (_3DSTATE_DFLT_DIFFUSE_CMD);
*b++ = (0);
*b++ = (_3DSTATE_DFLT_SPEC_CMD);
*b++ = (0);
*b++ = (_3DSTATE_DFLT_Z_CMD);
*b++ = (0);
*b++ = (_3DSTATE_COORD_SET_BINDINGS |
CSB_TCB(0, 0) |
CSB_TCB(1, 1) |
CSB_TCB(2, 2) |
CSB_TCB(3, 3) |
CSB_TCB(4, 4) |
CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7));
*b++ = (_3DSTATE_RASTER_RULES_CMD |
ENABLE_POINT_RASTER_RULE |
OGL_POINT_RASTER_RULE |
ENABLE_LINE_STRIP_PROVOKE_VRTX |
ENABLE_TRI_FAN_PROVOKE_VRTX |
LINE_STRIP_PROVOKE_VRTX(1) |
TRI_FAN_PROVOKE_VRTX(2) | ENABLE_TEXKILL_3D_4D | TEXKILL_4D);
*b++ = (_3DSTATE_MODES_4_CMD |
ENABLE_LOGIC_OP_FUNC | LOGIC_OP_FUNC(LOGICOP_COPY) |
ENABLE_STENCIL_WRITE_MASK | STENCIL_WRITE_MASK(0xff) |
ENABLE_STENCIL_TEST_MASK | STENCIL_TEST_MASK(0xff));
*b++ = (_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | I1_LOAD_S(4) | I1_LOAD_S(5) | 2);
*b++ = (0x00000000); /* Disable texture coordinate wrap-shortest */
*b++ = ((1 << S4_POINT_WIDTH_SHIFT) |
S4_LINE_WIDTH_ONE |
S4_CULLMODE_NONE |
S4_VFMT_XY);
*b++ = (0x00000000); /* Stencil. */
*b++ = (_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
*b++ = (_3DSTATE_SCISSOR_RECT_0_CMD);
*b++ = (0);
*b++ = (0);
*b++ = (_3DSTATE_DEPTH_SUBRECT_DISABLE);
*b++ = (_3DSTATE_LOAD_INDIRECT | 0); /* disable indirect state */
*b++ = (0);
*b++ = (_3DSTATE_STIPPLE);
*b++ = (0x00000000);
*b++ = (_3DSTATE_BACKFACE_STENCIL_OPS | BFO_ENABLE_STENCIL_TWO_SIDE | 0);
/* samler state */
#define TEX_COUNT 1
*b++ = (_3DSTATE_MAP_STATE | (3 * TEX_COUNT));
*b++ = ((1 << TEX_COUNT) - 1);
*b = fill_reloc(r++, b-batch, src, I915_GEM_DOMAIN_SAMPLER, 0); b++;
*b++ = (MAPSURF_32BIT | MT_32BIT_ARGB8888 |
MS3_TILED_SURFACE |
(HEIGHT - 1) << MS3_HEIGHT_SHIFT |
(WIDTH - 1) << MS3_WIDTH_SHIFT);
*b++ = ((WIDTH-1) << MS4_PITCH_SHIFT);
*b++ = (_3DSTATE_SAMPLER_STATE | (3 * TEX_COUNT));
*b++ = ((1 << TEX_COUNT) - 1);
*b++ = (MIPFILTER_NONE << SS2_MIP_FILTER_SHIFT |
FILTER_NEAREST << SS2_MAG_FILTER_SHIFT |
FILTER_NEAREST << SS2_MIN_FILTER_SHIFT);
*b++ = (TEXCOORDMODE_WRAP << SS3_TCX_ADDR_MODE_SHIFT |
TEXCOORDMODE_WRAP << SS3_TCY_ADDR_MODE_SHIFT |
0 << SS3_TEXTUREMAP_INDEX_SHIFT);
*b++ = (0x00000000);
/* render target state */
*b++ = (_3DSTATE_BUF_INFO_CMD);
*b++ = (BUF_3D_ID_COLOR_BACK | BUF_3D_TILED_SURFACE | WIDTH*4);
*b = fill_reloc(r++, b-batch, dst,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
b++;
*b++ = (_3DSTATE_DST_BUF_VARS_CMD);
*b++ = (COLR_BUF_ARGB8888 |
DSTORG_HORT_BIAS(0x8) |
DSTORG_VERT_BIAS(0x8));
/* draw rect is unconditional */
*b++ = (_3DSTATE_DRAW_RECT_CMD);
*b++ = (0x00000000);
*b++ = (0x00000000); /* ymin, xmin */
*b++ = (DRAW_YMAX(HEIGHT - 1) |
DRAW_XMAX(WIDTH - 1));
/* yorig, xorig (relate to color buffer?) */
*b++ = (0x00000000);
/* texfmt */
*b++ = (_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(1) | I1_LOAD_S(2) | I1_LOAD_S(6) | 2);
*b++ = ((4 << S1_VERTEX_WIDTH_SHIFT) | (4 << S1_VERTEX_PITCH_SHIFT));
*b++ = (~S2_TEXCOORD_FMT(0, TEXCOORDFMT_NOT_PRESENT) |
S2_TEXCOORD_FMT(0, TEXCOORDFMT_2D));
*b++ = (S6_CBUF_BLEND_ENABLE | S6_COLOR_WRITE_ENABLE |
BLENDFUNC_ADD << S6_CBUF_BLEND_FUNC_SHIFT |
BLENDFACT_ONE << S6_CBUF_SRC_BLEND_FACT_SHIFT |
BLENDFACT_ZERO << S6_CBUF_DST_BLEND_FACT_SHIFT);
/* pixel shader */
*b++ = (_3DSTATE_PIXEL_SHADER_PROGRAM | (1 + 3*3 - 2));
/* decl FS_T0 */
*b++ = (D0_DCL |
REG_TYPE(FS_T0) << D0_TYPE_SHIFT |
REG_NR(FS_T0) << D0_NR_SHIFT |
((REG_TYPE(FS_T0) != REG_TYPE_S) ? D0_CHANNEL_ALL : 0));
*b++ = (0);
*b++ = (0);
/* decl FS_S0 */
*b++ = (D0_DCL |
(REG_TYPE(FS_S0) << D0_TYPE_SHIFT) |
(REG_NR(FS_S0) << D0_NR_SHIFT) |
((REG_TYPE(FS_S0) != REG_TYPE_S) ? D0_CHANNEL_ALL : 0));
*b++ = (0);
*b++ = (0);
/* texld(FS_OC, FS_S0, FS_T0 */
*b++ = (T0_TEXLD |
(REG_TYPE(FS_OC) << T0_DEST_TYPE_SHIFT) |
(REG_NR(FS_OC) << T0_DEST_NR_SHIFT) |
(REG_NR(FS_S0) << T0_SAMPLER_NR_SHIFT));
*b++ = ((REG_TYPE(FS_T0) << T1_ADDRESS_REG_TYPE_SHIFT) |
(REG_NR(FS_T0) << T1_ADDRESS_REG_NR_SHIFT));
*b++ = (0);
*b++ = (PRIM3D_RECTLIST | (3*4 - 1));
*b++ = pack_float(WIDTH);
*b++ = pack_float(HEIGHT);
*b++ = pack_float(WIDTH);
*b++ = pack_float(HEIGHT);
*b++ = pack_float(0);
*b++ = pack_float(HEIGHT);
*b++ = pack_float(0);
*b++ = pack_float(HEIGHT);
*b++ = pack_float(0);
*b++ = pack_float(0);
*b++ = pack_float(0);
*b++ = pack_float(0);
*b++ = MI_BATCH_BUFFER_END;
if ((b - batch) & 1)
*b++ = 0;
igt_assert(b - batch <= 1024);
handle = gem_create(fd, 4096);
gem_write(fd, handle, 0, batch, (b-batch)*sizeof(batch[0]));
igt_assert(r-reloc == 2);
obj[0].handle = dst;
obj[0].relocation_count = 0;
obj[0].relocs_ptr = 0;
obj[0].alignment = 0;
obj[0].offset = 0;
obj[0].flags = 0;
obj[0].rsvd1 = 0;
obj[0].rsvd2 = 0;
obj[1].handle = src;
obj[1].relocation_count = 0;
obj[1].relocs_ptr = 0;
obj[1].alignment = 0;
obj[1].offset = 0;
obj[1].flags = 0;
obj[1].rsvd1 = 0;
obj[1].rsvd2 = 0;
obj[2].handle = handle;
obj[2].relocation_count = 2;
obj[2].relocs_ptr = (uintptr_t)reloc;
obj[2].alignment = 0;
obj[2].offset = 0;
obj[2].flags = 0;
obj[2].rsvd1 = obj[2].rsvd2 = 0;
exec.buffers_ptr = (uintptr_t)obj;
exec.buffer_count = 3;
exec.batch_start_offset = 0;
exec.batch_len = (b-batch)*sizeof(batch[0]);
exec.DR1 = exec.DR4 = 0;
exec.num_cliprects = 0;
exec.cliprects_ptr = 0;
exec.flags = 0;
i915_execbuffer2_set_context_id(exec, 0);
exec.rsvd2 = 0;
ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &exec);
while (ret && errno == EBUSY) {
drmCommandNone(fd, DRM_I915_GEM_THROTTLE);
ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &exec);
}
igt_assert_eq(ret, 0);
gem_close(fd, handle);
}
static void
i915_init_packets(struct i915_context *i915)
{
intelScreenPrivate *screen = i915->intel.intelScreen;
/* Zero all state */
memset(&i915->state, 0, sizeof(i915->state));
{
I915_STATECHANGE(i915, I915_UPLOAD_CTX);
/* Probably don't want to upload all this stuff every time one
* piece changes.
*/
i915->state.Ctx[I915_CTXREG_LI] = (_3DSTATE_LOAD_STATE_IMMEDIATE_1 |
I1_LOAD_S(2) |
I1_LOAD_S(4) |
I1_LOAD_S(5) | I1_LOAD_S(6) | (3));
i915->state.Ctx[I915_CTXREG_LIS2] = 0;
i915->state.Ctx[I915_CTXREG_LIS4] = 0;
i915->state.Ctx[I915_CTXREG_LIS5] = 0;
if (screen->cpp == 2) /* XXX FBO fix */
i915->state.Ctx[I915_CTXREG_LIS5] |= S5_COLOR_DITHER_ENABLE;
i915->state.Ctx[I915_CTXREG_LIS6] = (S6_COLOR_WRITE_ENABLE |
(2 << S6_TRISTRIP_PV_SHIFT));
i915->state.Ctx[I915_CTXREG_STATE4] = (_3DSTATE_MODES_4_CMD |
ENABLE_LOGIC_OP_FUNC |
LOGIC_OP_FUNC(LOGICOP_COPY) |
ENABLE_STENCIL_TEST_MASK |
STENCIL_TEST_MASK(0xff) |
ENABLE_STENCIL_WRITE_MASK |
STENCIL_WRITE_MASK(0xff));
i915->state.Ctx[I915_CTXREG_IAB] =
(_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD | IAB_MODIFY_ENABLE |
IAB_MODIFY_FUNC | IAB_MODIFY_SRC_FACTOR | IAB_MODIFY_DST_FACTOR);
i915->state.Ctx[I915_CTXREG_BLENDCOLOR0] =
_3DSTATE_CONST_BLEND_COLOR_CMD;
i915->state.Ctx[I915_CTXREG_BLENDCOLOR1] = 0;
}
{
I915_STATECHANGE(i915, I915_UPLOAD_STIPPLE);
i915->state.Stipple[I915_STPREG_ST0] = _3DSTATE_STIPPLE;
}
{
I915_STATECHANGE(i915, I915_UPLOAD_FOG);
i915->state.Fog[I915_FOGREG_MODE0] = _3DSTATE_FOG_MODE_CMD;
i915->state.Fog[I915_FOGREG_MODE1] = (FMC1_FOGFUNC_MODIFY_ENABLE |
FMC1_FOGFUNC_VERTEX |
FMC1_FOGINDEX_MODIFY_ENABLE |
FMC1_FOGINDEX_W |
FMC1_C1_C2_MODIFY_ENABLE |
FMC1_DENSITY_MODIFY_ENABLE);
i915->state.Fog[I915_FOGREG_COLOR] = _3DSTATE_FOG_COLOR_CMD;
}
{
I915_STATECHANGE(i915, I915_UPLOAD_BUFFERS);
/* color buffer offset/stride */
i915->state.Buffer[I915_DESTREG_CBUFADDR0] = _3DSTATE_BUF_INFO_CMD;
/* XXX FBO: remove this? Also get set in i915_set_draw_region() */
i915->state.Buffer[I915_DESTREG_CBUFADDR1] = (BUF_3D_ID_COLOR_BACK | BUF_3D_PITCH(screen->front.pitch) | /* pitch in bytes */
BUF_3D_USE_FENCE);
i915->state.Buffer[I915_DESTREG_DBUFADDR0] = _3DSTATE_BUF_INFO_CMD;
/* XXX FBO: remove this? Also get set in i915_set_draw_region() */
i915->state.Buffer[I915_DESTREG_DBUFADDR1] = (BUF_3D_ID_DEPTH | BUF_3D_PITCH(screen->depth.pitch) | /* pitch in bytes */
BUF_3D_USE_FENCE);
i915->state.Buffer[I915_DESTREG_DV0] = _3DSTATE_DST_BUF_VARS_CMD;
/* XXX FBO: remove this? Also get set in i915_set_draw_region() */
#if 0 /* seems we don't need this */
switch (screen->fbFormat) {
case DV_PF_565:
i915->state.Buffer[I915_DESTREG_DV1] = (DSTORG_HORT_BIAS(0x8) | /* .5 */
DSTORG_VERT_BIAS(0x8) | /* .5 */
LOD_PRECLAMP_OGL |
TEX_DEFAULT_COLOR_OGL |
DITHER_FULL_ALWAYS |
screen->fbFormat |
DEPTH_FRMT_16_FIXED);
break;
case DV_PF_8888:
i915->state.Buffer[I915_DESTREG_DV1] = (DSTORG_HORT_BIAS(0x8) | /* .5 */
DSTORG_VERT_BIAS(0x8) | /* .5 */
LOD_PRECLAMP_OGL |
TEX_DEFAULT_COLOR_OGL |
screen->fbFormat |
DEPTH_FRMT_24_FIXED_8_OTHER);
break;
}
#endif
/* scissor */
i915->state.Buffer[I915_DESTREG_SENABLE] =
(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
i915->state.Buffer[I915_DESTREG_SR0] = _3DSTATE_SCISSOR_RECT_0_CMD;
i915->state.Buffer[I915_DESTREG_SR1] = 0;
i915->state.Buffer[I915_DESTREG_SR2] = 0;
}
#if 0
{
I915_STATECHANGE(i915, I915_UPLOAD_DEFAULTS);
i915->state.Default[I915_DEFREG_C0] = _3DSTATE_DEFAULT_DIFFUSE;
i915->state.Default[I915_DEFREG_C1] = 0;
i915->state.Default[I915_DEFREG_S0] = _3DSTATE_DEFAULT_SPECULAR;
i915->state.Default[I915_DEFREG_S1] = 0;
i915->state.Default[I915_DEFREG_Z0] = _3DSTATE_DEFAULT_Z;
i915->state.Default[I915_DEFREG_Z1] = 0;
}
#endif
/* These will be emitted every at the head of every buffer, unless
* we get hardware contexts working.
*/
i915->state.active = (I915_UPLOAD_PROGRAM |
I915_UPLOAD_STIPPLE |
I915_UPLOAD_CTX |
I915_UPLOAD_BUFFERS | I915_UPLOAD_INVARIENT);
}
void I915EmitInvarientState(ScrnInfoPtr scrn)
{
intel_screen_private *intel = intel_get_screen_private(scrn);
assert(intel->in_batch_atomic);
OUT_BATCH(_3DSTATE_AA_CMD |
AA_LINE_ECAAR_WIDTH_ENABLE |
AA_LINE_ECAAR_WIDTH_1_0 |
AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);
/* Disable independent alpha blend */
OUT_BATCH(_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD |
IAB_MODIFY_ENABLE |
IAB_MODIFY_FUNC | (BLENDFUNC_ADD << IAB_FUNC_SHIFT) |
IAB_MODIFY_SRC_FACTOR | (BLENDFACT_ONE <<
IAB_SRC_FACTOR_SHIFT) |
IAB_MODIFY_DST_FACTOR | (BLENDFACT_ZERO <<
IAB_DST_FACTOR_SHIFT));
OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
OUT_BATCH(0);
OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
OUT_BATCH(0);
OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
OUT_BATCH(0);
/* Don't support texture crossbar yet */
OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS |
CSB_TCB(0, 0) |
CSB_TCB(1, 1) |
CSB_TCB(2, 2) |
CSB_TCB(3, 3) |
CSB_TCB(4, 4) |
CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7));
OUT_BATCH(_3DSTATE_RASTER_RULES_CMD |
ENABLE_POINT_RASTER_RULE |
OGL_POINT_RASTER_RULE |
ENABLE_LINE_STRIP_PROVOKE_VRTX |
ENABLE_TRI_FAN_PROVOKE_VRTX |
LINE_STRIP_PROVOKE_VRTX(1) |
TRI_FAN_PROVOKE_VRTX(2) | ENABLE_TEXKILL_3D_4D | TEXKILL_4D);
OUT_BATCH(_3DSTATE_MODES_4_CMD |
ENABLE_LOGIC_OP_FUNC | LOGIC_OP_FUNC(LOGICOP_COPY) |
ENABLE_STENCIL_WRITE_MASK | STENCIL_WRITE_MASK(0xff) |
ENABLE_STENCIL_TEST_MASK | STENCIL_TEST_MASK(0xff));
OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | I1_LOAD_S(4) | I1_LOAD_S(5) | 2);
OUT_BATCH(0x00000000); /* Disable texture coordinate wrap-shortest */
OUT_BATCH((1 << S4_POINT_WIDTH_SHIFT) |
S4_LINE_WIDTH_ONE |
S4_CULLMODE_NONE |
S4_VFMT_XY);
OUT_BATCH(0x00000000); /* Stencil. */
OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD);
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(_3DSTATE_DEPTH_SUBRECT_DISABLE);
OUT_BATCH(_3DSTATE_LOAD_INDIRECT | 0); /* disable indirect state */
OUT_BATCH(0);
OUT_BATCH(_3DSTATE_STIPPLE);
OUT_BATCH(0x00000000);
OUT_BATCH(_3DSTATE_BACKFACE_STENCIL_OPS | BFO_ENABLE_STENCIL_TWO_SIDE | 0);
}
