/**
* @brief This function handles I2C1 Event interrupt request.
* @param None
* @retval : None
*/
void I2C1_EV_IRQHandler(void)
{
__IO uint32_t SR1Register =0;
__IO uint32_t SR2Register =0;
#ifdef SLAVE_DMA_USE
/* Read SR1 register */
SR1Register = I2C1->SR1;
/* If ADDR is set */
if ((SR1Register & 0x0002) == 0x0002)
{
/* In slave Transmitter/Receiver mode, when using DMA, it is recommended to update the buffer
base address and the buffer size before clearing ADDR flag. In fact, the only
period when the slave has control on the bus(SCL is stretched so master can not initiate
transfers) is the period between ADDR is set and ADDR is cleared. Otherwise, the master can
initiate transfers and the buffer size & the buffer address have not yet been updated.*/
/* Update the DMA channels memory base address and count */
Buffer_Tx1[0]=getStateId(state);
//Buffer_Tx1[1]=getBatteryLevel(4, 3300, 3600, state.batteryState, ((uint32_t)ADC_ConvertedValueTabPointer[1])*/*41*/ADC_TO_MV_CONSTANT);
//Buffer_Tx1[1]=percent;
Buffer_Tx1[1]=(uint8_t)((((uint32_t)ADC_ConvertedValueTabPointer[1])*ADC_TO_MV_CONSTANT)/1000);
I2C_DMAConfig (I2C1, Buffer_Tx1, 0xFFFF, I2C_DIRECTION_TX);
I2C_DMAConfig (I2C1, Buffer_Rx1, 0xFFFF, I2C_DIRECTION_RX);
/* Clear ADDR by reading SR2 register */
SR2Register = I2C1->SR2;
}
#else
/* Read the I2C1 SR1 and SR2 status registers */
SR1Register = I2C1->SR1;
SR2Register = I2C1->SR2;
/* If I2C1 is slave (MSL flag = 0) */
if ((SR2Register &0x0001) != 0x0001)
{
/* If ADDR = 1: EV1 */
if ((SR1Register & 0x0002) == 0x0002)
{
/* Clear SR1Register and SR2Register variables to prepare for next IT */
SR1Register = 0;
SR2Register = 0;
/* Initialize the transmit/receive counters for next transmission/reception
using Interrupt */
Tx_Idx1 = 0;
Rx_Idx1 = 0;
/* Set the values in the buffer */
Buffer_Tx1[0]=getStateId(state);
//Buffer_Tx1[1]=getBatteryLevel(4, 3300, 3600, state.batteryState, ((uint32_t)ADC_ConvertedValueTabPointer[1])*/*41*/ADC_TO_MV_CONSTANT);
//Buffer_Tx1[1]=percent;
Buffer_Tx1[1]=(uint8_t)((((uint32_t)ADC_ConvertedValueTabPointer[1])*ADC_TO_MV_CONSTANT)/1000);
}
/* If TXE = 1: EV3 */
if ((SR1Register & 0x0080) == 0x0080)
{
/* Write data in data register */
I2C1->DR = Buffer_Tx1[Tx_Idx1++];
SR1Register = 0;
SR2Register = 0;
}
/* If RXNE = 1: EV2 */
//if ((SR1Register & 0x0040) == 0x0040)
//{
// /* Read data from data register */
// Buffer_Rx1[Rx_Idx1++] = I2C1->DR;
// SR1Register = 0;
// SR2Register = 0;
//}
/* If STOPF =1: EV4 (Slave has detected a STOP condition on the bus */
if (( SR1Register & 0x0010) == 0x0010)
{
I2C1->CR1 |= CR1_PE_Set;
SR1Register = 0;
SR2Register = 0;
}
} /* End slave mode */
#endif
/* If SB = 1, I2C1 master sent a START on the bus: EV5) */
if ((SR1Register &0x0001) == 0x0001)
{
/* Send the slave address for transmssion or for reception (according to the configured value
in the write master write routine */
I2C1->DR = Address;
SR1Register = 0;
SR2Register = 0;
}
}
/**
* @brief Reads buffer of bytes from the slave.
* @param pBuffer: Buffer of bytes to be read from the slave.
* @param NumByteToRead: Number of bytes to be read by the Master.
* @param Mode: Polling or DMA or Interrupt having the highest priority in the application.
* @param SlaveAddress: The address of the slave to be addressed by the Master.
* @retval : None.
*/
ErrorStatus I2C_Master_BufferRead(I2C_TypeDef* I2Cx, uint8_t* pBuffer,
uint32_t NumByteToRead, I2C_ProgrammingModel Mode, uint8_t SlaveAddress,
uint32_t timeoutMs)
{
__IO uint32_t temp = 0;
__IO uint32_t Timeout = 0;
/* Enable I2C errors interrupts (used in all modes: Polling, DMA and Interrupts */
I2Cx->CR2 |= I2C_IT_ERR;
if (Mode == DMA) /* I2Cx Master Reception using DMA */
{
/* Configure I2Cx DMA channel */
I2C_DMAConfig(I2Cx, pBuffer, NumByteToRead, I2C_DIRECTION_RX);
/* Set Last bit to have a NACK on the last received byte */
I2Cx->CR2 |= CR2_LAST_Set;
/* Enable I2C DMA requests */
I2Cx->CR2 |= CR2_DMAEN_Set;
Timeout = 0xFFFF;
/* Send START condition */
I2Cx->CR1 |= CR1_START_Set;
/* Wait until SB flag is set: EV5 */
while ((I2Cx->SR1 & 0x0001) != 0x0001)
{
if (Timeout-- == 0)
return ERROR;
}
Timeout = 0xFFFF;
/* Send slave address */
/* Set the address bit0 for read */
SlaveAddress |= OAR1_ADD0_Set;
Address = SlaveAddress;
/* Send the slave address */
I2Cx->DR = Address;
/* Wait until ADDR is set: EV6 */
while ((I2Cx->SR1 & 0x0002) != 0x0002)
{
if (Timeout-- == 0)
return ERROR;
}
/* Clear ADDR flag by reading SR2 register */
temp = I2Cx->SR2;
if (I2Cx == I2C1)
{
/* Wait until DMA end of transfer */
while (!DMA_GetFlagStatus(DMA1_FLAG_TC7));
//xSemaphoreTake(i2cdevDmaEventI2c1, M2T(timeoutMs));
/* Disable DMA Channel */
DMA_Cmd(I2C1_DMA_CHANNEL_RX, DISABLE);
/* Clear the DMA Transfer Complete flag */
DMA_ClearFlag(DMA1_FLAG_TC7);
}
else /* I2Cx = I2C2*/
{
/* Wait until DMA end of transfer */
while (!DMA_GetFlagStatus(DMA1_FLAG_TC5));
//xSemaphoreTake(i2cdevDmaEventI2c2, M2T(timeoutMs));
/* Disable DMA Channel */
DMA_Cmd(I2C2_DMA_CHANNEL_RX, DISABLE);
/* Clear the DMA Transfer Complete flag */
DMA_ClearFlag(DMA1_FLAG_TC5);
}
/* Program the STOP */
I2Cx->CR1 |= CR1_STOP_Set;
/* Make sure that the STOP bit is cleared by Hardware before CR1 write access */
while ((I2Cx->CR1 & 0x200) == 0x200)
;
}
/* I2Cx Master Reception using Interrupts with highest priority in an application */
else
{
/* Enable EVT IT*/
I2Cx->CR2 |= I2C_IT_EVT;
/* Enable BUF IT */
I2Cx->CR2 |= I2C_IT_BUF;
/* Set the I2C direction to reception */
I2CDirection = I2C_DIRECTION_RX;
Buffer_Rx1 = pBuffer;
SlaveAddress |= OAR1_ADD0_Set;
Address = SlaveAddress;
if (I2Cx == I2C1)
NumbOfBytes1 = NumByteToRead;
else
NumbOfBytes2 = NumByteToRead;
/* Send START condition */
I2Cx->CR1 |= CR1_START_Set;
Timeout = timeoutMs * I2CDEV_LOOPS_PER_MS;
/* Wait until the START condition is generated on the bus: START bit is cleared by hardware */
while ((I2Cx->CR1 & 0x100) == 0x100 && Timeout)
{
Timeout--;
}
/* Wait until BUSY flag is reset (until a STOP is generated) */
while ((I2Cx->SR2 & 0x0002) == 0x0002 && Timeout)
{
Timeout--;
}
/* Enable Acknowledgement to be ready for another reception */
I2Cx->CR1 |= CR1_ACK_Set;
if (Timeout == 0)
return ERROR;
}
return SUCCESS;
temp++; //To avoid GCC warning!
}
/**
* @brief Writes buffer of bytes.
* @param pBuffer: Buffer of bytes to be sent to the slave.
* @param NumByteToWrite: Number of bytes to be sent by the Master.
* @param Mode: Polling or DMA or Interrupt having the highest priority in the application.
* @param SlaveAddress: The address of the slave to be addressed by the Master.
* @retval : None.
*/
ErrorStatus I2C_Master_BufferWrite(I2C_TypeDef* I2Cx, uint8_t* pBuffer,
uint32_t NumByteToWrite, I2C_ProgrammingModel Mode, uint8_t SlaveAddress,
uint32_t timeoutMs)
{
__IO uint32_t temp = 0;
__IO uint32_t Timeout = 0;
/* Enable Error IT (used in all modes: DMA, Polling and Interrupts */
I2Cx->CR2 |= I2C_IT_ERR;
if (Mode == DMA) /* I2Cx Master Transmission using DMA */
{
Timeout = 0xFFFF;
/* Configure the DMA channel for I2Cx transmission */
I2C_DMAConfig(I2Cx, pBuffer, NumByteToWrite, I2C_DIRECTION_TX);
/* Enable the I2Cx DMA requests */
I2Cx->CR2 |= CR2_DMAEN_Set;
/* Send START condition */
I2Cx->CR1 |= CR1_START_Set;
/* Wait until SB flag is set: EV5 */
while ((I2Cx->SR1 & 0x0001) != 0x0001)
{
if (Timeout-- == 0)
return ERROR;
}
Timeout = 0xFFFF;
/* Send slave address */
/* Reset the address bit0 for write */
SlaveAddress &= OAR1_ADD0_Reset;
Address = SlaveAddress;
/* Send the slave address */
I2Cx->DR = Address;
/* Wait until ADDR is set: EV6 */
while ((I2Cx->SR1 & 0x0002) != 0x0002)
{
if (Timeout-- == 0)
return ERROR;
}
/* Clear ADDR flag by reading SR2 register */
temp = I2Cx->SR2;
if (I2Cx == I2C1)
{
/* Wait until DMA end of transfer */
// while (!DMA_GetFlagStatus(DMA1_FLAG_TC6));
xSemaphoreTake(i2cdevDmaEventI2c1, M2T(5));
/* Disable the DMA1 Channel 6 */
DMA_Cmd(I2C1_DMA_CHANNEL_TX, DISABLE);
/* Clear the DMA Transfer complete flag */
DMA_ClearFlag(DMA1_FLAG_TC6);
}
else /* I2Cx = I2C2 */
{
/* Wait until DMA end of transfer */
//while (!DMA_GetFlagStatus(DMA1_FLAG_TC4))
xSemaphoreTake(i2cdevDmaEventI2c2, M2T(5));
/* Disable the DMA1 Channel 4 */
DMA_Cmd(I2C2_DMA_CHANNEL_TX, DISABLE);
/* Clear the DMA Transfer complete flag */
DMA_ClearFlag(DMA1_FLAG_TC4);
}
/* EV8_2: Wait until BTF is set before programming the STOP */
while ((I2Cx->SR1 & 0x00004) != 0x000004)
;
/* Program the STOP */
I2Cx->CR1 |= CR1_STOP_Set;
/* Make sure that the STOP bit is cleared by Hardware */
while ((I2Cx->CR1 & 0x200) == 0x200)
;
}
/* I2Cx Master Transmission using Interrupt with highest priority in the application */
else
{
/* Enable EVT IT*/
I2Cx->CR2 |= I2C_IT_EVT;
/* Enable BUF IT */
I2Cx->CR2 |= I2C_IT_BUF;
/* Set the I2C direction to Transmission */
I2CDirection = I2C_DIRECTION_TX;
Buffer_Tx1 = pBuffer;
SlaveAddress &= OAR1_ADD0_Reset;
Address = SlaveAddress;
if (I2Cx == I2C1)
NumbOfBytes1 = NumByteToWrite;
else
NumbOfBytes2 = NumByteToWrite;
/* Send START condition */
I2Cx->CR1 |= CR1_START_Set;
Timeout = timeoutMs * I2CDEV_LOOPS_PER_MS;
/* Wait until the START condition is generated on the bus: the START bit is cleared by hardware */
while ((I2Cx->CR1 & 0x100) == 0x100 && Timeout)
{
Timeout--;
}
/* Wait until BUSY flag is reset: a STOP has been generated on the bus signaling the end
of transmission */
while ((I2Cx->SR2 & 0x0002) == 0x0002 && Timeout)
{
Timeout--;
}
if (Timeout == 0)
return ERROR;
}
return SUCCESS;
temp++; //To avoid GCC warning!
}
/*
Only 1 byte READ using Interrupt or Polling otherwise using DMA
*/
void I2C1_EV_IRQHandler()
{
__IO uint16_t regSR1, regSR2;
__IO uint32_t regSR;
int i=10;
rt_interrupt_enter();
//rt_hw_led_on(10);
regSR1 = I2C1->SR1;
regSR2 = I2C1->SR2;
regSR = (regSR2 << 16) | regSR1;
//rt_kprintf("EV=> SR1: 0x%x\tSR2: 0x%x\tSR: 0x%x status: %d\n", regSR1, regSR2, regSR, i2cStatus);
if( (regSR & I2C_EVENT_MASTER_MODE_SELECT) == I2C_EVENT_MASTER_MODE_SELECT) //EV5
{
if( i2cStatus == S1 ) //Send TX Command
{
I2C1->DR = DevAddr & 0xFE;
i2cStatus = S2;
}
else if( i2cStatus == S4 ) //Send RX Command
{
I2C1->DR = DevAddr | 0x01;
i2cStatus = S5;
}
regSR1 = 0;
regSR2 = 0;
}
if( (regSR & I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED)== I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ) //EV6
{
switch( i2cStatus )
{
case S2: //Send 1st memory address phase
{
//I2C_DMACmd(I2C1, ENABLE);
I2C1->DR = MemAddr[0];
if( memtype == I2C_MEM_1Byte )
i2cStatus = S2_2;
else if( memtype == I2C_MEM_2Bytes )
i2cStatus = S2_1;
}
break;
case S5: //Set RX buffer phase
{
if( i2cFlag == I2C_READ_DMA )
{
I2C_DMAConfig(I2C1, i2c_buf, BufSize, I2C_DIRECTION_RX);
I2C1->CR2 |= CR2_LAST_Set | CR2_DMAEN_Set;
DMA_ITConfig( I2C1_DMA_CHANNEL_RX, DMA_IT_TC, ENABLE);
}
else if( i2cFlag == I2C_READ_INTERRUPT )
{
I2C1->CR2 |= I2C_IT_BUF;
I2C1->CR1 &= CR1_ACK_Reset;
/* Program the STOP */
I2C1->CR1 |= CR1_STOP_Set;
}
i2cStatus = S6;
}
break;
}
regSR1 = 0;
regSR2 = 0;
//dump_i2c_register(I2C1);
}
if((regSR & I2C_EVENT_MASTER_BYTE_RECEIVED) == I2C_EVENT_MASTER_BYTE_RECEIVED) //EV7
{
//Interrupt RX complete phase
if( i2cStatus == S6 && i2cFlag == I2C_READ_INTERRUPT )
{
*i2c_buf = I2C1->DR;
i2cStatus = S_STOP;
rt_event_send(&i2c_event, I2C_COMPLETE);
}
}
if( (regSR & I2C_EVENT_MASTER_BYTE_TRANSMITTED) == I2C_EVENT_MASTER_BYTE_TRANSMITTED ) //EV8_2
{
//Start TX/RX phase
if(i2cStatus == S3)
{
DMA_ClearFlag(I2C1_DMA_CHANNEL_TX, DMA_FLAG_TCIF6 );
DMA_Cmd(I2C1_DMA_CHANNEL_TX, DISABLE);
switch (i2cFlag)
{
case I2C_WRITE:
i2cStatus = S_STOP;
I2C1->CR1 |= CR1_STOP_Set;
rt_event_send(&i2c_event, I2C_COMPLETE);
break;
case I2C_READ_DMA:
i2cStatus = S4;
I2C1->CR1 |= CR1_START_Set;
break;
case I2C_READ_POLLING:
i2cStatus = S_STOP;
rt_event_send(&i2c_event, I2C_COMPLETE);
I2C1->CR2 &= ~(CR2_LAST_Set | I2C_IT_EVT | CR2_DMAEN_Set);
I2C1->CR1 |= CR1_START_Set;
break;
case I2C_READ_INTERRUPT:
i2cStatus = S4;
I2C1->CR1 |= CR1_START_Set;
break;
}
}
if( i2cStatus == S2_1 ) //Send 2nd memory address
{
if( memtype == I2C_MEM_2Bytes ) //memory address has 2 bytes
{
I2C1->DR = MemAddr[1];
i2cStatus = S2_2;
}
if( i2cFlag == I2C_READ_POLLING || i2cFlag == I2C_READ_DMA || i2cFlag == I2C_READ_INTERRUPT)
{
i2cStatus = S3;
}
}
if( i2cStatus == S2_2 ) //Set TX DAM phase
{
I2C_DMAConfig(I2C1, i2c_buf, BufSize, I2C_DIRECTION_TX);
I2C1->CR2 |= CR2_DMAEN_Set;
i2cStatus = S3;
}
}
rt_interrupt_leave();
}
/**
* @brief Reads buffer of bytes from the slave.
* @param pBuffer: Buffer of bytes to be read from the slave.
* @param NumByteToRead: Number of bytes to be read by the Master.
* @param Mode: Polling or DMA or Interrupt having the highest priority in the application.
* @param SlaveAddress: The address of the slave to be addressed by the Master.
* @retval : None.
*/
Status I2C_Master_BufferRead(I2C_TypeDef* I2Cx, uint8_t* pBuffer, uint32_t NumByteToRead, I2C_ProgrammingModel Mode, uint8_t SlaveAddress)
{
__IO uint32_t temp = 0;
__IO uint32_t Timeout = 0;
/* Enable I2C errors interrupts (used in all modes: Polling, DMA and Interrupts */
I2Cx->CR2 |= I2C_IT_ERR;
if (Mode == DMA) /* I2Cx Master Reception using DMA */
{
/* Configure I2Cx DMA channel */
I2C_DMAConfig(I2Cx, pBuffer, NumByteToRead, I2C_DIRECTION_RX);
/* Set Last bit to have a NACK on the last received byte */
I2Cx->CR2 |= CR2_LAST_Set;
/* Enable I2C DMA requests */
I2Cx->CR2 |= CR2_DMAEN_Set;
Timeout = 0xFFFF;
/* Send START condition */
I2Cx->CR1 |= CR1_START_Set;
/* Wait until SB flag is set: EV5 */
while ((I2Cx->SR1&0x0001) != 0x0001)
{
if (Timeout-- == 0)
return Error;
}
Timeout = 0xFFFF;
/* Send slave address */
/* Set the address bit0 for read */
SlaveAddress |= OAR1_ADD0_Set;
Address = SlaveAddress;
/* Send the slave address */
I2Cx->DR = Address;
/* Wait until ADDR is set: EV6 */
while ((I2Cx->SR1&0x0002) != 0x0002)
{
if (Timeout-- == 0)
return Error;
}
/* Clear ADDR flag by reading SR2 register */
temp = I2Cx->SR2;
if (I2Cx == I2C1)
{
/* Wait until DMA end of transfer */
while (!DMA_GetFlagStatus(DMA1_FLAG_TC7));
/* Disable DMA Channel */
DMA_Cmd(I2C1_DMA_CHANNEL_RX, DISABLE);
/* Clear the DMA Transfer Complete flag */
DMA_ClearFlag(DMA1_FLAG_TC7);
}
else /* I2Cx = I2C2*/
{
/* Wait until DMA end of transfer */
while (!DMA_GetFlagStatus(DMA1_FLAG_TC5));
/* Disable DMA Channel */
DMA_Cmd(I2C2_DMA_CHANNEL_RX, DISABLE);
/* Clear the DMA Transfer Complete flag */
DMA_ClearFlag(DMA1_FLAG_TC5);
}
/* Program the STOP */
I2Cx->CR1 |= CR1_STOP_Set;
/* Make sure that the STOP bit is cleared by Hardware before CR1 write access */
while ((I2Cx->CR1&0x200) == 0x200);
}
else if (Mode == Polling) /* I2Cx Master Reception using Polling */
{
if (NumByteToRead == 1)
{
Timeout = 0xFFFF;
/* Send START condition */
I2Cx->CR1 |= CR1_START_Set;
/* Wait until SB flag is set: EV5 */
while ((I2Cx->SR1&0x0001) != 0x0001)
{
if (Timeout-- == 0)
return Error;
}
/* Send slave address */
/* Reset the address bit0 for read */
SlaveAddress |= OAR1_ADD0_Set;
Address = SlaveAddress;
/* Send the slave address */
I2Cx->DR = Address;
/* Wait until ADDR is set: EV6_3, then program ACK = 0, clear ADDR
and program the STOP just after ADDR is cleared. The EV6_3
software sequence must complete before the current byte end of transfer.*/
/* Wait until ADDR is set */
Timeout = 0xFFFF;
while ((I2Cx->SR1&0x0002) != 0x0002)
{
if (Timeout-- == 0)
return Error;
}
/* Clear ACK bit */
I2Cx->CR1 &= CR1_ACK_Reset;
/* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
software sequence must complete before the current byte end of transfer */
__disable_irq();
/* Clear ADDR flag */
temp = I2Cx->SR2;
/* Program the STOP */
I2Cx->CR1 |= CR1_STOP_Set;
/* Re-enable IRQs */
__enable_irq();
/* Wait until a data is received in DR register (RXNE = 1) EV7 */
while ((I2Cx->SR1 & 0x00040) != 0x000040);
/* Read the data */
*pBuffer = I2Cx->DR;
/* Make sure that the STOP bit is cleared by Hardware before CR1 write access */
while ((I2Cx->CR1&0x200) == 0x200);
/* Enable Acknowledgement to be ready for another reception */
I2Cx->CR1 |= CR1_ACK_Set;
}
else if (NumByteToRead == 2)
{
/* Set POS bit */
I2Cx->CR1 |= CR1_POS_Set;
Timeout = 0xFFFF;
/* Send START condition */
I2Cx->CR1 |= CR1_START_Set;
/* Wait until SB flag is set: EV5 */
while ((I2Cx->SR1&0x0001) != 0x0001)
{
if (Timeout-- == 0)
return Error;
}
Timeout = 0xFFFF;
/* Send slave address */
/* Set the address bit0 for read */
SlaveAddress |= OAR1_ADD0_Set;
Address = SlaveAddress;
/* Send the slave address */
I2Cx->DR = Address;
/* Wait until ADDR is set: EV6 */
while ((I2Cx->SR1&0x0002) != 0x0002)
{
if (Timeout-- == 0)
return Error;
}
/* EV6_1: The acknowledge disable should be done just after EV6,
that is after ADDR is cleared, so disable all active IRQs around ADDR clearing and
ACK clearing */
__disable_irq();
/* Clear ADDR by reading SR2 register */
temp = I2Cx->SR2;
/* Clear ACK */
I2Cx->CR1 &= CR1_ACK_Reset;
/*Re-enable IRQs */
__enable_irq();
/* Wait until BTF is set */
while ((I2Cx->SR1 & 0x00004) != 0x000004);
/* Disable IRQs around STOP programming and data reading because of the limitation ?*/
__disable_irq();
/* Program the STOP */
I2C_GenerateSTOP(I2Cx, ENABLE);
/* Read first data */
*pBuffer = I2Cx->DR;
/* Re-enable IRQs */
__enable_irq();
/**/
pBuffer++;
/* Read second data */
*pBuffer = I2Cx->DR;
/* Make sure that the STOP bit is cleared by Hardware before CR1 write access */
while ((I2Cx->CR1&0x200) == 0x200);
/* Enable Acknowledgement to be ready for another reception */
I2Cx->CR1 |= CR1_ACK_Set;
/* Clear POS bit */
I2Cx->CR1 &= CR1_POS_Reset;
}
else
{
Timeout = 0xFFFF;
/* Send START condition */
I2Cx->CR1 |= CR1_START_Set;
/* Wait until SB flag is set: EV5 */
while ((I2Cx->SR1&0x0001) != 0x0001)
{
if (Timeout-- == 0)
return Error;
}
Timeout = 0xFFFF;
/* Send slave address */
/* Reset the address bit0 for write */
SlaveAddress |= OAR1_ADD0_Set;;
Address = SlaveAddress;
/* Send the slave address */
I2Cx->DR = Address;
/* Wait until ADDR is set: EV6 */
while ((I2Cx->SR1&0x0002) != 0x0002)
{
if (Timeout-- == 0)
return Error;
}
/* Clear ADDR by reading SR2 status register */
temp = I2Cx->SR2;
/* While there is data to be read */
while (NumByteToRead)
{
/* Receive bytes from first byte until byte N-3 */
if (NumByteToRead != 3)
{
/* Poll on BTF to receive data because in polling mode we can not guarantee the
EV7 software sequence is managed before the current byte transfer completes */
while ((I2Cx->SR1 & 0x00004) != 0x000004);
/* Read data */
*pBuffer = I2Cx->DR;
/* */
pBuffer++;
/* Decrement the read bytes counter */
NumByteToRead--;
}
/* it remains to read three data: data N-2, data N-1, Data N */
if (NumByteToRead == 3)
{
/* Wait until BTF is set: Data N-2 in DR and data N -1 in shift register */
while ((I2Cx->SR1 & 0x00004) != 0x000004);
/* Clear ACK */
I2Cx->CR1 &= CR1_ACK_Reset;
/* Disable IRQs around data reading and STOP programming because of the
limitation ? */
__disable_irq();
/* Read Data N-2 */
*pBuffer = I2Cx->DR;
/* Increment */
pBuffer++;
/* Program the STOP */
I2Cx->CR1 |= CR1_STOP_Set;
/* Read DataN-1 */
*pBuffer = I2Cx->DR;
/* Re-enable IRQs */
__enable_irq();
/* Increment */
pBuffer++;
/* Wait until RXNE is set (DR contains the last data) */
while ((I2Cx->SR1 & 0x00040) != 0x000040);
/* Read DataN */
*pBuffer = I2Cx->DR;
/* Reset the number of bytes to be read by master */
NumByteToRead = 0;
}
}
/* Make sure that the STOP bit is cleared by Hardware before CR1 write access */
while ((I2Cx->CR1&0x200) == 0x200);
/* Enable Acknowledgement to be ready for another reception */
I2Cx->CR1 |= CR1_ACK_Set;
}
}
else /* I2Cx Master Reception using Interrupts with highest priority in an application */
{
/* Enable EVT IT*/
I2Cx->CR2 |= I2C_IT_EVT;
/* Enable BUF IT */
I2Cx->CR2 |= I2C_IT_BUF;
/* Set the I2C direction to reception */
I2CDirection = I2C_DIRECTION_RX;
SlaveAddress |= OAR1_ADD0_Set;
Address = SlaveAddress;
if (I2Cx == I2C1) NumbOfBytes1 = NumByteToRead;
else NumbOfBytes2 = NumByteToRead;
/* Send START condition */
I2Cx->CR1 |= CR1_START_Set;
/* Wait until the START condition is generated on the bus: START bit is cleared by hardware */
while ((I2Cx->CR1&0x100) == 0x100);
/* Wait until BUSY flag is reset (until a STOP is generated) */
while ((I2Cx->SR2 &0x0002) == 0x0002);
/* Enable Acknowledgement to be ready for another reception */
I2Cx->CR1 |= CR1_ACK_Set;
}
return Success;
}
/**
* @brief Writes buffer of bytes.
* @param pBuffer: Buffer of bytes to be sent to the slave.
* @param NumByteToWrite: Number of bytes to be sent by the Master.
* @param Mode: Polling or DMA or Interrupt having the highest priority in the application.
* @param SlaveAddress: The address of the slave to be addressed by the Master.
* @retval : None.
*/
Status I2C_Master_BufferWrite(I2C_TypeDef* I2Cx, uint8_t* pBuffer, uint32_t NumByteToWrite, I2C_ProgrammingModel Mode, uint8_t SlaveAddress )
{
__IO uint32_t temp = 0;
__IO uint32_t Timeout = 0;
/* Enable Error IT (used in all modes: DMA, Polling and Interrupts */
I2Cx->CR2 |= I2C_IT_ERR;
if (Mode == DMA) /* I2Cx Master Transmission using DMA */
{
Timeout = 0xFFFF;
/* Configure the DMA channel for I2Cx transmission */
I2C_DMAConfig (I2Cx, pBuffer, NumByteToWrite, I2C_DIRECTION_TX);
/* Enable the I2Cx DMA requests */
I2Cx->CR2 |= CR2_DMAEN_Set;
/* Send START condition */
I2Cx->CR1 |= CR1_START_Set;
/* Wait until SB flag is set: EV5 */
while ((I2Cx->SR1&0x0001) != 0x0001)
{
if (Timeout-- == 0)
return Error;
}
Timeout = 0xFFFF;
/* Send slave address */
/* Reset the address bit0 for write */
SlaveAddress &= OAR1_ADD0_Reset;
Address = SlaveAddress;
/* Send the slave address */
I2Cx->DR = Address;
/* Wait until ADDR is set: EV6 */
while ((I2Cx->SR1&0x0002) != 0x0002)
{
if (Timeout-- == 0)
return Error;
}
/* Clear ADDR flag by reading SR2 register */
temp = I2Cx->SR2;
if (I2Cx == I2C1)
{
/* Wait until DMA end of transfer */
while (!DMA_GetFlagStatus(DMA1_FLAG_TC6));
/* Disable the DMA1 Channel 6 */
DMA_Cmd(I2C1_DMA_CHANNEL_TX, DISABLE);
/* Clear the DMA Transfer complete flag */
DMA_ClearFlag(DMA1_FLAG_TC6);
}
else /* I2Cx = I2C2 */
{
/* Wait until DMA end of transfer */
while (!DMA_GetFlagStatus(DMA1_FLAG_TC4));
/* Disable the DMA1 Channel 4 */
DMA_Cmd(I2C2_DMA_CHANNEL_TX, DISABLE);
/* Clear the DMA Transfer complete flag */
DMA_ClearFlag(DMA1_FLAG_TC4);
}
/* EV8_2: Wait until BTF is set before programming the STOP */
while ((I2Cx->SR1 & 0x00004) != 0x000004);
/* Program the STOP */
I2Cx->CR1 |= CR1_STOP_Set;
/* Make sure that the STOP bit is cleared by Hardware */
while ((I2Cx->CR1&0x200) == 0x200);
}
else if (Mode == Polling) /* I2Cx Master Transmission using Polling */
{
Timeout = 0xFFFF;
/* Send START condition */
I2Cx->CR1 |= CR1_START_Set;
/* Wait until SB flag is set: EV5 */
while ((I2Cx->SR1&0x0001) != 0x0001)
{
if (Timeout-- == 0)
return Error;
}
/* Send slave address */
/* Reset the address bit0 for write*/
SlaveAddress &= OAR1_ADD0_Reset;
Address = SlaveAddress;
/* Send the slave address */
I2Cx->DR = Address;
Timeout = 0xFFFF;
/* Wait until ADDR is set: EV6 */
while ((I2Cx->SR1 &0x0002) != 0x0002)
{
if (Timeout-- == 0)
return Error;
}
/* Clear ADDR flag by reading SR2 register */
temp = I2Cx->SR2;
/* Write the first data in DR register (EV8_1) */
I2Cx->DR = *pBuffer;
/* Increment */
pBuffer++;
/* Decrement the number of bytes to be written */
NumByteToWrite--;
/* While there is data to be written */
while (NumByteToWrite--)
{
/* Poll on BTF to receive data because in polling mode we can not guarantee the
EV8 software sequence is managed before the current byte transfer completes */
while ((I2Cx->SR1 & 0x00004) != 0x000004);
/* Send the current byte */
I2Cx->DR = *pBuffer;
/* Point to the next byte to be written */
pBuffer++;
}
/* EV8_2: Wait until BTF is set before programming the STOP */
while ((I2Cx->SR1 & 0x00004) != 0x000004);
/* Send STOP condition */
I2Cx->CR1 |= CR1_STOP_Set;
/* Make sure that the STOP bit is cleared by Hardware */
while ((I2Cx->CR1&0x200) == 0x200);
}
else /* I2Cx Master Transmission using Interrupt with highest priority in the application */
{
/* Enable EVT IT*/
I2Cx->CR2 |= I2C_IT_EVT;
/* Enable BUF IT */
I2Cx->CR2 |= I2C_IT_BUF;
/* Set the I2C direction to Transmission */
I2CDirection = I2C_DIRECTION_TX;
SlaveAddress &= OAR1_ADD0_Reset;
Address = SlaveAddress;
if (I2Cx == I2C1) NumbOfBytes1 = NumByteToWrite;
else NumbOfBytes2 = NumByteToWrite;
/* Send START condition */
I2Cx->CR1 |= CR1_START_Set;
/* Wait until the START condition is generated on the bus: the START bit is cleared by hardware */
while ((I2Cx->CR1&0x100) == 0x100);
/* Wait until BUSY flag is reset: a STOP has been generated on the bus signaling the end
of transmission */
while ((I2Cx->SR2 &0x0002) == 0x0002);
}
return Success;
}
