static void
ar9285WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan)
{
u_int modesIndex, freqIndex;
int regWrites = 0;
/* Setup the indices for the next set of register array writes */
/* XXX Ignore 11n dynamic mode on the AR5416 for the moment */
freqIndex = 2;
if (IEEE80211_IS_CHAN_HT40(chan))
modesIndex = 3;
else if (IEEE80211_IS_CHAN_108G(chan))
modesIndex = 5;
else
modesIndex = 4;
/* Set correct Baseband to analog shift setting to access analog chips. */
OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes,
modesIndex, regWrites);
if (AR_SREV_KITE_12_OR_LATER(ah)) {
regWrites = ath_hal_ini_write(ah, &AH9285(ah)->ah_ini_txgain,
modesIndex, regWrites);
}
regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common,
1, regWrites);
}
/*
* ADC GAIN/DC offset calibration is for calibrating two ADCs that
* are acting as one by interleaving incoming symbols. This isn't
* relevant for 2.4GHz 20MHz wide modes because, as far as I can tell,
* the secondary ADC is never enabled. It is enabled however for
* 5GHz modes.
*
* It hasn't been confirmed whether doing this calibration is needed
* at all in the above modes and/or whether it's actually harmful.
* So for now, let's leave it enabled and just remember to get
* confirmation that it needs to be clarified.
*
* See US Patent No: US 7,541,952 B1:
* " Method and Apparatus for Offset and Gain Compensation for
* Analog-to-Digital Converters."
*/
static OS_INLINE HAL_BOOL
ar5416IsCalSupp(struct ath_hal *ah, const struct ieee80211_channel *chan,
HAL_CAL_TYPE calType)
{
struct ar5416PerCal *cal = &AH5416(ah)->ah_cal;
switch (calType & cal->suppCals) {
case IQ_MISMATCH_CAL:
/* Run IQ Mismatch for non-CCK only */
return !IEEE80211_IS_CHAN_B(chan);
case ADC_GAIN_CAL:
case ADC_DC_CAL:
/*
* Run ADC Gain Cal for either 5ghz any or 2ghz HT40.
*
* Don't run ADC calibrations for 5ghz fast clock mode
* in HT20 - only one ADC is used.
*/
if (IEEE80211_IS_CHAN_HT20(chan) &&
(IS_5GHZ_FAST_CLOCK_EN(ah, chan)))
return AH_FALSE;
if (IEEE80211_IS_CHAN_5GHZ(chan))
return AH_TRUE;
if (IEEE80211_IS_CHAN_HT40(chan))
return AH_TRUE;
return AH_FALSE;
}
return AH_FALSE;
}
static void
r12a_tx_set_sgi(struct rtwn_softc *sc, void *buf, struct ieee80211_node *ni)
{
struct r12a_tx_desc *txd = (struct r12a_tx_desc *)buf;
struct ieee80211vap *vap = ni->ni_vap;
if ((vap->iv_flags_ht & IEEE80211_FHT_SHORTGI20) && /* HT20 */
(ni->ni_htcap & IEEE80211_HTCAP_SHORTGI20))
txd->txdw5 |= htole32(R12A_TXDW5_DATA_SHORT);
else if (ni->ni_chan != IEEE80211_CHAN_ANYC && /* HT40 */
IEEE80211_IS_CHAN_HT40(ni->ni_chan) &&
(ni->ni_htcap & IEEE80211_HTCAP_SHORTGI40) &&
(vap->iv_flags_ht & IEEE80211_FHT_SHORTGI40))
txd->txdw5 |= htole32(R12A_TXDW5_DATA_SHORT);
}
/*
* Enable radar check. Return 1 if the driver should
* enable radar PHY errors, or 0 if not.
*/
int
ath_dfs_radar_enable(struct ath_softc *sc, struct ieee80211_channel *chan)
{
#if 0
HAL_PHYERR_PARAM pe;
/* Check if the hardware supports radar reporting */
/* XXX TODO: migrate HAL_CAP_RADAR/HAL_CAP_AR to somewhere public! */
if (ath_hal_getcapability(sc->sc_ah,
HAL_CAP_PHYDIAG, 0, NULL) != HAL_OK)
return (0);
/* Check if the current channel is radar-enabled */
if (! IEEE80211_IS_CHAN_DFS(chan))
return (0);
/* Fetch the default parameters */
memset(&pe, '\0', sizeof(pe));
if (! ath_hal_getdfsdefaultthresh(sc->sc_ah, &pe))
return (0);
/* Enable radar PHY error reporting */
sc->sc_dodfs = 1;
/* Tell the hardware to enable radar reporting */
pe.pe_enabled = 1;
/* Flip on extension channel events only if doing HT40 */
if (IEEE80211_IS_CHAN_HT40(chan))
pe.pe_extchannel = 1;
else
pe.pe_extchannel = 0;
ath_hal_enabledfs(sc->sc_ah, &pe);
/*
* Disable strong signal fast diversity - needed for
* AR5212 and similar PHYs for reliable short pulse
* duration.
*/
(void) ath_hal_setcapability(sc->sc_ah, HAL_CAP_DIVERSITY, 2, 0, NULL);
return (1);
#else
return (0);
#endif
}
static void
r12a_tx_set_ht40(struct rtwn_softc *sc, void *buf, struct ieee80211_node *ni)
{
struct r12a_tx_desc *txd = (struct r12a_tx_desc *)buf;
/* XXX 80 Mhz */
if (ni->ni_chan != IEEE80211_CHAN_ANYC &&
IEEE80211_IS_CHAN_HT40(ni->ni_chan)) {
int prim_chan;
prim_chan = r12a_get_primary_channel(sc, ni->ni_chan);
txd->txdw5 |= htole32(SM(R12A_TXDW5_DATA_BW,
R12A_TXDW5_DATA_BW40));
txd->txdw5 |= htole32(SM(R12A_TXDW5_DATA_PRIM_CHAN,
prim_chan));
}
}
void
r92c_set_chan(struct rtwn_softc *sc, struct ieee80211_channel *c)
{
struct r92c_softc *rs = sc->sc_priv;
u_int chan;
int i;
chan = rtwn_chan2centieee(c);
/* Set Tx power for this new channel. */
r92c_set_txpower(sc, c);
for (i = 0; i < sc->nrxchains; i++) {
rtwn_rf_write(sc, i, R92C_RF_CHNLBW,
RW(rs->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan));
}
if (IEEE80211_IS_CHAN_HT40(c))
r92c_set_bw40(sc, chan, IEEE80211_IS_CHAN_HT40U(c));
else
rtwn_r92c_set_bw20(sc, chan);
}
HAL_BOOL
ar9300_reset_freebsd(struct ath_hal *ah, HAL_OPMODE opmode,
struct ieee80211_channel *chan, HAL_BOOL bChannelChange,
HAL_STATUS *status)
{
HAL_BOOL r;
HAL_HT_MACMODE macmode;
struct ath_hal_private *ap = AH_PRIVATE(ah);
macmode =
IEEE80211_IS_CHAN_HT40(chan) ?
HAL_HT_MACMODE_2040 : HAL_HT_MACMODE_20;
r = ar9300_reset(ah, opmode, chan, macmode,
ap->ah_caps.halTxChainMask,
ap->ah_caps.halRxChainMask,
HAL_HT_EXTPROTSPACING_20, /* always 20Mhz channel spacing */
bChannelChange,
status,
AH_FALSE); /* XXX should really extend ath_hal_reset() */
return (r);
}
/* XXX recheck */
void
r92c_get_txpower(struct rtwn_softc *sc, int chain,
struct ieee80211_channel *c, uint16_t power[RTWN_RIDX_COUNT])
{
struct r92c_softc *rs = sc->sc_priv;
struct rtwn_r92c_txpwr *rt = rs->rs_txpwr;
const struct rtwn_r92c_txagc *base = rs->rs_txagc;
uint8_t ofdmpow, htpow, diff, max;
int max_mcs, ridx, group;
/* Determine channel group. */
group = r92c_get_power_group(sc, c);
if (group == -1) { /* shouldn't happen */
device_printf(sc->sc_dev, "%s: incorrect channel\n", __func__);
return;
}
/* XXX net80211 regulatory */
max_mcs = RTWN_RIDX_MCS(sc->ntxchains * 8 - 1);
KASSERT(max_mcs <= RTWN_RIDX_COUNT, ("increase ridx limit\n"));
memset(power, 0, max_mcs * sizeof(power[0]));
if (rs->regulatory == 0) {
for (ridx = RTWN_RIDX_CCK1; ridx <= RTWN_RIDX_CCK11; ridx++)
power[ridx] = base[chain].pwr[0][ridx];
}
for (ridx = RTWN_RIDX_OFDM6; ridx < RTWN_RIDX_COUNT; ridx++) {
if (rs->regulatory == 3) {
power[ridx] = base[chain].pwr[0][ridx];
/* Apply vendor limits. */
if (IEEE80211_IS_CHAN_HT40(c))
max = rt->ht40_max_pwr[chain][group];
else
max = rt->ht20_max_pwr[chain][group];
if (power[ridx] > max)
power[ridx] = max;
} else if (rs->regulatory == 1) {
if (!IEEE80211_IS_CHAN_HT40(c))
power[ridx] = base[chain].pwr[group][ridx];
} else if (rs->regulatory != 2)
power[ridx] = base[chain].pwr[0][ridx];
}
/* Compute per-CCK rate Tx power. */
for (ridx = RTWN_RIDX_CCK1; ridx <= RTWN_RIDX_CCK11; ridx++)
power[ridx] += rt->cck_tx_pwr[chain][group];
htpow = rt->ht40_1s_tx_pwr[chain][group];
if (sc->ntxchains > 1) {
/* Apply reduction for 2 spatial streams. */
diff = rt->ht40_2s_tx_pwr_diff[chain][group];
htpow = (htpow > diff) ? htpow - diff : 0;
}
/* Compute per-OFDM rate Tx power. */
diff = rt->ofdm_tx_pwr_diff[chain][group];
ofdmpow = htpow + diff; /* HT->OFDM correction. */
for (ridx = RTWN_RIDX_OFDM6; ridx <= RTWN_RIDX_OFDM54; ridx++)
power[ridx] += ofdmpow;
/* Compute per-MCS Tx power. */
if (!IEEE80211_IS_CHAN_HT40(c)) {
diff = rt->ht20_tx_pwr_diff[chain][group];
htpow += diff; /* HT40->HT20 correction. */
}
for (ridx = RTWN_RIDX_MCS(0); ridx <= max_mcs; ridx++)
power[ridx] += htpow;
/* Apply max limit. */
for (ridx = RTWN_RIDX_CCK1; ridx <= max_mcs; ridx++) {
if (power[ridx] > R92C_MAX_TX_PWR)
power[ridx] = R92C_MAX_TX_PWR;
}
}
/*
* Fill in 802.11 available channel set, mark
* all available channels as active, and pick
* a default channel if not already specified.
*/
static void
ieee80211_chan_init(struct ieee80211com *ic)
{
#define DEFAULTRATES(m, def) do { \
if (ic->ic_sup_rates[m].rs_nrates == 0) \
ic->ic_sup_rates[m] = def; \
} while (0)
struct ieee80211_channel *c;
int i;
KASSERT(0 < ic->ic_nchans && ic->ic_nchans <= IEEE80211_CHAN_MAX,
("invalid number of channels specified: %u", ic->ic_nchans));
memset(ic->ic_chan_avail, 0, sizeof(ic->ic_chan_avail));
memset(ic->ic_modecaps, 0, sizeof(ic->ic_modecaps));
setbit(ic->ic_modecaps, IEEE80211_MODE_AUTO);
for (i = 0; i < ic->ic_nchans; i++) {
c = &ic->ic_channels[i];
KASSERT(c->ic_flags != 0, ("channel with no flags"));
/*
* Help drivers that work only with frequencies by filling
* in IEEE channel #'s if not already calculated. Note this
* mimics similar work done in ieee80211_setregdomain when
* changing regulatory state.
*/
if (c->ic_ieee == 0)
c->ic_ieee = ieee80211_mhz2ieee(c->ic_freq,c->ic_flags);
if (IEEE80211_IS_CHAN_HT40(c) && c->ic_extieee == 0)
c->ic_extieee = ieee80211_mhz2ieee(c->ic_freq +
(IEEE80211_IS_CHAN_HT40U(c) ? 20 : -20),
c->ic_flags);
/* default max tx power to max regulatory */
if (c->ic_maxpower == 0)
c->ic_maxpower = 2*c->ic_maxregpower;
setbit(ic->ic_chan_avail, c->ic_ieee);
/*
* Identify mode capabilities.
*/
if (IEEE80211_IS_CHAN_A(c))
setbit(ic->ic_modecaps, IEEE80211_MODE_11A);
if (IEEE80211_IS_CHAN_B(c))
setbit(ic->ic_modecaps, IEEE80211_MODE_11B);
if (IEEE80211_IS_CHAN_ANYG(c))
setbit(ic->ic_modecaps, IEEE80211_MODE_11G);
if (IEEE80211_IS_CHAN_FHSS(c))
setbit(ic->ic_modecaps, IEEE80211_MODE_FH);
if (IEEE80211_IS_CHAN_108A(c))
setbit(ic->ic_modecaps, IEEE80211_MODE_TURBO_A);
if (IEEE80211_IS_CHAN_108G(c))
setbit(ic->ic_modecaps, IEEE80211_MODE_TURBO_G);
if (IEEE80211_IS_CHAN_ST(c))
setbit(ic->ic_modecaps, IEEE80211_MODE_STURBO_A);
if (IEEE80211_IS_CHAN_HALF(c))
setbit(ic->ic_modecaps, IEEE80211_MODE_HALF);
if (IEEE80211_IS_CHAN_QUARTER(c))
setbit(ic->ic_modecaps, IEEE80211_MODE_QUARTER);
if (IEEE80211_IS_CHAN_HTA(c))
setbit(ic->ic_modecaps, IEEE80211_MODE_11NA);
if (IEEE80211_IS_CHAN_HTG(c))
setbit(ic->ic_modecaps, IEEE80211_MODE_11NG);
}
/* initialize candidate channels to all available */
memcpy(ic->ic_chan_active, ic->ic_chan_avail,
sizeof(ic->ic_chan_avail));
/* sort channel table to allow lookup optimizations */
ieee80211_sort_channels(ic->ic_channels, ic->ic_nchans);
/* invalidate any previous state */
ic->ic_bsschan = IEEE80211_CHAN_ANYC;
ic->ic_prevchan = NULL;
ic->ic_csa_newchan = NULL;
/* arbitrarily pick the first channel */
ic->ic_curchan = &ic->ic_channels[0];
ic->ic_rt = ieee80211_get_ratetable(ic->ic_curchan);
/* fillin well-known rate sets if driver has not specified */
DEFAULTRATES(IEEE80211_MODE_11B, ieee80211_rateset_11b);
DEFAULTRATES(IEEE80211_MODE_11G, ieee80211_rateset_11g);
DEFAULTRATES(IEEE80211_MODE_11A, ieee80211_rateset_11a);
DEFAULTRATES(IEEE80211_MODE_TURBO_A, ieee80211_rateset_11a);
DEFAULTRATES(IEEE80211_MODE_TURBO_G, ieee80211_rateset_11g);
DEFAULTRATES(IEEE80211_MODE_STURBO_A, ieee80211_rateset_11a);
DEFAULTRATES(IEEE80211_MODE_HALF, ieee80211_rateset_half);
DEFAULTRATES(IEEE80211_MODE_QUARTER, ieee80211_rateset_quarter);
DEFAULTRATES(IEEE80211_MODE_11NA, ieee80211_rateset_11a);
DEFAULTRATES(IEEE80211_MODE_11NG, ieee80211_rateset_11g);
/*
* Set auto mode to reset active channel state and any desired channel.
*/
(void) ieee80211_setmode(ic, IEEE80211_MODE_AUTO);
#undef DEFAULTRATES
}
/*
* rt2872_rf_set_chan
*/
static void
rt2872_rf_set_chan(struct rt2860_softc *sc,
struct ieee80211_channel *c)
{
struct ifnet *ifp;
struct ieee80211com *ic;
const struct rt2860_rf_prog *prog;
uint32_t r1, r2, r3, r4;
uint32_t r6, r7, r12, r13, r23, r24;
int8_t txpow1, txpow2;
int i, chan;
ifp = sc->ifp;
ic = ifp->if_l2com;
prog = rt2860_rf_2850;
/* get central channel position */
chan = ieee80211_chan2ieee(ic, c);
if (IEEE80211_IS_CHAN_HT40U(c))
chan += 2;
else if (IEEE80211_IS_CHAN_HT40D(c))
chan -= 2;
RT2860_DPRINTF(sc, RT2860_DEBUG_CHAN,
"%s: RF set channel: channel=%u, HT%s%s\n",
device_get_nameunit(sc->dev),
ieee80211_chan2ieee(ic, c),
!IEEE80211_IS_CHAN_HT(c) ? " disabled" :
IEEE80211_IS_CHAN_HT20(c) ? "20":
IEEE80211_IS_CHAN_HT40U(c) ? "40U" : "40D",
(ic->ic_flags & IEEE80211_F_SCAN) ? ", scanning" : "");
if (chan == 0 || chan == IEEE80211_CHAN_ANY)
return;
for (i = 0; prog[i].chan != chan; i++);
r1 = prog[i].r1;
r2 = prog[i].r2;
r3 = prog[i].r3;
r4 = prog[i].r4;
txpow1 = sc->txpow1[i];
txpow2 = sc->txpow2[i];
for (i = 0; rt2860_rf_fi3020[i].channel != chan; i++);
/* Programm channel parameters */
r2 = rt2860_rf_fi3020[i].n;
rt2860_io_rf_write(sc, 2 , r2 );
r3 = rt2860_rf_fi3020[i].k;
rt2860_io_rf_write(sc, 3 , r3 );
r6 = (rt3052_rf_default[6] & 0xFC) | (rt2860_rf_fi3020[i].r & 0x03);
rt2860_io_rf_write(sc, 6 , r6 );
/* Set Tx Power */
r12 = (rt3052_rf_default[12] & 0xE0) | (txpow1 & 0x1f);
rt2860_io_rf_write(sc, 12, r12);
/* Set Tx1 Power */
r13 = (rt3052_rf_default[13] & 0xE0) | (txpow2 & 0x1f);
rt2860_io_rf_write(sc, 13, r13);
/* Set RF offset */
r23 = (rt3052_rf_default[23] & 0x80) | (sc->rf_freq_off);
rt2860_io_rf_write(sc, 23, r23);
/* Set BW */
r24 = (rt3052_rf_default[24] & 0xDF);
if (!(ic->ic_flags & IEEE80211_F_SCAN) && IEEE80211_IS_CHAN_HT40(c))
r24 |= 0x20;
rt2860_io_rf_write(sc, 24, r24);
/* Enable RF tuning */
r7 = (rt3052_rf_default[7]) | 1;
rt2860_io_rf_write(sc, 7 , r7 );
/* Antenna */
r1 = (rt3052_rf_default[1] & 0xab) | ((sc->nrxpath == 1)?0x10:0) |
((sc->ntxpath == 1)?0x20:0);
rt2860_io_rf_write(sc, 1 , r1 );
DELAY(200);
rt2860_rf_select_chan_group(sc, c);
DELAY(1000);
}
static void
ar9280WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan)
{
u_int modesIndex, freqIndex;
int regWrites = 0;
int i;
const HAL_INI_ARRAY *ia;
/* Setup the indices for the next set of register array writes */
/* XXX Ignore 11n dynamic mode on the AR5416 for the moment */
if (IEEE80211_IS_CHAN_2GHZ(chan)) {
freqIndex = 2;
if (IEEE80211_IS_CHAN_HT40(chan))
modesIndex = 3;
else if (IEEE80211_IS_CHAN_108G(chan))
modesIndex = 5;
else
modesIndex = 4;
} else {
freqIndex = 1;
if (IEEE80211_IS_CHAN_HT40(chan) ||
IEEE80211_IS_CHAN_TURBO(chan))
modesIndex = 2;
else
modesIndex = 1;
}
/* Set correct Baseband to analog shift setting to access analog chips. */
OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
/*
* This is unwound because at the moment, there's a requirement
* for Merlin (and later, perhaps) to have a specific bit fixed
* in the AR_AN_TOP2 register before writing it.
*/
ia = &AH5212(ah)->ah_ini_modes;
#if 0
regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes,
modesIndex, regWrites);
#endif
HALASSERT(modesIndex < ia->cols);
for (i = 0; i < ia->rows; i++) {
uint32_t reg = HAL_INI_VAL(ia, i, 0);
uint32_t val = HAL_INI_VAL(ia, i, modesIndex);
if (reg == AR_AN_TOP2 && AH5416(ah)->ah_need_an_top2_fixup)
val &= ~AR_AN_TOP2_PWDCLKIND;
OS_REG_WRITE(ah, reg, val);
/* Analog shift register delay seems needed for Merlin - PR kern/154220 */
if (reg >= 0x7800 && reg < 0x7900)
OS_DELAY(100);
DMA_YIELD(regWrites);
}
if (AR_SREV_MERLIN_20_OR_LATER(ah)) {
regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_rxgain,
modesIndex, regWrites);
regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_txgain,
modesIndex, regWrites);
}
/* XXX Merlin 100us delay for shift registers */
regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common,
1, regWrites);
if (AR_SREV_MERLIN_20(ah) && IS_5GHZ_FAST_CLOCK_EN(ah, chan)) {
/* 5GHz channels w/ Fast Clock use different modal values */
regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_xmodes,
modesIndex, regWrites);
}
}
void
ar9280SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan)
{
static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 };
static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 };
static int inc[4] = { 0, 100, 0, 0 };
int bb_spur = AR_NO_SPUR;
int freq;
int bin, cur_bin;
int bb_spur_off, spur_subchannel_sd;
int spur_freq_sd;
int spur_delta_phase;
int denominator;
int upper, lower, cur_vit_mask;
int tmp, newVal;
int i;
CHAN_CENTERS centers;
int8_t mask_m[123];
int8_t mask_p[123];
int8_t mask_amt;
int tmp_mask;
int cur_bb_spur;
HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan);
OS_MEMZERO(&mask_m, sizeof(int8_t) * 123);
OS_MEMZERO(&mask_p, sizeof(int8_t) * 123);
ar5416GetChannelCenters(ah, chan, ¢ers);
freq = centers.synth_center;
/*
* Need to verify range +/- 9.38 for static ht20 and +/- 18.75 for ht40,
* otherwise spur is out-of-band and can be ignored.
*/
for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz);
/* Get actual spur freq in MHz from EEPROM read value */
if (is2GHz) {
cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
} else {
cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
}
if (AR_NO_SPUR == cur_bb_spur)
break;
cur_bb_spur = cur_bb_spur - freq;
if (IEEE80211_IS_CHAN_HT40(chan)) {
if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
(cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
bb_spur = cur_bb_spur;
break;
}
} else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
(cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
bb_spur = cur_bb_spur;
break;
}
}
if (AR_NO_SPUR == bb_spur) {
#if 1
/*
* MRC CCK can interfere with beacon detection and cause deaf/mute.
* Disable MRC CCK for now.
*/
OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
#else
/* Enable MRC CCK if no spur is found in this channel. */
OS_REG_SET_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
#endif
return;
} else {
/*
* For Merlin, spur can break CCK MRC algorithm. Disable CCK MRC if spur
* is found in this channel.
*/
OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
}
bin = bb_spur * 320;
tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0));
newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), newVal);
newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
AR_PHY_SPUR_REG_MASK_RATE_SELECT |
AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
OS_REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
/* Pick control or extn channel to cancel the spur */
if (IEEE80211_IS_CHAN_HT40(chan)) {
if (bb_spur < 0) {
spur_subchannel_sd = 1;
bb_spur_off = bb_spur + 10;
} else {
spur_subchannel_sd = 0;
bb_spur_off = bb_spur - 10;
}
} else {
spur_subchannel_sd = 0;
bb_spur_off = bb_spur;
}
/*
* spur_delta_phase = bb_spur/40 * 2**21 for static ht20,
* /80 for dyn2040.
*/
if (IEEE80211_IS_CHAN_HT40(chan))
spur_delta_phase = ((bb_spur * 262144) / 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
else
spur_delta_phase = ((bb_spur * 524288) / 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
/*
* in 11A mode the denominator of spur_freq_sd should be 40 and
* it should be 44 in 11G
*/
denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 44 : 40;
spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
OS_REG_WRITE(ah, AR_PHY_TIMING11, newVal);
/* Choose to cancel between control and extension channels */
newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
OS_REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
/*
* ============================================
* Set Pilot and Channel Masks
*
* pilot mask 1 [31:0] = +6..-26, no 0 bin
* pilot mask 2 [19:0] = +26..+7
*
* channel mask 1 [31:0] = +6..-26, no 0 bin
* channel mask 2 [19:0] = +26..+7
*/
cur_bin = -6000;
upper = bin + 100;
lower = bin - 100;
for (i = 0; i < 4; i++) {
int pilot_mask = 0;
int chan_mask = 0;
int bp = 0;
for (bp = 0; bp < 30; bp++) {
if ((cur_bin > lower) && (cur_bin < upper)) {
pilot_mask = pilot_mask | 0x1 << bp;
chan_mask = chan_mask | 0x1 << bp;
}
cur_bin += 100;
}
cur_bin += inc[i];
OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask);
}
/* =================================================
* viterbi mask 1 based on channel magnitude
* four levels 0-3
* - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c)
* [1 2 2 1] for -9.6 or [1 2 1] for +16
* - enable_mask_ppm, all bins move with freq
*
* - mask_select, 8 bits for rates (reg 67,0x990c)
* - mask_rate_cntl, 8 bits for rates (reg 67,0x990c)
* choose which mask to use mask or mask2
*/
/*
* viterbi mask 2 2nd set for per data rate puncturing
* four levels 0-3
* - mask_select, 8 bits for rates (reg 67)
* - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994)
* [1 2 2 1] for -9.6 or [1 2 1] for +16
*/
cur_vit_mask = 6100;
upper = bin + 120;
lower = bin - 120;
for (i = 0; i < 123; i++) {
if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
if ((abs(cur_vit_mask - bin)) < 75) {
mask_amt = 1;
} else {
mask_amt = 0;
}
if (cur_vit_mask < 0) {
mask_m[abs(cur_vit_mask / 100)] = mask_amt;
} else {
mask_p[cur_vit_mask / 100] = mask_amt;
}
}
cur_vit_mask -= 100;
}
tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
| (mask_m[48] << 26) | (mask_m[49] << 24)
| (mask_m[50] << 22) | (mask_m[51] << 20)
| (mask_m[52] << 18) | (mask_m[53] << 16)
| (mask_m[54] << 14) | (mask_m[55] << 12)
| (mask_m[56] << 10) | (mask_m[57] << 8)
| (mask_m[58] << 6) | (mask_m[59] << 4)
| (mask_m[60] << 2) | (mask_m[61] << 0);
OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
tmp_mask = (mask_m[31] << 28)
| (mask_m[32] << 26) | (mask_m[33] << 24)
| (mask_m[34] << 22) | (mask_m[35] << 20)
| (mask_m[36] << 18) | (mask_m[37] << 16)
| (mask_m[48] << 14) | (mask_m[39] << 12)
| (mask_m[40] << 10) | (mask_m[41] << 8)
| (mask_m[42] << 6) | (mask_m[43] << 4)
| (mask_m[44] << 2) | (mask_m[45] << 0);
OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
| (mask_m[18] << 26) | (mask_m[18] << 24)
| (mask_m[20] << 22) | (mask_m[20] << 20)
| (mask_m[22] << 18) | (mask_m[22] << 16)
| (mask_m[24] << 14) | (mask_m[24] << 12)
| (mask_m[25] << 10) | (mask_m[26] << 8)
| (mask_m[27] << 6) | (mask_m[28] << 4)
| (mask_m[29] << 2) | (mask_m[30] << 0);
OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28)
| (mask_m[ 2] << 26) | (mask_m[ 3] << 24)
| (mask_m[ 4] << 22) | (mask_m[ 5] << 20)
| (mask_m[ 6] << 18) | (mask_m[ 7] << 16)
| (mask_m[ 8] << 14) | (mask_m[ 9] << 12)
| (mask_m[10] << 10) | (mask_m[11] << 8)
| (mask_m[12] << 6) | (mask_m[13] << 4)
| (mask_m[14] << 2) | (mask_m[15] << 0);
OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
tmp_mask = (mask_p[15] << 28)
| (mask_p[14] << 26) | (mask_p[13] << 24)
| (mask_p[12] << 22) | (mask_p[11] << 20)
| (mask_p[10] << 18) | (mask_p[ 9] << 16)
| (mask_p[ 8] << 14) | (mask_p[ 7] << 12)
| (mask_p[ 6] << 10) | (mask_p[ 5] << 8)
| (mask_p[ 4] << 6) | (mask_p[ 3] << 4)
| (mask_p[ 2] << 2) | (mask_p[ 1] << 0);
OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
tmp_mask = (mask_p[30] << 28)
| (mask_p[29] << 26) | (mask_p[28] << 24)
| (mask_p[27] << 22) | (mask_p[26] << 20)
| (mask_p[25] << 18) | (mask_p[24] << 16)
| (mask_p[23] << 14) | (mask_p[22] << 12)
| (mask_p[21] << 10) | (mask_p[20] << 8)
| (mask_p[19] << 6) | (mask_p[18] << 4)
| (mask_p[17] << 2) | (mask_p[16] << 0);
OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
tmp_mask = (mask_p[45] << 28)
| (mask_p[44] << 26) | (mask_p[43] << 24)
| (mask_p[42] << 22) | (mask_p[41] << 20)
| (mask_p[40] << 18) | (mask_p[39] << 16)
| (mask_p[38] << 14) | (mask_p[37] << 12)
| (mask_p[36] << 10) | (mask_p[35] << 8)
| (mask_p[34] << 6) | (mask_p[33] << 4)
| (mask_p[32] << 2) | (mask_p[31] << 0);
OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
| (mask_p[59] << 26) | (mask_p[58] << 24)
| (mask_p[57] << 22) | (mask_p[56] << 20)
| (mask_p[55] << 18) | (mask_p[54] << 16)
| (mask_p[53] << 14) | (mask_p[52] << 12)
| (mask_p[51] << 10) | (mask_p[50] << 8)
| (mask_p[49] << 6) | (mask_p[48] << 4)
| (mask_p[47] << 2) | (mask_p[46] << 0);
OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
}
static void
ar9287AniSetup(struct ath_hal *ah)
{
/*
* These are the parameters from the AR5416 ANI code;
* they likely need quite a bit of adjustment for the
* AR9280.
*/
static const struct ar5212AniParams aniparams = {
.maxNoiseImmunityLevel = 4, /* levels 0..4 */
.totalSizeDesired = { -55, -55, -55, -55, -62 },
.coarseHigh = { -14, -14, -14, -14, -12 },
.coarseLow = { -64, -64, -64, -64, -70 },
.firpwr = { -78, -78, -78, -78, -80 },
.maxSpurImmunityLevel = 2,
.cycPwrThr1 = { 2, 4, 6 },
.maxFirstepLevel = 2, /* levels 0..2 */
.firstep = { 0, 4, 8 },
.ofdmTrigHigh = 500,
.ofdmTrigLow = 200,
.cckTrigHigh = 200,
.cckTrigLow = 100,
.rssiThrHigh = 40,
.rssiThrLow = 7,
.period = 100,
};
/* NB: disable ANI noise immmunity for reliable RIFS rx */
AH5416(ah)->ah_ani_function &= ~ HAL_ANI_NOISE_IMMUNITY_LEVEL;
/* NB: ANI is not enabled yet */
ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE);
}
/*
* Attach for an AR9287 part.
*/
static struct ath_hal *
ar9287Attach(uint16_t devid, HAL_SOFTC sc,
HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata,
HAL_STATUS *status)
{
struct ath_hal_9287 *ahp9287;
struct ath_hal_5212 *ahp;
struct ath_hal *ah;
uint32_t val;
HAL_STATUS ecode;
HAL_BOOL rfStatus;
int8_t pwr_table_offset;
HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
__func__, sc, (void*) st, (void*) sh);
/* NB: memory is returned zero'd */
ahp9287 = ath_hal_malloc(sizeof (struct ath_hal_9287));
if (ahp9287 == AH_NULL) {
HALDEBUG(AH_NULL, HAL_DEBUG_ANY,
"%s: cannot allocate memory for state block\n", __func__);
*status = HAL_ENOMEM;
return AH_NULL;
}
ahp = AH5212(ahp9287);
ah = &ahp->ah_priv.h;
ar5416InitState(AH5416(ah), devid, sc, st, sh, status);
/* XXX override with 9280 specific state */
/* override 5416 methods for our needs */
AH5416(ah)->ah_initPLL = ar9280InitPLL;
ah->ah_setAntennaSwitch = ar9287SetAntennaSwitch;
ah->ah_configPCIE = ar9287ConfigPCIE;
AH5416(ah)->ah_cal.iqCalData.calData = &ar9287_iq_cal;
AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9287_adc_gain_cal;
AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9287_adc_dc_cal;
AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9287_adc_init_dc_cal;
/* Better performance without ADC Gain Calibration */
AH5416(ah)->ah_cal.suppCals = ADC_DC_CAL | IQ_MISMATCH_CAL;
AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate;
AH5416(ah)->ah_writeIni = ar9287WriteIni;
ah->ah_setTxPower = ar9287SetTransmitPower;
ah->ah_setBoardValues = ar9287SetBoardValues;
AH5416(ah)->ah_olcInit = ar9287olcInit;
AH5416(ah)->ah_olcTempCompensation = ar9287olcTemperatureCompensation;
//AH5416(ah)->ah_setPowerCalTable = ar9287SetPowerCalTable;
AH5416(ah)->ah_cal_initcal = ar9287InitCalHardware;
AH5416(ah)->ah_cal_pacal = ar9287PACal;
/* XXX NF calibration */
/* XXX Ini override? (IFS vars - since the kiwi mac clock is faster?) */
/* XXX what else is kiwi-specific in the radio/calibration pathway? */
AH5416(ah)->ah_rx_chainmask = AR9287_DEFAULT_RXCHAINMASK;
AH5416(ah)->ah_tx_chainmask = AR9287_DEFAULT_TXCHAINMASK;
if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) {
/* reset chip */
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n",
__func__);
ecode = HAL_EIO;
goto bad;
}
if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n",
__func__);
ecode = HAL_EIO;
goto bad;
}
/* Read Revisions from Chips before taking out of reset */
val = OS_REG_READ(ah, AR_SREV);
HALDEBUG(ah, HAL_DEBUG_ATTACH,
"%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n",
__func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION),
MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION));
/* NB: include chip type to differentiate from pre-Sowl versions */
AH_PRIVATE(ah)->ah_macVersion =
(val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S;
AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION);
AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0;
/* Don't support Kiwi < 1.2; those are pre-release chips */
if (! AR_SREV_KIWI_12_OR_LATER(ah)) {
ath_hal_printf(ah, "[ath]: Kiwi < 1.2 is not supported\n");
ecode = HAL_EIO;
goto bad;
}
/* setup common ini data; rf backends handle remainder */
HAL_INI_INIT(&ahp->ah_ini_modes, ar9287Modes_9287_1_1, 6);
HAL_INI_INIT(&ahp->ah_ini_common, ar9287Common_9287_1_1, 2);
/* If pcie_clock_req */
HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
ar9287PciePhy_clkreq_always_on_L1_9287_1_1, 2);
/* XXX WoW ini values */
/* Else */
#if 0
HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
ar9287PciePhy_clkreq_off_L1_9287_1_1, 2);
#endif
/* Initialise Japan arrays */
HAL_INI_INIT(&ahp9287->ah_ini_cckFirNormal,
ar9287Common_normal_cck_fir_coeff_9287_1_1, 2);
HAL_INI_INIT(&ahp9287->ah_ini_cckFirJapan2484,
ar9287Common_japan_2484_cck_fir_coeff_9287_1_1, 2);
ar5416AttachPCIE(ah);
ecode = ath_hal_9287EepromAttach(ah);
if (ecode != HAL_OK)
goto bad;
if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);
ecode = HAL_EIO;
goto bad;
}
AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
if (!ar5212ChipTest(ah)) {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",
__func__);
ecode = HAL_ESELFTEST;
goto bad;
}
/*
* Set correct Baseband to analog shift
* setting to access analog chips.
*/
OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
/* Read Radio Chip Rev Extract */
AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah);
switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
case AR_RAD2133_SREV_MAJOR: /* Sowl: 2G/3x3 */
case AR_RAD5133_SREV_MAJOR: /* Sowl: 2+5G/3x3 */
break;
default:
if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {
AH_PRIVATE(ah)->ah_analog5GhzRev =
AR_RAD5133_SREV_MAJOR;
break;
}
#ifdef AH_DEBUG
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: 5G Radio Chip Rev 0x%02X is not supported by "
"this driver\n", __func__,
AH_PRIVATE(ah)->ah_analog5GhzRev);
ecode = HAL_ENOTSUPP;
goto bad;
#endif
}
rfStatus = ar9287RfAttach(ah, &ecode);
if (!rfStatus) {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",
__func__, ecode);
goto bad;
}
/*
* We only implement open-loop TX power control
* for the AR9287 in this codebase.
*/
if (! ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) {
ath_hal_printf(ah, "[ath] AR9287 w/ closed-loop TX power control"
" isn't supported.\n");
ecode = HAL_ENOTSUPP;
goto bad;
}
/*
* Check whether the power table offset isn't the default.
* This can occur with eeprom minor V21 or greater on Merlin.
*/
(void) ath_hal_eepromGet(ah, AR_EEP_PWR_TABLE_OFFSET, &pwr_table_offset);
if (pwr_table_offset != AR5416_PWR_TABLE_OFFSET_DB)
ath_hal_printf(ah, "[ath]: default pwr offset: %d dBm != EEPROM pwr offset: %d dBm; curves will be adjusted.\n",
AR5416_PWR_TABLE_OFFSET_DB, (int) pwr_table_offset);
/* setup rxgain table */
HAL_INI_INIT(&ahp9287->ah_ini_rxgain, ar9287Modes_rx_gain_9287_1_1, 6);
/* setup txgain table */
HAL_INI_INIT(&ahp9287->ah_ini_txgain, ar9287Modes_tx_gain_9287_1_1, 6);
/*
* Got everything we need now to setup the capabilities.
*/
if (!ar9287FillCapabilityInfo(ah)) {
ecode = HAL_EEREAD;
goto bad;
}
ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);
if (ecode != HAL_OK) {
HALDEBUG(ah, HAL_DEBUG_ANY,
"%s: error getting mac address from EEPROM\n", __func__);
goto bad;
}
/* XXX How about the serial number ? */
/* Read Reg Domain */
AH_PRIVATE(ah)->ah_currentRD =
ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL);
AH_PRIVATE(ah)->ah_currentRDext = AR9287_RDEXT_DEFAULT;
/*
* ah_miscMode is populated by ar5416FillCapabilityInfo()
* starting from griffin. Set here to make sure that
* AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is
* placed into hardware.
*/
if (ahp->ah_miscMode != 0)
OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode);
ar9287AniSetup(ah); /* Anti Noise Immunity */
/* Setup noise floor min/max/nominal values */
AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9287_2GHZ;
AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9287_2GHZ;
AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9287_2GHZ;
AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9287_5GHZ;
AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9287_5GHZ;
AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9287_5GHZ;
ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist);
HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
return ah;
bad:
if (ah != AH_NULL)
ah->ah_detach(ah);
if (status)
*status = ecode;
return AH_NULL;
}
static void
ar9287ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore)
{
if (AH_PRIVATE(ah)->ah_ispcie && !restore) {
ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0);
OS_DELAY(1000);
OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
OS_REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT); /* Yes, Kiwi uses the Kite PCIe PHY WA */
}
}
static void
ar9287WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan)
{
u_int modesIndex, freqIndex;
int regWrites = 0;
/* Setup the indices for the next set of register array writes */
/* XXX Ignore 11n dynamic mode on the AR5416 for the moment */
if (IEEE80211_IS_CHAN_2GHZ(chan)) {
freqIndex = 2;
if (IEEE80211_IS_CHAN_HT40(chan))
modesIndex = 3;
else if (IEEE80211_IS_CHAN_108G(chan))
modesIndex = 5;
else
modesIndex = 4;
} else {
freqIndex = 1;
if (IEEE80211_IS_CHAN_HT40(chan) ||
IEEE80211_IS_CHAN_TURBO(chan))
modesIndex = 2;
else
modesIndex = 1;
}
/* Set correct Baseband to analog shift setting to access analog chips. */
OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, modesIndex, regWrites);
regWrites = ath_hal_ini_write(ah, &AH9287(ah)->ah_ini_rxgain, modesIndex, regWrites);
regWrites = ath_hal_ini_write(ah, &AH9287(ah)->ah_ini_txgain, modesIndex, regWrites);
regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 1, regWrites);
}
static HAL_BOOL
ar5416LoadNF(struct ath_hal *ah, const struct ieee80211_channel *chan)
{
static const uint32_t ar5416_cca_regs[] = {
AR_PHY_CCA,
AR_PHY_CH1_CCA,
AR_PHY_CH2_CCA,
AR_PHY_EXT_CCA,
AR_PHY_CH1_EXT_CCA,
AR_PHY_CH2_EXT_CCA
};
struct ar5212NfCalHist *h;
int i;
int32_t val;
uint8_t chainmask;
int16_t default_nf = ar5416GetDefaultNF(ah, chan);
/*
* Force NF calibration for all chains.
*/
if (AR_SREV_KITE(ah)) {
/* Kite has only one chain */
chainmask = 0x9;
} else if (AR_SREV_MERLIN(ah) || AR_SREV_KIWI(ah)) {
/* Merlin/Kiwi has only two chains */
chainmask = 0x1B;
} else {
chainmask = 0x3F;
}
/*
* Write filtered NF values into maxCCApwr register parameter
* so we can load below.
*/
h = AH5416(ah)->ah_cal.nfCalHist;
HALDEBUG(ah, HAL_DEBUG_NFCAL, "CCA: ");
for (i = 0; i < AR5416_NUM_NF_READINGS; i ++) {
/* Don't write to EXT radio CCA registers unless in HT/40 mode */
/* XXX this check should really be cleaner! */
if (i > 2 && !IEEE80211_IS_CHAN_HT40(chan))
continue;
if (chainmask & (1 << i)) {
int16_t nf_val;
if (h)
nf_val = h[i].privNF;
else
nf_val = default_nf;
val = OS_REG_READ(ah, ar5416_cca_regs[i]);
val &= 0xFFFFFE00;
val |= (((uint32_t) nf_val << 1) & 0x1ff);
HALDEBUG(ah, HAL_DEBUG_NFCAL, "[%d: %d]", i, nf_val);
OS_REG_WRITE(ah, ar5416_cca_regs[i], val);
}
}
HALDEBUG(ah, HAL_DEBUG_NFCAL, "\n");
/* Load software filtered NF value into baseband internal minCCApwr variable. */
OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF);
OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
/* Wait for load to complete, should be fast, a few 10s of us. */
if (! ar5212WaitNFCalComplete(ah, 1000)) {
/*
* We timed out waiting for the noisefloor to load, probably due to an
* in-progress rx. Simply return here and allow the load plenty of time
* to complete before the next calibration interval. We need to avoid
* trying to load -50 (which happens below) while the previous load is
* still in progress as this can cause rx deafness. Instead by returning
* here, the baseband nf cal will just be capped by our present
* noisefloor until the next calibration timer.
*/
HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "Timeout while waiting for "
"nf to load: AR_PHY_AGC_CONTROL=0x%x\n",
OS_REG_READ(ah, AR_PHY_AGC_CONTROL));
return AH_FALSE;
}
/*
* Restore maxCCAPower register parameter again so that we're not capped
* by the median we just loaded. This will be initial (and max) value
* of next noise floor calibration the baseband does.
*/
for (i = 0; i < AR5416_NUM_NF_READINGS; i ++) {
/* Don't write to EXT radio CCA registers unless in HT/40 mode */
/* XXX this check should really be cleaner! */
if (i > 2 && !IEEE80211_IS_CHAN_HT40(chan))
continue;
if (chainmask & (1 << i)) {
val = OS_REG_READ(ah, ar5416_cca_regs[i]);
val &= 0xFFFFFE00;
val |= (((uint32_t)(-50) << 1) & 0x1ff);
OS_REG_WRITE(ah, ar5416_cca_regs[i], val);
}
}
return AH_TRUE;
}
/*
* rt2860_rf_select_chan_group
*/
void rt2860_rf_select_chan_group(struct rt2860_softc *sc,
struct ieee80211_channel *c)
{
struct ifnet *ifp;
struct ieee80211com *ic;
int chan, group;
uint32_t tmp;
ifp = sc->ifp;
ic = ifp->if_l2com;
chan = ieee80211_chan2ieee(ic, c);
if (chan == 0 || chan == IEEE80211_CHAN_ANY)
return;
if (chan <= 14)
group = 0;
else if (chan <= 64)
group = 1;
else if (chan <= 128)
group = 2;
else
group = 3;
rt2860_io_bbp_write(sc, 62, 0x37 - sc->lna_gain[group]);
rt2860_io_bbp_write(sc, 63, 0x37 - sc->lna_gain[group]);
rt2860_io_bbp_write(sc, 64, 0x37 - sc->lna_gain[group]);
rt2860_io_bbp_write(sc, 86, 0x00);
if (group == 0)
{
if (sc->ext_lna_2ghz)
{
rt2860_io_bbp_write(sc, 82, 0x62);
rt2860_io_bbp_write(sc, 75, 0x46);
}
else
{
rt2860_io_bbp_write(sc, 82, 0x84);
rt2860_io_bbp_write(sc, 75, 0x50);
}
}
else
{
rt2860_io_bbp_write(sc, 82, 0xf2);
if (sc->ext_lna_5ghz)
rt2860_io_bbp_write(sc, 75, 0x46);
else
rt2860_io_bbp_write(sc, 75, 0x50);
}
if (group == 0)
{
tmp = 0x2e + sc->lna_gain[group];
}
else
{
if ((ic->ic_flags & IEEE80211_F_SCAN) || !IEEE80211_IS_CHAN_HT40(c))
tmp = 0x32 + sc->lna_gain[group] * 5 / 3;
else
tmp = 0x3a + sc->lna_gain[group] * 5 / 3;
}
rt2860_io_bbp_write(sc, 66, tmp);
tmp = RT2860_REG_RFTR_ENABLE |
RT2860_REG_TRSW_ENABLE |
RT2860_REG_LNA_PE_G1_ENABLE |
RT2860_REG_LNA_PE_A1_ENABLE |
RT2860_REG_LNA_PE_G0_ENABLE |
RT2860_REG_LNA_PE_A0_ENABLE;
if (group == 0)
tmp |= RT2860_REG_PA_PE_G1_ENABLE |
RT2860_REG_PA_PE_G0_ENABLE;
else
tmp |= RT2860_REG_PA_PE_A1_ENABLE |
RT2860_REG_PA_PE_A0_ENABLE;
if (sc->ntxpath == 1)
tmp &= ~(RT2860_REG_PA_PE_G1_ENABLE | RT2860_REG_PA_PE_A1_ENABLE);
if (sc->nrxpath == 1)
tmp &= ~(RT2860_REG_LNA_PE_G1_ENABLE | RT2860_REG_LNA_PE_A1_ENABLE);
rt2860_io_mac_write(sc, RT2860_REG_TX_PIN_CFG, tmp);
tmp = rt2860_io_mac_read(sc, RT2860_REG_TX_BAND_CFG);
tmp &= ~(RT2860_REG_TX_BAND_BG | RT2860_REG_TX_BAND_A | RT2860_REG_TX_BAND_HT40_ABOVE);
if (group == 0)
tmp |= RT2860_REG_TX_BAND_BG;
else
tmp |= RT2860_REG_TX_BAND_A;
/* set central channel position */
if (IEEE80211_IS_CHAN_HT40U(c))
tmp |= RT2860_REG_TX_BAND_HT40_BELOW;
else if (IEEE80211_IS_CHAN_HT40D(c))
tmp |= RT2860_REG_TX_BAND_HT40_ABOVE;
else
tmp |= RT2860_REG_TX_BAND_HT40_BELOW;
rt2860_io_mac_write(sc, RT2860_REG_TX_BAND_CFG, tmp);
/* set bandwidth (20MHz or 40MHz) */
tmp = rt2860_io_bbp_read(sc, 4);
tmp &= ~0x18;
if (IEEE80211_IS_CHAN_HT40(c))
tmp |= 0x10;
rt2860_io_bbp_write(sc, 4, tmp);
/* set central channel position */
tmp = rt2860_io_bbp_read(sc, 3);
tmp &= ~0x20;
if (IEEE80211_IS_CHAN_HT40D(c))
tmp |= 0x20;
rt2860_io_bbp_write(sc, 3, tmp);
if (sc->mac_rev == 0x28600100)
{
if (!IEEE80211_IS_CHAN_HT40(c))
{
rt2860_io_bbp_write(sc, 69, 0x16);
rt2860_io_bbp_write(sc, 70, 0x08);
rt2860_io_bbp_write(sc, 73, 0x12);
}
else
{
rt2860_io_bbp_write(sc, 69, 0x1a);
rt2860_io_bbp_write(sc, 70, 0x0a);
rt2860_io_bbp_write(sc, 73, 0x16);
}
}
}
static void
r12a_tx_raid(struct rtwn_softc *sc, struct r12a_tx_desc *txd,
struct ieee80211_node *ni, int ismcast)
{
struct ieee80211com *ic = &sc->sc_ic;
struct ieee80211vap *vap = ni->ni_vap;
struct ieee80211_channel *chan;
enum ieee80211_phymode mode;
uint8_t raid;
chan = (ni->ni_chan != IEEE80211_CHAN_ANYC) ?
ni->ni_chan : ic->ic_curchan;
mode = ieee80211_chan2mode(chan);
/* NB: group addressed frames are done at 11bg rates for now */
if (ismcast || !(ni->ni_flags & IEEE80211_NODE_HT)) {
switch (mode) {
case IEEE80211_MODE_11A:
case IEEE80211_MODE_11B:
case IEEE80211_MODE_11G:
break;
case IEEE80211_MODE_11NA:
mode = IEEE80211_MODE_11A;
break;
case IEEE80211_MODE_11NG:
mode = IEEE80211_MODE_11G;
break;
default:
device_printf(sc->sc_dev, "unknown mode(1) %d!\n",
ic->ic_curmode);
return;
}
}
switch (mode) {
case IEEE80211_MODE_11A:
raid = R12A_RAID_11G;
break;
case IEEE80211_MODE_11B:
raid = R12A_RAID_11B;
break;
case IEEE80211_MODE_11G:
if (vap->iv_flags & IEEE80211_F_PUREG)
raid = R12A_RAID_11G;
else
raid = R12A_RAID_11BG;
break;
case IEEE80211_MODE_11NA:
if (sc->ntxchains == 1)
raid = R12A_RAID_11GN_1;
else
raid = R12A_RAID_11GN_2;
break;
case IEEE80211_MODE_11NG:
if (sc->ntxchains == 1) {
if (IEEE80211_IS_CHAN_HT40(chan))
raid = R12A_RAID_11BGN_1_40;
else
raid = R12A_RAID_11BGN_1;
} else {
if (IEEE80211_IS_CHAN_HT40(chan))
raid = R12A_RAID_11BGN_2_40;
else
raid = R12A_RAID_11BGN_2;
}
break;
default:
/* TODO: 80 MHz / 11ac */
device_printf(sc->sc_dev, "unknown mode(2) %d!\n", mode);
return;
}
txd->txdw1 |= htole32(SM(R12A_TXDW1_RAID, raid));
}
/*
* rt2860_rf_set_chan
*/
void rt2860_rf_set_chan(struct rt2860_softc *sc,
struct ieee80211_channel *c)
{
struct ifnet *ifp;
struct ieee80211com *ic;
const struct rt2860_rf_prog *prog;
uint32_t r1, r2, r3, r4;
int8_t txpow1, txpow2;
int i, chan;
if (sc->mac_rev == 0x28720200) {
rt2872_rf_set_chan(sc, c);
return;
}
ifp = sc->ifp;
ic = ifp->if_l2com;
prog = rt2860_rf_2850;
/* get central channel position */
chan = ieee80211_chan2ieee(ic, c);
if ((sc->mac_rev & 0xffff0000) >= 0x30710000) {
rt3090_set_chan(sc, chan);
return;
}
if (IEEE80211_IS_CHAN_HT40U(c))
chan += 2;
else if (IEEE80211_IS_CHAN_HT40D(c))
chan -= 2;
RT2860_DPRINTF(sc, RT2860_DEBUG_CHAN,
"%s: RF set channel: channel=%u, HT%s%s\n",
device_get_nameunit(sc->dev),
ieee80211_chan2ieee(ic, c),
!IEEE80211_IS_CHAN_HT(c) ? " disabled" :
IEEE80211_IS_CHAN_HT20(c) ? "20":
IEEE80211_IS_CHAN_HT40U(c) ? "40U" : "40D",
(ic->ic_flags & IEEE80211_F_SCAN) ? ", scanning" : "");
if (chan == 0 || chan == IEEE80211_CHAN_ANY)
return;
for (i = 0; prog[i].chan != chan; i++);
r1 = prog[i].r1;
r2 = prog[i].r2;
r3 = prog[i].r3;
r4 = prog[i].r4;
txpow1 = sc->txpow1[i];
txpow2 = sc->txpow2[i];
if (sc->ntxpath == 1)
r2 |= (1 << 14);
if (sc->nrxpath == 2)
r2 |= (1 << 6);
else if (sc->nrxpath == 1)
r2 |= (1 << 17) | (1 << 6);
if (IEEE80211_IS_CHAN_2GHZ(c))
{
r3 = (r3 & 0xffffc1ff) | (txpow1 << 9);
r4 = (r4 & ~0x001f87c0) | (sc->rf_freq_off << 15) |
(txpow2 << 6);
}
else
{
r3 = r3 & 0xffffc1ff;
r4 = (r4 & ~0x001f87c0) | (sc->rf_freq_off << 15);
if (txpow1 >= RT2860_EEPROM_TXPOW_5GHZ_MIN && txpow1 < 0)
{
txpow1 = (-RT2860_EEPROM_TXPOW_5GHZ_MIN + txpow1);
if (txpow1 > RT2860_EEPROM_TXPOW_5GHZ_MAX)
txpow1 = RT2860_EEPROM_TXPOW_5GHZ_MAX;
r3 |= (txpow1 << 10);
}
else
{
if (txpow1 > RT2860_EEPROM_TXPOW_5GHZ_MAX)
txpow1 = RT2860_EEPROM_TXPOW_5GHZ_MAX;
r3 |= (txpow1 << 10) | (1 << 9);
}
if (txpow2 >= RT2860_EEPROM_TXPOW_5GHZ_MIN && txpow2 < 0)
{
txpow2 = (-RT2860_EEPROM_TXPOW_5GHZ_MIN + txpow2);
if (txpow2 > RT2860_EEPROM_TXPOW_5GHZ_MAX)
txpow2 = RT2860_EEPROM_TXPOW_5GHZ_MAX;
r4 |= (txpow2 << 7);
}
else
{
if (txpow2 > RT2860_EEPROM_TXPOW_5GHZ_MAX)
txpow2 = RT2860_EEPROM_TXPOW_5GHZ_MAX;
r4 |= (txpow2 << 7) | (1 << 6);
}
}
if (!(ic->ic_flags & IEEE80211_F_SCAN) && IEEE80211_IS_CHAN_HT40(c))
r4 |= (1 << 21);
rt2860_io_rf_write(sc, RT2860_REG_RF_R1, r1);
rt2860_io_rf_write(sc, RT2860_REG_RF_R2, r2);
rt2860_io_rf_write(sc, RT2860_REG_RF_R3, r3 & ~(1 << 2));
rt2860_io_rf_write(sc, RT2860_REG_RF_R4, r4);
DELAY(200);
rt2860_io_rf_write(sc, RT2860_REG_RF_R1, r1);
rt2860_io_rf_write(sc, RT2860_REG_RF_R2, r2);
rt2860_io_rf_write(sc, RT2860_REG_RF_R3, r3 | (1 << 2));
rt2860_io_rf_write(sc, RT2860_REG_RF_R4, r4);
DELAY(200);
rt2860_io_rf_write(sc, RT2860_REG_RF_R1, r1);
rt2860_io_rf_write(sc, RT2860_REG_RF_R2, r2);
rt2860_io_rf_write(sc, RT2860_REG_RF_R3, r3 & ~(1 << 2));
rt2860_io_rf_write(sc, RT2860_REG_RF_R4, r4);
rt2860_rf_select_chan_group(sc, c);
DELAY(1000);
}
