INTEL_I945GM_IDS(&intel_i945gm_info), INTEL_I965G_IDS(&intel_i965g_info), INTEL_G33_IDS(&intel_g33_info), INTEL_I965GM_IDS(&intel_i965gm_info), INTEL_GM45_IDS(&intel_gm45_info), INTEL_G45_IDS(&intel_g45_info), INTEL_PINEVIEW_IDS(&intel_pineview_info), INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), INTEL_SNB_D_IDS(&intel_sandybridge_d_info), INTEL_SNB_M_IDS(&intel_sandybridge_m_info), INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ INTEL_IVB_M_IDS(&intel_ivybridge_m_info), INTEL_IVB_D_IDS(&intel_ivybridge_d_info), INTEL_HSW_D_IDS(&intel_haswell_d_info), INTEL_HSW_M_IDS(&intel_haswell_m_info), INTEL_VLV_M_IDS(&intel_valleyview_m_info), INTEL_VLV_D_IDS(&intel_valleyview_d_info), INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info), INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info), INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), INTEL_CHV_IDS(&intel_cherryview_info), INTEL_SKL_GT1_IDS(&intel_skylake_info), INTEL_SKL_GT2_IDS(&intel_skylake_info), INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info), INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info), INTEL_BXT_IDS(&intel_broxton_info), INTEL_KBL_GT1_IDS(&intel_kabylake_info), INTEL_KBL_GT2_IDS(&intel_kabylake_info), INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
INTEL_I965GM_IDS(040),
INTEL_G45_IDS(045),
INTEL_GM45_IDS(045),
INTEL_IRONLAKE_D_IDS(050),
INTEL_IRONLAKE_M_IDS(050),
INTEL_SNB_D_IDS(060),
INTEL_SNB_M_IDS(060),
INTEL_IVB_D_IDS(070),
INTEL_IVB_M_IDS(070),
INTEL_HSW_D_IDS(075),
INTEL_HSW_M_IDS(075),
INTEL_VLV_D_IDS(071),
INTEL_VLV_M_IDS(071),
INTEL_BDW_D_IDS(0100),
INTEL_BDW_M_IDS(0100),
};
static int i915_gen(int device)
{
struct drm_i915_getparam gp;
int devid = 0;
int n;
gp.param = I915_PARAM_CHIPSET_ID;