static int
legacy_uart_probe( void )
{
/* Verify that the Scratch Register is accessible */
IO_WRITE( SCR, 0x5a );
if (IO_READ(SCR) != 0x5a) return 0;
IO_WRITE( SCR, 0xa5 );
if (IO_READ(SCR) != 0xa5) return 0;
return 1;
}
static int netx_serial_getc(struct console_device *cdev)
{
struct device_d *dev = cdev->dev;
int c;
while( IO_READ(dev->map_base + UART_FR) & FR_RXFE );
c = IO_READ(dev->map_base + UART_DR);
IO_READ(dev->map_base + UART_SR);
return c;
}
static int
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
static int irq_state = 0;
channel_data_t* chan = (channel_data_t*)__ch_data;
int ret = 0;
cyg_uint8 status;
CYGARC_HAL_SAVE_GP();
switch (__func) {
case __COMMCTL_IRQ_ENABLE:
irq_state = 1;
// Ensure that only Receive ints are generated.
status = IO_READ(chan->base + AMBA_UARTCR);
status |= (AMBA_UARTCR_RTIE | AMBA_UARTCR_RIE);
HAL_WRITE_UINT32(chan->base + AMBA_UARTCR, status);
HAL_INTERRUPT_UNMASK(chan->isr_vector);
break;
case __COMMCTL_IRQ_DISABLE:
ret = irq_state;
irq_state = 0;
status = IO_READ(chan->base + AMBA_UARTCR);
status &= ~(AMBA_UARTCR_RTIE | AMBA_UARTCR_TIE | AMBA_UARTCR_RIE | AMBA_UARTCR_MSIE);
HAL_WRITE_UINT32(chan->base + AMBA_UARTCR, status);
HAL_INTERRUPT_MASK(chan->isr_vector);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = chan->isr_vector;
break;
case __COMMCTL_SET_TIMEOUT:
{
va_list ap;
va_start(ap, __func);
ret = chan->msec_timeout;
chan->msec_timeout = va_arg(ap, cyg_uint32);
va_end(ap);
}
default:
break;
}
CYGARC_HAL_RESTORE_GP();
return ret;
}
static int
legacy_uart_rr0( void )
{
unsigned char lsr;
lsr = IO_READ( LSR );
if ( lsr & (UART_LSR_FE | UART_LSR_PE | UART_LSR_OE) )
{
IO_READ( RBR ); /* discard */
return 0;
}
return (lsr & UART_LSR_DR);
}
static void
legacy_uart_init( void )
{
/* Disable hardware interrupts */
IO_WRITE( MCR, 0 );
IO_WRITE( IER, 0 );
/* Disable FIFO's for 16550 devices */
IO_WRITE( FCR, 0 );
/* Set for 8-bit, no parity, DLAB bit cleared */
IO_WRITE( LCR, UART_LCR_8BITS );
/* Set baud rate */
gPESF->uart_set_baud_rate ( 0, uart_baud_rate );
/* Assert DTR# and RTS# lines (OUT2?) */
IO_WRITE( MCR, UART_MCR_DTR | UART_MCR_RTS );
/* Clear any garbage in the input buffer */
IO_READ( RBR );
uart_initted = 1;
}
//Read one byte of Calendar/Clock data
static uint8_t read_byte(void)
{
uint8_t byte = 0;
uint8_t i;
//Port pins in read mode for data read
READ_MODE();
//Disable internal I/O pull-up
DISABLE_IO_PULLUP();
//Read one byte of Calendar/Clock data
for(i = 0; i != 8; ++i)
{
//Strobe SCLK low to read I/O
SCLK_STROBE_LOW();
_delay_us(1);
if(IO_READ() != 0)
{
byte |= 1<<i;
}
//Strobe SCLK high for next I/O read
SCLK_STROBE_HIGH();
_delay_us(1);
}
return byte;
}
int do_dma_cp ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
ulong addr, dest, count;
int size;
EDMA_Config image_transfer;
if (argc != 4)
return cmd_usage(cmdtp);
/* Check for size specification.
*/
if ((size = cmd_get_data_size(argv[0], 4)) < 0)
return 1;
addr = simple_strtoul(argv[1], NULL, 16);
addr += base_address;
dest = simple_strtoul(argv[2], NULL, 16);
dest += base_address;
count = simple_strtoul(argv[3], NULL, 16);
if (count == 0) {
puts ("Zero length ???\n");
return 1;
}
//hEdma=_EDMA_MK_HANDLE(10*_EDMA_ENTRY_SIZE,EDMA_RSV6,_EDMA_TYPE_C);
{
image_transfer.opt=0x0010A00C;
image_transfer.src=addr;
image_transfer.acnt=size;
image_transfer.bcnt=count/size;
image_transfer.dst=dest;
image_transfer.srcbidx=size;
image_transfer.dstbidx=size;
image_transfer.link=0xffff;
image_transfer.bcntrld=0x0;
image_transfer.srccidx=0x0;
image_transfer.dstcidx=0x0;
image_transfer.ccnt=0x01;
}
EDMA_config(10, &image_transfer);
//EDMA_enableChannel(10); //EESR
IO_WRITE(EDMACC_EESR_ADDR, 1<<10);
//EDMA_setChannel(10); //ESR
IO_WRITE(EDMACC_ESR_ADDR, 1<<10);
while((IO_READ(EDMACC_IPR_ADDR)&(1<<10)) ==0);
IO_WRITE(EDMACC_ICR_ADDR, 1<<10);
return 0;
}
static void netx_serial_putc(struct console_device *cdev, char c)
{
struct device_d *dev = cdev->dev;
while( IO_READ(dev->map_base + UART_FR) & FR_TXFF );
IO_WRITE(dev->map_base + UART_DR, c);
}
int main() {
uart_init();
uart_puts("-------------------------------------------------\n");
uart_puts("CORE0 READY\n");
uart_puts("-------------------------------------------------\n");
uart_puts(" V3D TEST\n");
uart_puts("-------------------------------------------------\n");
mailbox_qpu_enable();
if( IO_READ(V3D_IDENT0) == 0x02443356) {
uart_puts(" OK! BLINK STATUS LED\n");
} else {
uart_puts(" NG\n");
}
uart_puts("-------------------------------------------------\n");
uint32_t size = mailbox_fb_init(SCREEN_WIDTH, SCREEN_HEIGHT);
mailbox_fb *fb = mailbox_fb_getaddr();
if(fb->pointer == 0) {
uart_puts(" NG fb->pointer == 0\n");
}
uart_puts("GET FRAMEBUFFER\n");
uart_debug_puts("fb->width =\n", fb->width);
uart_debug_puts("fb->height =\n", fb->height);
uart_debug_puts("fb->size =\n", size);
uart_debug_puts("fb->pointer=\n", fb->pointer);
IO_WRITE(V3D_L2CACTL, 0x1);
uart_debug_puts("V3D_L2CACTL=\n", IO_READ(V3D_L2CACTL));
int count = 0;
int x, y;
uint32_t *ptr = (uint32_t *)VcToArm(fb->pointer);
for(y = 1 ; y < fb->height; y++) {
for(x = 1 ; x < fb->width; x++) {
if(!(x % 16) || !(y % 16)) ptr[x + y * fb->width] = 0xFF00FFFF;
}
}
count++;
testTriangle(fb);
return 0;
}
static void
legacy_uart_set_baud_rate( __unused int unit, uint32_t baud_rate )
{
const unsigned char lcr = IO_READ( LCR );
unsigned long div;
if (baud_rate == 0) baud_rate = 9600;
div = LEGACY_UART_CLOCK / 16 / baud_rate;
IO_WRITE( LCR, lcr | UART_LCR_DLAB );
IO_WRITE( DLM, (unsigned char)(div >> 8) );
IO_WRITE( DLL, (unsigned char) div );
IO_WRITE( LCR, lcr & ~UART_LCR_DLAB);
}
static int
legacy_uart_rd0( void )
{
return IO_READ( RBR );
}
static int
legacy_uart_tr0( void )
{
return (IO_READ(LSR) & UART_LSR_THRE);
}
int do_dma_rev ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
ulong addr, dest, count;
int size;
EDMA_Config image_transfer;
unsigned int timer_start=0;
unsigned int timer_end=0;
unsigned short *p=(unsigned short *)0x8A000000;
if (argc != 4)
return cmd_usage(cmdtp);
*(unsigned int *)0x01c67008 = 0x1;
*(unsigned int *)0x01c67010 |= 0x8;
*(unsigned int *)0x01c67024 = 0x8;
*(unsigned int *)0x01c67030 = 0x8;
/* Check for size specification.
*/
if ((size = cmd_get_data_size(argv[0], 4)) < 0)
return 1;
addr = simple_strtoul(argv[1], NULL, 16);
addr += base_address;
dest = simple_strtoul(argv[2], NULL, 16);
dest += base_address;
count = simple_strtoul(argv[3], NULL, 16);
if (count == 0) {
puts ("Zero length ???\n");
return 1;
}
while(1)
{
*p++ = *(unsigned int *)0x01c21414;
IO_WRITE(EDMACC_EECRH_ADDR, 1<<3);
IO_WRITE(EDMACC_ESR_ADDR-4, 1<<3);
//hEdma=_EDMA_MK_HANDLE(10*_EDMA_ENTRY_SIZE,EDMA_RSV6,_EDMA_TYPE_C);
{
image_transfer.opt=0x00123004;
image_transfer.src=0x2002020;
image_transfer.acnt=2;
image_transfer.bcnt=0x2130;
image_transfer.dst=0x85000000;
image_transfer.srcbidx=0;
image_transfer.dstbidx=2;
image_transfer.link=0xffff;
image_transfer.bcntrld=0;
image_transfer.srccidx=0;
image_transfer.dstcidx=0;
//image_transfer.ccnt=count/(size*1062);
image_transfer.ccnt=1;
}
EDMA_config(35, &image_transfer);
IO_WRITE(EDMACC_ICRH_ADDR, 1<<3);
//EDMA_enableChannel(35); //EESR
IO_WRITE(EDMACC_SECRH_ADDR, 1<<3);
IO_WRITE(EDMACC_EESRH_ADDR, 1<<3);
//EDMA_setChannel(35); //ESR
//IO_WRITE(EDMACC_ESR_ADDR+4, 1<<3);
while((IO_READ(EDMACC_IPRH_ADDR)&(1<<3)) ==0);
IO_WRITE(EDMACC_EECRH_ADDR, 1<<3);
*p++ = *(unsigned int *)0x01c21414;
//printf("dma recv tb1 OK! time = %d\n",timer_end -timer_start);
IO_WRITE(EDMACC_EECR_ADDR, 1<<11);
{
image_transfer.opt=0x0010B004;
image_transfer.src=0x2002040;
image_transfer.acnt=2;
image_transfer.bcnt=0x554;
image_transfer.dst=0x87000000;
image_transfer.srcbidx=0;
image_transfer.dstbidx=2;
image_transfer.link=0xffff;
image_transfer.bcntrld=0;
image_transfer.srccidx=0;
image_transfer.dstcidx=0;
//image_transfer.ccnt=count/(size*1062);
image_transfer.ccnt=1;
}
EDMA_config(11, &image_transfer);
IO_WRITE(EDMACC_ICR_ADDR, 1<<11);
//EDMA_enableChannel(35); //EESR
IO_WRITE(EDMACC_SECR_ADDR, 1<<11);
IO_WRITE(EDMACC_ESR_ADDR, 1<<11);
IO_WRITE(EDMACC_EESR_ADDR, 1<<11);
//EDMA_setChannel(35); //ESR
//IO_WRITE(EDMACC_ESR_ADDR+4, 1<<3);
while((IO_READ(EDMACC_IPR_ADDR)&(1<<11)) ==0);
IO_WRITE(EDMACC_EECR_ADDR, 1<<11);
*p++ = *(unsigned int *)0x01c21414;
//printf("dma recv tb2 OK! time = %d\n",timer_end -timer_start);
//run_command("cmp.b 0x86000000 0x87000000 0xAA8",0);
//run_command("cmp.b 0x84000000 0x85000000 0x4260",0);
if (ctrlc())
{
putc ('\n');
break;
}
*p++ = *(unsigned int *)0x01c21414;
}
return 0;
}
int do_dma_send ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
ulong addr, dest, count;
int size;
EDMA_Config image_transfer;
unsigned int timer_start=0;
unsigned int timer_end=0;
unsigned short *p=(unsigned short *)0x88000000;
if (argc != 4)
return cmd_usage(cmdtp);
//for(size = 0;size<0x10000; size++)
//*p++ = size;
*(unsigned int *)0x01c67008 = 0x1;
*(unsigned int *)0x01c67010 |= 0x8;
*(unsigned int *)0x01c67024 = 0x8;
*(unsigned int *)0x01c67030 = 0x8;
/* Check for size specification.
*/
size = 2;
addr = simple_strtoul(argv[1], NULL, 16);
addr += base_address;
dest = simple_strtoul(argv[2], NULL, 16);
dest += base_address;
count = simple_strtoul(argv[3], NULL, 16);
if (count == 0) {
puts ("Zero length ???\n");
return 1;
}
while(1)
{
*p++ = *(unsigned int *)0x01c21414;
IO_WRITE(EDMACC_EECRH_ADDR, 1<<3);
//IO_WRITE(EDMACC_ICRH_ADDR, 1<<3);
IO_WRITE(EDMACC_ESR_ADDR-4, 1<<3);
//hEdma=_EDMA_MK_HANDLE(10*_EDMA_ENTRY_SIZE,EDMA_RSV6,_EDMA_TYPE_C);
{
image_transfer.opt=0x00123004;
image_transfer.src=0x84000000;
image_transfer.acnt=2;
//image_transfer.bcnt=count/2;
image_transfer.bcnt=0x2130;
image_transfer.dst=0x2002004;
image_transfer.srcbidx=size;
image_transfer.dstbidx=0;
image_transfer.link=0xFFFF;
image_transfer.bcntrld=0;
image_transfer.srccidx=0;
image_transfer.dstcidx=0;
image_transfer.ccnt=1;
}
EDMA_config(35, &image_transfer);
IO_WRITE(EDMACC_ICRH_ADDR, 1<<3);
IO_WRITE(EDMACC_SECRH_ADDR, 1<<3);
IO_WRITE(EDMACC_EESRH_ADDR, 1<<3);
*p++ = *(unsigned int *)0x01c21414;
//printf("dma send tb1 start wait! time = %d\n",timer_end -timer_start);
while((IO_READ(EDMACC_IPRH_ADDR)&(1<<3)) ==0);
IO_WRITE(EDMACC_EECRH_ADDR, 1<<3);
*p++ = *(unsigned int *)0x01c21414;
//printf("dma send tb1 OK! time = %d\n",timer_end -timer_start);
IO_WRITE(EDMACC_EECR_ADDR, 1<<10);
{
image_transfer.opt=0x0010A004;
image_transfer.src=0x86000000;
image_transfer.acnt=2;
//image_transfer.bcnt=count/2;
image_transfer.bcnt=0x554;
image_transfer.dst=0x2002008;
image_transfer.srcbidx=size;
image_transfer.dstbidx=0;
image_transfer.link=0xffff;
image_transfer.bcntrld=0;
image_transfer.srccidx=0;
image_transfer.dstcidx=0;
image_transfer.ccnt=1;
}
EDMA_config(10, &image_transfer);
IO_WRITE(EDMACC_ICR_ADDR, 1<<10);
//EDMA_enableChannel(35); //EESR
IO_WRITE(EDMACC_SECR_ADDR, 1<<10);
IO_WRITE(EDMACC_ESR_ADDR, 1<<10);
IO_WRITE(EDMACC_EESR_ADDR, 1<<10);
*p++ = *(unsigned int *)0x01c21414;
//printf("dma send tb2 start wait! time = %d\n",timer_end -timer_start);
while((IO_READ(EDMACC_IPR_ADDR)&(1<<10)) ==0);
IO_WRITE(EDMACC_EECR_ADDR, 1<<10);
*p++ = *(unsigned int *)0x01c21414;
//printf("dma send tb2 OK! time = %d\n",timer_end -timer_start);
if (ctrlc())
{
putc ('\n');
break;
}
*p++ = *(unsigned int *)0x01c21414;
}
return 0;
}
static int netx_serial_tstc(struct console_device *cdev)
{
struct device_d *dev = cdev->dev;
return (IO_READ(dev->map_base + UART_FR) & FR_RXFE) ? 0 : 1;
}
