static void
legacy_uart_init( void )
{
/* Disable hardware interrupts */
IO_WRITE( MCR, 0 );
IO_WRITE( IER, 0 );
/* Disable FIFO's for 16550 devices */
IO_WRITE( FCR, 0 );
/* Set for 8-bit, no parity, DLAB bit cleared */
IO_WRITE( LCR, UART_LCR_8BITS );
/* Set baud rate */
gPESF->uart_set_baud_rate ( 0, uart_baud_rate );
/* Assert DTR# and RTS# lines (OUT2?) */
IO_WRITE( MCR, UART_MCR_DTR | UART_MCR_RTS );
/* Clear any garbage in the input buffer */
IO_READ( RBR );
uart_initted = 1;
}
int do_dma_cp ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
ulong addr, dest, count;
int size;
EDMA_Config image_transfer;
if (argc != 4)
return cmd_usage(cmdtp);
/* Check for size specification.
*/
if ((size = cmd_get_data_size(argv[0], 4)) < 0)
return 1;
addr = simple_strtoul(argv[1], NULL, 16);
addr += base_address;
dest = simple_strtoul(argv[2], NULL, 16);
dest += base_address;
count = simple_strtoul(argv[3], NULL, 16);
if (count == 0) {
puts ("Zero length ???\n");
return 1;
}
//hEdma=_EDMA_MK_HANDLE(10*_EDMA_ENTRY_SIZE,EDMA_RSV6,_EDMA_TYPE_C);
{
image_transfer.opt=0x0010A00C;
image_transfer.src=addr;
image_transfer.acnt=size;
image_transfer.bcnt=count/size;
image_transfer.dst=dest;
image_transfer.srcbidx=size;
image_transfer.dstbidx=size;
image_transfer.link=0xffff;
image_transfer.bcntrld=0x0;
image_transfer.srccidx=0x0;
image_transfer.dstcidx=0x0;
image_transfer.ccnt=0x01;
}
EDMA_config(10, &image_transfer);
//EDMA_enableChannel(10); //EESR
IO_WRITE(EDMACC_EESR_ADDR, 1<<10);
//EDMA_setChannel(10); //ESR
IO_WRITE(EDMACC_ESR_ADDR, 1<<10);
while((IO_READ(EDMACC_IPR_ADDR)&(1<<10)) ==0);
IO_WRITE(EDMACC_ICR_ADDR, 1<<10);
return 0;
}
static int
legacy_uart_probe( void )
{
/* Verify that the Scratch Register is accessible */
IO_WRITE( SCR, 0x5a );
if (IO_READ(SCR) != 0x5a) return 0;
IO_WRITE( SCR, 0xa5 );
if (IO_READ(SCR) != 0xa5) return 0;
return 1;
}
static void
legacy_uart_set_baud_rate( __unused int unit, uint32_t baud_rate )
{
const unsigned char lcr = IO_READ( LCR );
unsigned long div;
if (baud_rate == 0) baud_rate = 9600;
div = LEGACY_UART_CLOCK / 16 / baud_rate;
IO_WRITE( LCR, lcr | UART_LCR_DLAB );
IO_WRITE( DLM, (unsigned char)(div >> 8) );
IO_WRITE( DLL, (unsigned char) div );
IO_WRITE( LCR, lcr & ~UART_LCR_DLAB);
}
static void netx_serial_putc(struct console_device *cdev, char c)
{
struct device_d *dev = cdev->dev;
while( IO_READ(dev->map_base + UART_FR) & FR_TXFF );
IO_WRITE(dev->map_base + UART_DR, c);
}
static int netx_serial_init_port(struct console_device *cdev)
{
struct device_d *dev = cdev->dev;
unsigned int divisor;
/* disable uart */
IO_WRITE( dev->map_base + UART_CR, 0);
IO_WRITE( dev->map_base + UART_LINE_CR, LINE_CR_8BIT | LINE_CR_FEN);
IO_WRITE( dev->map_base + UART_DRV_ENABLE, DRV_ENABLE_TX | DRV_ENABLE_RTS );
/* set baud rate */
divisor = 115200 * 4096;
divisor /= 1000;
divisor *= 256;
divisor /= 100000;
IO_WRITE( dev->map_base + UART_BAUDDIV_MSB, (divisor >> 8) & 0xff );
IO_WRITE( dev->map_base + UART_BAUDDIV_LSB, divisor & 0xff );
IO_WRITE( dev->map_base + UART_BRM_CR, BRM_CR_BAUD_RATE_MODE);
/* Finally, enable the UART */
IO_WRITE( dev->map_base + UART_CR, CR_UARTEN);
return 0;
}
u8 usbListener() {
volatile u16 resp;
volatile u8 cmd;
usb_buff8 = (u8 *) usb_buff;
if (evd_fifoRxf())return 0;
resp = evd_fifoRd(usb_buff, 1);
if (resp != 0) return 1;
if (usb_buff8[0] != 'C' || usb_buff8[1] != 'M' || usb_buff8[2] != 'D')return 2;
cmd = usb_buff8[3];
switch (cmd) {
case 'R':
resp = cmdReadRom();
if (resp)return 10;
break;
case 'W':
resp = cmdWriteRom();
if (resp)return 11;
break;
case 'T':
resp = cmdTest();
if (resp)return 12;
break;
case 'F':
resp = cmdFill();
if (resp)return 13;
break;
case 'S':
//IO_WRITE(PI_BSD_DOM1_PGS_REG, 0x0c);
//IO_WRITE(PI_BSD_DOM1_PGS_REG, 0x80);
//evdSetESaveType(SAVE_TYPE_EEP16k);
system_cic = CIC_6102;
evd_lockRegs();
IO_WRITE(PI_STATUS_REG, 3);
sleep(2);
pif_boot();
break;
}
return 0;
}
static void
cyg_hal_plf_serial_init_channel(void* __ch_data)
{
cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
// first, disable everything
IO_WRITE(base + AMBA_UARTCR, 0x0);
// Set baud rate CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD
IO_WRITE(base + AMBA_UARTLCR_M, ((ARM_INTEGRATOR_BAUD_DIVISOR & 0xf00) >> 8));
IO_WRITE(base + AMBA_UARTLCR_L, (ARM_INTEGRATOR_BAUD_DIVISOR & 0xff));
// ----------v----------v----------v----------v----------
// NOTE: MUST BE WRITTEN LAST (AFTER UARTLCR_M & UARTLCR_L)
// ----------^----------^----------^----------^----------
// set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled
IO_WRITE(base + AMBA_UARTLCR_H, (AMBA_UARTLCR_H_WLEN_8 | AMBA_UARTLCR_H_FEN));
// finally, enable the uart
IO_WRITE(base + AMBA_UARTCR, AMBA_UARTCR_UARTEN);
}
int main() {
uart_init();
uart_puts("-------------------------------------------------\n");
uart_puts("CORE0 READY\n");
uart_puts("-------------------------------------------------\n");
uart_puts(" V3D TEST\n");
uart_puts("-------------------------------------------------\n");
mailbox_qpu_enable();
if( IO_READ(V3D_IDENT0) == 0x02443356) {
uart_puts(" OK! BLINK STATUS LED\n");
} else {
uart_puts(" NG\n");
}
uart_puts("-------------------------------------------------\n");
uint32_t size = mailbox_fb_init(SCREEN_WIDTH, SCREEN_HEIGHT);
mailbox_fb *fb = mailbox_fb_getaddr();
if(fb->pointer == 0) {
uart_puts(" NG fb->pointer == 0\n");
}
uart_puts("GET FRAMEBUFFER\n");
uart_debug_puts("fb->width =\n", fb->width);
uart_debug_puts("fb->height =\n", fb->height);
uart_debug_puts("fb->size =\n", size);
uart_debug_puts("fb->pointer=\n", fb->pointer);
IO_WRITE(V3D_L2CACTL, 0x1);
uart_debug_puts("V3D_L2CACTL=\n", IO_READ(V3D_L2CACTL));
int count = 0;
int x, y;
uint32_t *ptr = (uint32_t *)VcToArm(fb->pointer);
for(y = 1 ; y < fb->height; y++) {
for(x = 1 ; x < fb->width; x++) {
if(!(x % 16) || !(y % 16)) ptr[x + y * fb->width] = 0xFF00FFFF;
}
}
count++;
testTriangle(fb);
return 0;
}
void spi_init(void) {
/* all output except MISO; all high, plus pullups on MISO */
IO_WRITE(PORT(IO_SPI), IO_SPI_ALL | IO_SPI_SS_ALL, IO_SPI_SS_ALL);
IO_WRITE(DDR(IO_SPI), IO_SPI_ALL | IO_SPI_SS_ALL,
(IO_SPI_ALL ^ IO_SPI_MISO) | IO_SPI_SS_ALL);
}
static void _spi_deselect(void) {
IO_WRITE(PORT(IO_SPI), IO_SPI_SS_ALL, IO_SPI_SS_ALL);
}
static void _spi_select(uint8_t slave){
IO_WRITE(PORT(IO_SPI), IO_SPI_SS_ALL, IO_SPI_SS_ALL ^ slave);
}
static void
legacy_uart_td0( int c )
{
IO_WRITE( THR, c );
}
int do_dma_rev ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
ulong addr, dest, count;
int size;
EDMA_Config image_transfer;
unsigned int timer_start=0;
unsigned int timer_end=0;
unsigned short *p=(unsigned short *)0x8A000000;
if (argc != 4)
return cmd_usage(cmdtp);
*(unsigned int *)0x01c67008 = 0x1;
*(unsigned int *)0x01c67010 |= 0x8;
*(unsigned int *)0x01c67024 = 0x8;
*(unsigned int *)0x01c67030 = 0x8;
/* Check for size specification.
*/
if ((size = cmd_get_data_size(argv[0], 4)) < 0)
return 1;
addr = simple_strtoul(argv[1], NULL, 16);
addr += base_address;
dest = simple_strtoul(argv[2], NULL, 16);
dest += base_address;
count = simple_strtoul(argv[3], NULL, 16);
if (count == 0) {
puts ("Zero length ???\n");
return 1;
}
while(1)
{
*p++ = *(unsigned int *)0x01c21414;
IO_WRITE(EDMACC_EECRH_ADDR, 1<<3);
IO_WRITE(EDMACC_ESR_ADDR-4, 1<<3);
//hEdma=_EDMA_MK_HANDLE(10*_EDMA_ENTRY_SIZE,EDMA_RSV6,_EDMA_TYPE_C);
{
image_transfer.opt=0x00123004;
image_transfer.src=0x2002020;
image_transfer.acnt=2;
image_transfer.bcnt=0x2130;
image_transfer.dst=0x85000000;
image_transfer.srcbidx=0;
image_transfer.dstbidx=2;
image_transfer.link=0xffff;
image_transfer.bcntrld=0;
image_transfer.srccidx=0;
image_transfer.dstcidx=0;
//image_transfer.ccnt=count/(size*1062);
image_transfer.ccnt=1;
}
EDMA_config(35, &image_transfer);
IO_WRITE(EDMACC_ICRH_ADDR, 1<<3);
//EDMA_enableChannel(35); //EESR
IO_WRITE(EDMACC_SECRH_ADDR, 1<<3);
IO_WRITE(EDMACC_EESRH_ADDR, 1<<3);
//EDMA_setChannel(35); //ESR
//IO_WRITE(EDMACC_ESR_ADDR+4, 1<<3);
while((IO_READ(EDMACC_IPRH_ADDR)&(1<<3)) ==0);
IO_WRITE(EDMACC_EECRH_ADDR, 1<<3);
*p++ = *(unsigned int *)0x01c21414;
//printf("dma recv tb1 OK! time = %d\n",timer_end -timer_start);
IO_WRITE(EDMACC_EECR_ADDR, 1<<11);
{
image_transfer.opt=0x0010B004;
image_transfer.src=0x2002040;
image_transfer.acnt=2;
image_transfer.bcnt=0x554;
image_transfer.dst=0x87000000;
image_transfer.srcbidx=0;
image_transfer.dstbidx=2;
image_transfer.link=0xffff;
image_transfer.bcntrld=0;
image_transfer.srccidx=0;
image_transfer.dstcidx=0;
//image_transfer.ccnt=count/(size*1062);
image_transfer.ccnt=1;
}
EDMA_config(11, &image_transfer);
IO_WRITE(EDMACC_ICR_ADDR, 1<<11);
//EDMA_enableChannel(35); //EESR
IO_WRITE(EDMACC_SECR_ADDR, 1<<11);
IO_WRITE(EDMACC_ESR_ADDR, 1<<11);
IO_WRITE(EDMACC_EESR_ADDR, 1<<11);
//EDMA_setChannel(35); //ESR
//IO_WRITE(EDMACC_ESR_ADDR+4, 1<<3);
while((IO_READ(EDMACC_IPR_ADDR)&(1<<11)) ==0);
IO_WRITE(EDMACC_EECR_ADDR, 1<<11);
*p++ = *(unsigned int *)0x01c21414;
//printf("dma recv tb2 OK! time = %d\n",timer_end -timer_start);
//run_command("cmp.b 0x86000000 0x87000000 0xAA8",0);
//run_command("cmp.b 0x84000000 0x85000000 0x4260",0);
if (ctrlc())
{
putc ('\n');
break;
}
*p++ = *(unsigned int *)0x01c21414;
}
return 0;
}
int do_dma_send ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
ulong addr, dest, count;
int size;
EDMA_Config image_transfer;
unsigned int timer_start=0;
unsigned int timer_end=0;
unsigned short *p=(unsigned short *)0x88000000;
if (argc != 4)
return cmd_usage(cmdtp);
//for(size = 0;size<0x10000; size++)
//*p++ = size;
*(unsigned int *)0x01c67008 = 0x1;
*(unsigned int *)0x01c67010 |= 0x8;
*(unsigned int *)0x01c67024 = 0x8;
*(unsigned int *)0x01c67030 = 0x8;
/* Check for size specification.
*/
size = 2;
addr = simple_strtoul(argv[1], NULL, 16);
addr += base_address;
dest = simple_strtoul(argv[2], NULL, 16);
dest += base_address;
count = simple_strtoul(argv[3], NULL, 16);
if (count == 0) {
puts ("Zero length ???\n");
return 1;
}
while(1)
{
*p++ = *(unsigned int *)0x01c21414;
IO_WRITE(EDMACC_EECRH_ADDR, 1<<3);
//IO_WRITE(EDMACC_ICRH_ADDR, 1<<3);
IO_WRITE(EDMACC_ESR_ADDR-4, 1<<3);
//hEdma=_EDMA_MK_HANDLE(10*_EDMA_ENTRY_SIZE,EDMA_RSV6,_EDMA_TYPE_C);
{
image_transfer.opt=0x00123004;
image_transfer.src=0x84000000;
image_transfer.acnt=2;
//image_transfer.bcnt=count/2;
image_transfer.bcnt=0x2130;
image_transfer.dst=0x2002004;
image_transfer.srcbidx=size;
image_transfer.dstbidx=0;
image_transfer.link=0xFFFF;
image_transfer.bcntrld=0;
image_transfer.srccidx=0;
image_transfer.dstcidx=0;
image_transfer.ccnt=1;
}
EDMA_config(35, &image_transfer);
IO_WRITE(EDMACC_ICRH_ADDR, 1<<3);
IO_WRITE(EDMACC_SECRH_ADDR, 1<<3);
IO_WRITE(EDMACC_EESRH_ADDR, 1<<3);
*p++ = *(unsigned int *)0x01c21414;
//printf("dma send tb1 start wait! time = %d\n",timer_end -timer_start);
while((IO_READ(EDMACC_IPRH_ADDR)&(1<<3)) ==0);
IO_WRITE(EDMACC_EECRH_ADDR, 1<<3);
*p++ = *(unsigned int *)0x01c21414;
//printf("dma send tb1 OK! time = %d\n",timer_end -timer_start);
IO_WRITE(EDMACC_EECR_ADDR, 1<<10);
{
image_transfer.opt=0x0010A004;
image_transfer.src=0x86000000;
image_transfer.acnt=2;
//image_transfer.bcnt=count/2;
image_transfer.bcnt=0x554;
image_transfer.dst=0x2002008;
image_transfer.srcbidx=size;
image_transfer.dstbidx=0;
image_transfer.link=0xffff;
image_transfer.bcntrld=0;
image_transfer.srccidx=0;
image_transfer.dstcidx=0;
image_transfer.ccnt=1;
}
EDMA_config(10, &image_transfer);
IO_WRITE(EDMACC_ICR_ADDR, 1<<10);
//EDMA_enableChannel(35); //EESR
IO_WRITE(EDMACC_SECR_ADDR, 1<<10);
IO_WRITE(EDMACC_ESR_ADDR, 1<<10);
IO_WRITE(EDMACC_EESR_ADDR, 1<<10);
*p++ = *(unsigned int *)0x01c21414;
//printf("dma send tb2 start wait! time = %d\n",timer_end -timer_start);
while((IO_READ(EDMACC_IPR_ADDR)&(1<<10)) ==0);
IO_WRITE(EDMACC_EECR_ADDR, 1<<10);
*p++ = *(unsigned int *)0x01c21414;
//printf("dma send tb2 OK! time = %d\n",timer_end -timer_start);
if (ctrlc())
{
putc ('\n');
break;
}
*p++ = *(unsigned int *)0x01c21414;
}
return 0;
}
