/** * @brief Enables DAC and starts conversion of channel. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) { uint32_t tmp1 = 0, tmp2 = 0; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); /* Process locked */ __HAL_LOCK(hdac); /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; /* Enable the Peripheral */ __HAL_DAC_ENABLE(hdac, Channel); if(Channel == DAC_CHANNEL_1) { tmp1 = hdac->Instance->CR & DAC_CR_TEN1; tmp2 = hdac->Instance->CR & DAC_CR_TSEL1; /* Check if software trigger enabled */ if((tmp1 == DAC_CR_TEN1) && (tmp2 == DAC_CR_TSEL1)) { /* Enable the selected DAC software conversion */ hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1; } } else { tmp1 = hdac->Instance->CR & DAC_CR_TEN2; tmp2 = hdac->Instance->CR & DAC_CR_TSEL2; /* Check if software trigger enabled */ if((tmp1 == DAC_CR_TEN2) && (tmp2 == DAC_CR_TSEL2)) { /* Enable the selected DAC software conversion*/ hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG2; } } /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hdac); /* Return function status */ return HAL_OK; }
/** * @brief Select DAC Noise Wave Generation LFSR according to the specified * parameters. * @param DAC_Channel : the selected DAC channel from @ref DAC_Channel_TypeDef * enumeration. * @param DAC_LFSRUnmask : the selected unmasked bit from * @ref DAC_LFSRUnmask_TypeDef enumeration. * @retval None */ void DAC_NoiseWaveLFSR(DAC_Channel_TypeDef DAC_Channel, DAC_LFSRUnmask_TypeDef DAC_LFSRUnmask) { uint8_t tmpreg = 0; uint16_t cr2addr = 0; /* Check the DAC parameters */ assert_param(IS_DAC_CHANNEL(DAC_Channel)); assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_LFSRUnmask)); /* Get the DAC CHxCR2 value & Clear MAMPx bits */ cr2addr = (uint16_t)(DAC_BASE + CR2_Offset + (uint8_t)((uint8_t)DAC_Channel << 1)); tmpreg = (uint8_t)((*(uint8_t*)(cr2addr)) & (uint8_t)~(DAC_CR2_MAMPx)); /* Write to DAC CHxCR2 */ (*(uint8_t*)(cr2addr)) = (uint8_t)( tmpreg | DAC_LFSRUnmask); }
/** * @brief Software output control. * @param DACx: Select the DAC channel. * This parameter can be one of the following values: * TSB_DA0, TSB_DA1 * @retval SUCCESS or ERROR. */ Result DAC_SWOutput(TSB_DA_TypeDef * DACx) { Result retval = ERROR; uint32_t reg = 0U; assert_param(IS_DAC_CHANNEL(DACx)); /*Set the bit if <TRGEN>=1 is set. */ reg = DACx->DCTL & DAC_SWEN_TRG_MASK; if (reg == DAC_SWEN_TRG_DATA) { DACx->TCTL = DAC_SWRTG_DATA; retval = SUCCESS; } else { retval = ERROR; } return retval; }
/** * @brief Disables DAC and stop conversion of channel. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); /* Disable the selected DAC channel DMA request */ hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel); /* Disable the Peripheral */ __HAL_DAC_DISABLE(hdac, Channel); /* Disable the DMA channel */ /* Channel1 is used */ if (Channel == DAC_CHANNEL_1) { /* Disable the DMA channel */ status = HAL_DMA_Abort(hdac->DMA_Handle1); /* Disable the DAC DMA underrun interrupt */ __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1); } else /* Channel2 is used for */ { /* Disable the DMA channel */ status = HAL_DMA_Abort(hdac->DMA_Handle2); /* Disable the DAC DMA underrun interrupt */ __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2); } /* Check if DMA Channel effectively disabled */ if (status != HAL_OK) { /* Update DAC state machine to error */ hdac->State = HAL_DAC_STATE_ERROR; } else { /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; } /* Return function status */ return status; }
/** * @brief Enables or disables the selected DAC channel software trigger. * @param DAC_Channel : the selected DAC channel from * @ref DAC_Channel_TypeDef enumeration. * @param NewState : new state of the selected DAC channel software trigger. * This parameter can be: ENABLE or DISABLE. * @retval None. */ void DAC_SoftwareTriggerCmd(DAC_Channel_TypeDef DAC_Channel, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_DAC_CHANNEL(DAC_Channel)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable software trigger for the selected DAC channel */ DAC->SWTRIGR |= (uint8_t)(DAC_SWTRIGR_SWTRIG1 << DAC_Channel); } else { /* Disable software trigger for the selected DAC channel */ DAC->SWTRIGR &= (uint8_t)~((uint8_t)(DAC_SWTRIGR_SWTRIG1 << DAC_Channel)); } }
/** * @brief This function will set the DAC to the required value * @param port : the gpio port to use * @param pin : the gpio pin to use * @param value : the value to push on the adc output * @param do_init : if set to 1 the initialization of the adc is done * @retval None */ void dac_write_value(PinName pin, uint32_t value, uint8_t do_init) { DAC_HandleTypeDef DacHandle = {}; DAC_ChannelConfTypeDef dacChannelConf = {}; uint32_t dacChannel; DacHandle.Instance = pinmap_peripheral(pin, PinMap_DAC); if (DacHandle.Instance == NP) return; dacChannel = get_dac_channel(pin); if (!IS_DAC_CHANNEL(dacChannel)) return; if(do_init == 1) { if (HAL_DAC_DeInit(&DacHandle) != HAL_OK) { /* DeInitialization Error */ return; } /*##-1- Configure the DAC peripheral #######################################*/ g_current_pin = pin; if (HAL_DAC_Init(&DacHandle) != HAL_OK) { /* Initialization Error */ return; } dacChannelConf.DAC_Trigger = DAC_TRIGGER_NONE; dacChannelConf.DAC_OutputBuffer=DAC_OUTPUTBUFFER_ENABLE; /*##-2- Configure DAC channel1 #############################################*/ if (HAL_DAC_ConfigChannel(&DacHandle, &dacChannelConf, dacChannel) != HAL_OK) { /* Channel configuration Error */ return; } } /*##-3- Set DAC Channel1 DHR register ######################################*/ if (HAL_DAC_SetValue(&DacHandle, dacChannel, DAC_ALIGN_12B_R, value) != HAL_OK) { /* Setting value Error */ return; } /*##-4- Enable DAC Channel1 ################################################*/ HAL_DAC_Start(&DacHandle, dacChannel); }
/** * @brief Disables DAC and stop conversion of channel. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel) { /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); /* Disable the selected DAC channel DMA request */ hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel); /* Disable the Peripharal */ __HAL_DAC_DISABLE(hdac, Channel); /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; /* Return function status */ return HAL_OK; }
/** * @brief This function will stop the DAC * @param port : the gpio port to use * @param pin : the gpio pin to use * @retval None */ void dac_stop(PinName pin) { DAC_HandleTypeDef DacHandle; uint32_t dacChannel; DacHandle.Instance = pinmap_peripheral(pin, PinMap_DAC); if (DacHandle.Instance == NP) return; dacChannel = get_dac_channel(pin); if (!IS_DAC_CHANNEL(dacChannel)) return; HAL_DAC_Stop(&DacHandle, dacChannel); if (HAL_DAC_DeInit(&DacHandle) != HAL_OK) { /* DeInitialization Error */ return; } }
/** * @brief Set the specified data holding register value for DAC channel. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @param Alignment: Specifies the data alignment. * This parameter can be one of the following values: * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected * @param Data: Data to be loaded in the selected data holding register. * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data) { __IO uint32_t tmp = 0U; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_DAC_ALIGN(Alignment)); assert_param(IS_DAC_DATA(Data)); tmp = (uint32_t)hdac->Instance; tmp += DAC_DHR12R1_ALIGNEMENT(Alignment); /* Set the DAC channel selected data holding register */ *(__IO uint32_t *) tmp = Data; /* Return function status */ return HAL_OK; }
/** * @brief Set the specified data holding register value for DAC channel. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param alignment: Specifies the data alignment for DAC channel1. * This parameter can be one of the following values: * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected * @param data: Data to be loaded in the selected data holding register. * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t channel, uint32_t alignment, uint32_t data) { __IO uint32_t tmp = 0; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(channel)); assert_param(IS_DAC_ALIGN(alignment)); assert_param(IS_DAC_DATA(data)); tmp = (uint32_t)DAC_BASE; tmp += __HAL_DHR12R1_ALIGNEMENT(alignment); /* Set the DAC channel1 selected data holding register */ *(__IO uint32_t *) tmp = data; /* Return function status */ return HAL_OK; }
/** * @brief Enables DAC and starts conversion of channel. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) { /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); /* Process locked */ __HAL_LOCK(hdac); /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; /* Enable the Peripharal */ __HAL_DAC_ENABLE(hdac, Channel); if(Channel == DAC_CHANNEL_1) { /* Check if software trigger enabled */ if((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == (DAC_CR_TEN1 | DAC_CR_TSEL1)) { /* Enable the selected DAC software conversion */ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1); } } else { /* Check if software trigger enabled */ if((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_CR_TEN2 | DAC_CR_TSEL2)) { /* Enable the selected DAC software conversion*/ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2); } } /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hdac); /* Return function status */ return HAL_OK; }
/** * @brief Configures the selected DAC channel. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param sConfig: DAC configuration structure. * @param Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel) { uint32_t tmpreg1 = 0, tmpreg2 = 0; /* Check the DAC parameters */ assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger)); assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer)); assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger)); assert_param(IS_DAC_CHANNEL(Channel)); /* Process locked */ __HAL_LOCK(hdac); /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; /* Get the DAC CR value */ tmpreg1 = DAC->CR; /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ // tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel); tmpreg1 &= ~(((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel); /* Configure for the selected DAC channel: buffer output, trigger */ /* Set TSELx and TENx bits according to DAC_Trigger value */ /* Set BOFFx bit according to DAC_OutputBuffer value */ tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer); /* Calculate CR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << Channel; /* Write to DAC CR */ DAC->CR = tmpreg1; /* Disable wave generation */ // DAC->CR &= ~(DAC_CR_WAVE1 << Channel); /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hdac); /* Return function status */ return HAL_OK; }
/** * @brief Enables or disables the specified DAC channel. * @param DAC_Channel : the selected DAC channel from * @ref DAC_Channel_TypeDef enumeration. * @param NewState : new state of the DAC channel. * This parameter can be: ENABLE or DISABLE. * @retval None */ void DAC_Cmd(DAC_Channel_TypeDef DAC_Channel, FunctionalState NewState) { uint16_t cr1addr = 0; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(DAC_Channel)); assert_param(IS_FUNCTIONAL_STATE(NewState)); /* Find CHxCR1 register Address */ cr1addr = DAC_BASE + CR1_Offset + (uint8_t)((uint8_t)DAC_Channel << 1); if (NewState != DISABLE) { /* Enable the selected DAC channel */ (*(uint8_t*)(cr1addr)) |= DAC_CR1_EN; } else { /* Disable the selected DAC channel */ (*(uint8_t*)(cr1addr)) &= (uint8_t) ~(DAC_CR1_EN); } }
/** * @brief Enables DAC and starts conversion of channel. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) { /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); /* Process locked */ __HAL_LOCK(hdac); /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; /* Enable the Peripheral */ __HAL_DAC_ENABLE(hdac, Channel); /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hdac); /* Return function status */ return HAL_OK; }
/** * @brief Returns the last data output value of the selected DAC channel. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected * @retval The selected DAC channel data output value. */ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel) { /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); /* Returns the DAC channel data output register value */ #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) return hdac->Instance->DOR1; #endif /* STM32L451xx STM32L452xx STM32L462xx */ #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) if(Channel == DAC_CHANNEL_1) { return hdac->Instance->DOR1; } else { return hdac->Instance->DOR2; } #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ }
/** * @brief Enables or disables DAC Wave Generation according to the specified * parameters. * @param DAC_Channel : the selected DAC channel from @ref DAC_Channel_TypeDef * enumeration. * @param DAC_Wave : the selected waveform from @ref DAC_Wave_TypeDef enumeration. * @retval None */ void DAC_WaveGenerationCmd(DAC_Channel_TypeDef DAC_Channel, DAC_Wave_TypeDef DAC_Wave, FunctionalState NewState) { uint8_t tmpreg = 0; /* Check the DAC parameters */ assert_param(IS_DAC_CHANNEL(DAC_Channel)); assert_param(IS_DAC_WAVE(DAC_Wave)); assert_param(IS_FUNCTIONAL_STATE(NewState)); /* Get the DAC CHxCR1 value & Clear WAVEN bits */ tmpreg = (uint8_t)((*(uint8_t*)(uint16_t)(DAC_BASE + CR1_Offset + (uint8_t)((uint8_t)DAC_Channel << 1))) & (uint8_t)~(DAC_CR1_WAVEN)); if (NewState != DISABLE) { tmpreg |= (uint8_t)(DAC_Wave); } /* Write to DAC CHxCR1 */ (*(uint8_t*) (uint16_t)(DAC_BASE + CR1_Offset + (uint8_t)((uint8_t)DAC_Channel << 1))) = tmpreg; }
/** * @brief Set the specified data holding register value for DAC channel. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param Channel The selected DAC channel. * @param Alignment Specifies the data alignment for DAC channel. * This parameter can be one of the following values: * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected * @param Data Data to be loaded in the selected data holding register. * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data) { __IO uint32_t tmp = 0U; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_DAC_ALIGN(Alignment)); assert_param(IS_DAC_DATA(Data)); tmp = (uint32_t) (hdac->Instance); /* DAC 1 has 1 or 2 channels - no DAC2 */ /* DAC 1 has 2 channels 1U & 2U - DAC 2 has one channel 1U */ if(Channel == DAC_CHANNEL_1) { tmp += DAC_DHR12R1_ALIGNMENT(Alignment); } #if defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F373xC) || defined(STM32F378xx) else /* channel = DAC_CHANNEL_2 */ { tmp += DAC_DHR12R2_ALIGNMENT(Alignment); } #endif /* STM32F303xE || STM32F398xx || */ /* STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F373xC || STM32F378xx */ /* Set the DAC channel1 selected data holding register */ *(__IO uint32_t *) tmp = Data; /* Return function status */ return HAL_OK; }
/** * @brief Initialize the DAC. * @param DACx: Select the DAC channel. * This parameter can be one of the following values: * TSB_DA0, TSB_DA1 * @param InitStruct: The structure containing basic DAC configuration including clear DAC request, * set post adjustment for VOUTHOLD time, pre adjustment for VOUTHOLD time, * offset setting of output waveform, amplitude setting of output waveform, * output waveform selection, trigger selection and trigger function. * @retval None */ void DAC_Init(TSB_DA_TypeDef * DACx, DAC_InitTypeDef * InitStruct) { uint32_t tmp = 0U; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(DACx)); assert_param(IS_POINTER_NOT_NULL(InitStruct)); assert_param(IS_DAC_CLEAR(InitStruct->DACClear)); assert_param(IS_DAC_ADJTIME(InitStruct->PostTime)); assert_param(IS_DAC_ADJTIME(InitStruct->PreTime)); assert_param(IS_DAC_OFFSET(InitStruct->Offset)); assert_param(IS_DAC_AMPSEL(InitStruct->AmpSel)); assert_param(IS_DAC_TRGSEL(InitStruct->TrgSel)); assert_param(IS_DAC_TRGFUNC(InitStruct->TrgFunc)); assert_param(IS_DAC_DMAFUNC(InitStruct->DMAFunc)); assert_param(IS_DAC_WAVE(InitStruct->Wave)); /*Clear DAC */ tmp = DACx->TCTL; tmp &= DAC_CLEAR_MASK; tmp |= InitStruct->DACClear; DACx->TCTL = tmp; /*Set time to VOUTHOLD adjustment register */ tmp = (uint8_t) (InitStruct->PostTime << 4U); tmp += InitStruct->PreTime; DACx->VCTL = tmp; /*set DACDCTLx(output control register) */ tmp = (uint8_t) (InitStruct->Offset << 18U); tmp += (uint8_t) (InitStruct->AmpSel << 16U); tmp += (uint8_t) (InitStruct->TrgSel << 9U); tmp += (uint8_t) (InitStruct->TrgFunc << 8U); tmp += (uint8_t) (InitStruct->DMAFunc << 7U); tmp += (uint8_t) (InitStruct->Wave); DACx->DCTL = tmp; }
/** * @brief Enables or disables the specified DAC interrupts. * @param DAC_Channel : the selected DAC channel from * @ref DAC_Channel_TypeDef enumeration. * @param DAC_IT : the selected DAC interrupt from * @ref DAC_IT_TypeDef enumeration. * @param NewState : new state of the DAC interrupt . * This parameter can be: ENABLE or DISABLE. * @retval None */ void DAC_ITConfig(DAC_Channel_TypeDef DAC_Channel, DAC_IT_TypeDef DAC_IT, FunctionalState NewState) { uint16_t cr2addr = 0; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(DAC_Channel)); assert_param(IS_FUNCTIONAL_STATE(NewState)); assert_param(IS_DAC_IT(DAC_IT)); /* Find CHxCR2 register Address */ cr2addr = DAC_BASE + CR2_Offset + (uint8_t)((uint8_t)DAC_Channel << 1); if (NewState != DISABLE) { /* Enable the selected DAC interrupts */ (*(uint8_t*)(cr2addr)) |= (uint8_t)(DAC_IT); } else { /* Disable the selected DAC interrupts */ (*(uint8_t*)(cr2addr)) &= (uint8_t)(~(DAC_IT)); } }
/** * @brief Enables or disables the selected DAC channel wave generation. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC1 Channel1 selected * @arg DAC_CHANNEL_2: DAC1 Channel2 selected * @param Amplitude: Select max triangle amplitude. * This parameter can be one of the following values: * @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1 * @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3 * @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7 * @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15 * @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31 * @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63 * @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127 * @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255 * @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511 * @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023 * @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047 * @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095 * @note Wave generation is not available in DAC2. * @retval HAL status */ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t channel, uint32_t Amplitude) { /* Check the parameters */ assert_param(IS_DAC_CHANNEL(channel)); assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude)); /* Process locked */ __HAL_LOCK(hdac); /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; /* Enable the selected wave generation for the selected DAC channel */ hdac->Instance->CR |= (DAC_WAVE_TRIANGLE | Amplitude) << channel; /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hdac); /* Return function status */ return HAL_OK; }
/** * @brief Enables or disables the selected DAC channel wave generation. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (STM32L07x/STM32L08x only) * @param Amplitude: Unmask DAC channel LFSR for noise wave generation. * This parameter can be one of the following values: * @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation * @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation * @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation * @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation * @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation * @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation * @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation * @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation * @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation * @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation * @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation * @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation * @retval HAL status */ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude) { /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude)); /* Process locked */ __HAL_LOCK(hdac); /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; /* Enable the noise wave generation for the selected DAC channel */ MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<<Channel, (DAC_CR_WAVE1_0 | Amplitude) << Channel); /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hdac); /* Return function status */ return HAL_OK; }
/** * @brief Enables DAC and starts conversion of channel. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected * @param pData: The destination peripheral Buffer address. * @param Length: The length of data to be transferred from memory to DAC peripheral * @param Alignment: Specifies the data alignment for DAC channel. * This parameter can be one of the following values: * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_DAC_ALIGN(Alignment)); /* Process locked */ __HAL_LOCK(hdac); /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; if(Channel == DAC_CHANNEL_1) { /* Set the DMA transfer complete callback for channel1 */ hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1; /* Set the DMA half transfer complete callback for channel1 */ hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1; /* Set the DMA error callback for channel1 */ hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1; /* Enable the selected DAC channel1 DMA request */ hdac->Instance->CR |= DAC_CR_DMAEN1; /* Case of use of channel 1 */ switch(Alignment) { case DAC_ALIGN_12B_R: /* Get DHR12R1 address */ tmpreg = (uint32_t)&hdac->Instance->DHR12R1; break; case DAC_ALIGN_12B_L: /* Get DHR12L1 address */ tmpreg = (uint32_t)&hdac->Instance->DHR12L1; break; case DAC_ALIGN_8B_R: /* Get DHR8R1 address */ tmpreg = (uint32_t)&hdac->Instance->DHR8R1; break; default: break; } } else { /* Set the DMA transfer complete callback for channel2 */ hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2; /* Set the DMA half transfer complete callback for channel2 */ hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2; /* Set the DMA error callback for channel2 */ hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2; /* Enable the selected DAC channel2 DMA request */ hdac->Instance->CR |= DAC_CR_DMAEN2; /* Case of use of channel 2 */ switch(Alignment) { case DAC_ALIGN_12B_R: /* Get DHR12R2 address */ tmpreg = (uint32_t)&hdac->Instance->DHR12R2; break; case DAC_ALIGN_12B_L: /* Get DHR12L2 address */ tmpreg = (uint32_t)&hdac->Instance->DHR12L2; break; case DAC_ALIGN_8B_R: /* Get DHR8R2 address */ tmpreg = (uint32_t)&hdac->Instance->DHR8R2; break; default: break; } } /* Enable the DMA Stream */ if(Channel == DAC_CHANNEL_1) { /* Enable the DAC DMA underrun interrupt */ __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1); /* Enable the DMA Stream */ HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length); } else { /* Enable the DAC DMA underrun interrupt */ __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2); /* Enable the DMA Stream */ HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length); } /* Enable the Peripheral */ __HAL_DAC_ENABLE(hdac, Channel); /* Process Unlocked */ __HAL_UNLOCK(hdac); /* Return function status */ return HAL_OK; }
/** * @brief Stop the operation of the specified DAC channel. * @param DACx: Select the DAC channel. * This parameter can be one of the following values: * TSB_DA0, TSB_DA1 * @retval None */ void DAC_Stop(TSB_DA_TypeDef * DACx) { assert_param(IS_DAC_CHANNEL(DACx)); DACx->CNT = DAC_STOP; }
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel) { uint32_t tmpreg1 = 0U, tmpreg2 = 0U; /* Check the DAC parameters */ assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger)); #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) if ((hdac->Instance == DAC1) && (Channel == DAC_CHANNEL_1)) { /* Output Buffer (BOFF1) control */ assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer)); } else /* DAC1 channel 2U & DAC2 channel 1U */ { /* Output Switch (OUTEN) control */ assert_param(IS_DAC_OUTPUT_SWITCH_STATE(sConfig->DAC_OutputSwitch)); } #else assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer)); #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ assert_param(IS_DAC_CHANNEL(Channel)); /* Process locked */ __HAL_LOCK(hdac); /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; /* Get the DAC CR value */ tmpreg1 = hdac->Instance->CR; /* Clear BOFFx-OUTENx, TENx, TSELx, WAVEx and MAMPx bits */ /* Configure for the selected DAC channel: buffer output or switch output, trigger */ /* Set TSELx and TENx bits according to DAC_Trigger value */ /* Set BOFFx bit according to DAC_OutputBuffer value OR */ /* Set OUTEN bit according to DAC_OutputSwitch value */ #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) if ((hdac->Instance == DAC1) && (Channel == DAC_CHANNEL_1)) { /* Output Buffer (BOFF1) control */ tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel); tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer); } else /* DAC1 channel 2U & DAC2 channel 1U */ { /* Output Switch (OUTEN) control */ tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_OUTEN1)) << Channel); tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputSwitch); } #else tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel); tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer); #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* Calculate CR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << Channel; /* Write to DAC CR */ hdac->Instance->CR = tmpreg1; /* Disable wave generation */ hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel); /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hdac); /* Return function status */ return HAL_OK; }
/** * @brief Start the operation of the specified DAC channel. * @param DACx: Select the DAC channel. * This parameter can be one of the following values: * TSB_DA0, TSB_DA1 * @retval None */ void DAC_Start(TSB_DA_TypeDef * DACx) { assert_param(IS_DAC_CHANNEL(DACx)); DACx->CNT = DAC_START; }
/** * @brief Configures the selected DAC channel. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param sConfig: DAC configuration structure. * @param Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel) { uint32_t tmpreg1 = 0, tmpreg2 = 0; uint32_t tickstart = 0; /* Check the DAC parameters */ assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger)); assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer)); assert_param(IS_DAC_CHIP_CONNECTION(sConfig->DAC_ConnectOnChipPeripheral)); assert_param(IS_DAC_TRIMMING(sConfig->DAC_UserTrimming)); if ((sConfig->DAC_UserTrimming) == DAC_TRIMMING_USER) { assert_param(IS_DAC_TRIMMINGVALUE(sConfig->DAC_TrimmingValue)); } assert_param(IS_DAC_SAMPLEANDHOLD(sConfig->DAC_SampleAndHold)); if ((sConfig->DAC_SampleAndHold) == DAC_SAMPLEANDHOLD_ENABLE) { assert_param(IS_DAC_SAMPLETIME(sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime)); assert_param(IS_DAC_HOLDTIME(sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime)); assert_param(IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime)); } assert_param(IS_DAC_CHANNEL(Channel)); /* Process locked */ __HAL_LOCK(hdac); /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; if(sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE) /* Sample on old configuration */ { /* SampleTime */ if (Channel == DAC_CHANNEL_1) { /* Get timeout */ tickstart = HAL_GetTick(); /* SHSR1 can be written when BWST1 equals RESET */ while (((hdac->Instance->SR) & DAC_SR_BWST1)!= RESET) { /* Check for the Timeout */ if((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) { /* Update error code */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); /* Change the DMA state */ hdac->State = HAL_DAC_STATE_TIMEOUT; return HAL_TIMEOUT; } } HAL_Delay(1); hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; } else /* Channel 2 */ { /* SHSR2 can be written when BWST2 equals RESET */ while (((hdac->Instance->SR) & DAC_SR_BWST2)!= RESET) { /* Check for the Timeout */ if((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) { /* Update error code */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); /* Change the DMA state */ hdac->State = HAL_DAC_STATE_TIMEOUT; return HAL_TIMEOUT; } } HAL_Delay(1); hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; } /* HoldTime */ hdac->Instance->SHHR = (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime)<<Channel; /* RefreshTime */ hdac->Instance->SHRR = (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime)<<Channel; } if(sConfig->DAC_UserTrimming == DAC_TRIMMING_USER) /* USER TRIMMING */ { /* Get the DAC CCR value */ tmpreg1 = hdac->Instance->CCR; /* Clear trimming value */ tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << Channel); /* Configure for the selected trimming offset */ tmpreg2 = sConfig->DAC_TrimmingValue; /* Calculate CCR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << Channel; /* Write to DAC CCR */ hdac->Instance->CCR = tmpreg1; } /* else factory trimming is used (factory setting are available at reset)*/ /* SW Nothing has nothing to do */ /* Get the DAC MCR value */ tmpreg1 = hdac->Instance->MCR; /* Clear DAC_MCR_MODE2_0, DAC_MCR_MODE2_1 and DAC_MCR_MODE2_2 bits */ tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << Channel); /* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */ tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | sConfig->DAC_ConnectOnChipPeripheral); /* Calculate MCR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << Channel; /* Write to DAC MCR */ hdac->Instance->MCR = tmpreg1; /* DAC in normal operating mode hence clear DAC_CR_CENx bit */ CLEAR_BIT (hdac->Instance->CR, DAC_CR_CEN1 << Channel); /* Get the DAC CR value */ tmpreg1 = hdac->Instance->CR; /* Clear TENx, TSELx, WAVEx and MAMPx bits */ tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << Channel); /* Configure for the selected DAC channel: trigger */ /* Set TSELx and TENx bits according to DAC_Trigger value */ tmpreg2 = (sConfig->DAC_Trigger); /* Calculate CR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << Channel; /* Write to DAC CR */ hdac->Instance->CR = tmpreg1; /* Disable wave generation */ hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel); /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hdac); /* Return function status */ return HAL_OK; }