void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
{
struct drm_i915_private *dev_priv = dev->dev_private;
unsigned long irqflags;
if (del_timer_sync(&dev_priv->uncore.force_wake_timer))
gen6_force_wake_timer((unsigned long)dev_priv);
/* Hold uncore.lock across reset to prevent any register access
* with forcewake not set correctly
*/
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
if (IS_VALLEYVIEW(dev))
vlv_force_wake_reset(dev_priv);
else if (IS_GEN6(dev) || IS_GEN7(dev))
__gen6_gt_force_wake_reset(dev_priv);
if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev))
__gen7_gt_force_wake_mt_reset(dev_priv);
if (IS_GEN9(dev))
__gen9_gt_force_wake_mt_reset(dev_priv);
if (restore) { /* If reset with a user forcewake, try to restore */
unsigned fw = 0;
if (IS_VALLEYVIEW(dev)) {
if (dev_priv->uncore.fw_rendercount)
fw |= FORCEWAKE_RENDER;
if (dev_priv->uncore.fw_mediacount)
fw |= FORCEWAKE_MEDIA;
} else if (IS_GEN9(dev)) {
if (dev_priv->uncore.fw_rendercount)
fw |= FORCEWAKE_RENDER;
if (dev_priv->uncore.fw_mediacount)
fw |= FORCEWAKE_MEDIA;
if (dev_priv->uncore.fw_blittercount)
fw |= FORCEWAKE_BLITTER;
} else {
if (dev_priv->uncore.forcewake_count)
fw = FORCEWAKE_ALL;
}
if (fw)
dev_priv->uncore.funcs.force_wake_get(dev_priv, fw);
if (IS_GEN6(dev) || IS_GEN7(dev))
dev_priv->uncore.fifo_count =
__raw_i915_read32(dev_priv, GTFIFOCTL) &
GT_FIFO_FREE_ENTRIES_MASK;
}
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}
void intel_uncore_early_sanitize(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
if (HAS_FPGA_DBG_UNCLAIMED(dev))
__raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
if (IS_HASWELL(dev) &&
(__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) == 1)) {
/* The docs do not explain exactly how the calculation can be
* made. It is somewhat guessable, but for now, it's always
* 128MB.
* NB: We can't write IDICR yet because we do not have gt funcs
* set up */
dev_priv->ellc_size = 128;
DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size);
}
/* clear out old GT FIFO errors */
if (IS_GEN6(dev) || IS_GEN7(dev))
__raw_i915_write32(dev_priv, GTFIFODBG,
__raw_i915_read32(dev_priv, GTFIFODBG));
intel_uncore_forcewake_reset(dev);
}
static inline int
mi_set_context(struct intel_ring_buffer *ring,
struct i915_hw_context *new_context,
u32 hw_flags)
{
int ret;
/* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB
* invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value
* explicitly, so we rely on the value at ring init, stored in
* itlb_before_ctx_switch.
*/
if (IS_GEN6(ring->dev) && ring->itlb_before_ctx_switch) {
ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, 0);
if (ret)
return ret;
}
ret = intel_ring_begin(ring, 6);
if (ret)
return ret;
/* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw */
if (IS_GEN7(ring->dev))
intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE);
else
intel_ring_emit(ring, MI_NOOP);
intel_ring_emit(ring, MI_NOOP);
intel_ring_emit(ring, MI_SET_CONTEXT);
intel_ring_emit(ring, new_context->obj->gtt_offset |
MI_MM_SPACE_GTT |
MI_SAVE_EXT_STATE_EN |
MI_RESTORE_EXT_STATE_EN |
hw_flags);
/* w/a: MI_SET_CONTEXT must always be followed by MI_NOOP */
intel_ring_emit(ring, MI_NOOP);
if (IS_GEN7(ring->dev))
intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE);
else
intel_ring_emit(ring, MI_NOOP);
intel_ring_advance(ring);
return ret;
}
static void __gen7_gt_force_wake_mt_put(struct drm_i915_private *dev_priv,
int fw_engine)
{
__raw_i915_write32(dev_priv, FORCEWAKE_MT,
_MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
/* something from same cacheline, but !FORCEWAKE_MT */
__raw_posting_read(dev_priv, ECOBUS);
if (IS_GEN7(dev_priv->dev))
gen6_gt_check_fifodbg(dev_priv);
}
media_fillfunc_t get_media_fillfunc(int devid)
{
media_fillfunc_t fill = NULL;
if (IS_GEN8(devid))
fill = gen8_media_fillfunc;
else if (IS_GEN7(devid))
fill = gen7_media_fillfunc;
else if (IS_GEN9(devid))
fill = gen9_media_fillfunc;
return fill;
}
int
intel_plane_init(struct drm_device *dev, enum pipe pipe)
{
struct intel_plane *intel_plane;
unsigned long possible_crtcs;
int ret;
if (!(IS_GEN6(dev) || IS_GEN7(dev)))
return -ENODEV;
intel_plane = kzalloc(sizeof(struct intel_plane), GFP_KERNEL);
if (!intel_plane)
return -ENOMEM;
if (IS_GEN6(dev)) {
intel_plane->max_downscale = 16;
intel_plane->update_plane = snb_update_plane;
intel_plane->disable_plane = snb_disable_plane;
intel_plane->update_colorkey = snb_update_colorkey;
intel_plane->get_colorkey = snb_get_colorkey;
} else if (IS_GEN7(dev)) {
intel_plane->max_downscale = 2;
intel_plane->update_plane = ivb_update_plane;
intel_plane->disable_plane = ivb_disable_plane;
intel_plane->update_colorkey = ivb_update_colorkey;
intel_plane->get_colorkey = ivb_get_colorkey;
}
intel_plane->pipe = pipe;
possible_crtcs = (1 << pipe);
ret = drm_plane_init(dev, &intel_plane->base, possible_crtcs,
&intel_plane_funcs, snb_plane_formats,
ARRAY_SIZE(snb_plane_formats), false);
if (ret)
kfree(intel_plane);
return ret;
}
int
intel_plane_init(struct drm_device *dev, enum i915_pipe pipe)
{
struct intel_plane *intel_plane;
unsigned long possible_crtcs;
int ret;
if (!(IS_GEN6(dev) || IS_GEN7(dev)))
return -ENODEV;
intel_plane = kmalloc(sizeof(struct intel_plane), DRM_MEM_KMS,
M_WAITOK | M_ZERO);
if (IS_GEN6(dev)) {
intel_plane->max_downscale = 16;
intel_plane->update_plane = snb_update_plane;
intel_plane->disable_plane = snb_disable_plane;
intel_plane->update_colorkey = snb_update_colorkey;
intel_plane->get_colorkey = snb_get_colorkey;
} else if (IS_GEN7(dev)) {
intel_plane->max_downscale = 2;
intel_plane->update_plane = ivb_update_plane;
intel_plane->disable_plane = ivb_disable_plane;
intel_plane->update_colorkey = ivb_update_colorkey;
intel_plane->get_colorkey = ivb_get_colorkey;
}
intel_plane->pipe = pipe;
possible_crtcs = (1 << pipe);
ret = drm_plane_init(dev, &intel_plane->base, possible_crtcs,
&intel_plane_funcs, snb_plane_formats,
DRM_ARRAY_SIZE(snb_plane_formats), false);
if (ret)
drm_free(intel_plane, DRM_MEM_KMS);
return ret;
}
static void emit_blt(drm_intel_bo *src_bo, uint32_t src_tiling, unsigned src_pitch,
unsigned src_x, unsigned src_y, unsigned w, unsigned h,
drm_intel_bo *dst_bo, uint32_t dst_tiling, unsigned dst_pitch,
unsigned dst_x, unsigned dst_y)
{
uint32_t cmd_bits = 0;
if (IS_965(devid) && src_tiling) {
src_pitch /= 4;
cmd_bits |= XY_SRC_COPY_BLT_SRC_TILED;
}
if (IS_965(devid) && dst_tiling) {
dst_pitch /= 4;
cmd_bits |= XY_SRC_COPY_BLT_DST_TILED;
}
/* copy lower half to upper half */
BEGIN_BATCH(8);
OUT_BATCH(XY_SRC_COPY_BLT_CMD |
XY_SRC_COPY_BLT_WRITE_ALPHA |
XY_SRC_COPY_BLT_WRITE_RGB |
cmd_bits);
OUT_BATCH((3 << 24) | /* 32 bits */
(0xcc << 16) | /* copy ROP */
dst_pitch);
OUT_BATCH(dst_y << 16 | dst_x);
OUT_BATCH((dst_y+h) << 16 | (dst_x+w));
OUT_RELOC_FENCED(dst_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
OUT_BATCH(src_y << 16 | src_x);
OUT_BATCH(src_pitch);
OUT_RELOC_FENCED(src_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
ADVANCE_BATCH();
if (IS_GEN6(devid) || IS_GEN7(devid)) {
BEGIN_BATCH(3);
OUT_BATCH(XY_SETUP_CLIP_BLT_CMD);
OUT_BATCH(0);
OUT_BATCH(0);
ADVANCE_BATCH();
}
}
static void
intel_driver_init(intel_driver_t *driver, int dev_fd)
{
driver->fd = dev_fd;
driver->locked = 0;
pthread_mutex_init(&driver->ctxmutex, NULL);
#ifndef NDEBUG
int res =
#endif /* NDEBUG */
intel_driver_get_param(driver, I915_PARAM_CHIPSET_ID, &driver->device_id);
assert(res);
intel_driver_memman_init(driver);
#if EMULATE_GEN
driver->gen_ver = EMULATE_GEN;
if (EMULATE_GEN == 75)
driver->device_id = PCI_CHIP_HASWELL_L; /* we pick L for HSW */
else if (EMULATE_GEN == 7)
driver->device_id = PCI_CHIP_IVYBRIDGE_GT2; /* we pick GT2 for IVB */
else if (EMULATE_GEN == 6)
driver->device_id = PCI_CHIP_SANDYBRIDGE_GT2; /* we pick GT2 for SNB */
else
FATAL ("Unsupported Gen for emulation");
#else
if (IS_GEN75(driver->device_id))
driver->gen_ver = 75;
else if (IS_GEN7(driver->device_id))
driver->gen_ver = 7;
else if (IS_GEN6(driver->device_id))
driver->gen_ver = 6;
else if(IS_IGDNG(driver->device_id))
driver->gen_ver = 5;
else
driver->gen_ver = 4;
#endif /* EMULATE_GEN */
}
BOOL
media_driver_data_init (VADriverContextP ctx)
{
MEDIA_DRV_CONTEXT *drv_ctx = NULL;
MEDIA_DRV_ASSERT (ctx);
drv_ctx = ctx->pDriverData;
if (IS_GEN75 (drv_ctx->drv_data.device_id))
drv_ctx->codec_info = &gen75_hw_codec_info;
else if (IS_GEN7 (drv_ctx->drv_data.device_id))
drv_ctx->codec_info = &gen7_hw_codec_info;
else if (IS_GEN8(drv_ctx->drv_data.device_id))
drv_ctx->codec_info = &gen8_hw_codec_info;
else if (IS_CHERRYVIEW(drv_ctx->drv_data.device_id))
drv_ctx->codec_info = &chv_hw_codec_info;
else
return false;
if (object_heap_init (&drv_ctx->config_heap,
sizeof (struct object_config), CONFIG_ID_OFFSET))
goto err_config_heap;
if (object_heap_init (&drv_ctx->context_heap,
sizeof (struct object_context), CONTEXT_ID_OFFSET))
goto err_context_heap;
if (object_heap_init (&drv_ctx->surface_heap,
sizeof (struct object_surface), SURFACE_ID_OFFSET))
goto err_surface_heap;
if (object_heap_init (&drv_ctx->buffer_heap,
sizeof (struct object_buffer), BUFFER_ID_OFFSET))
goto err_buffer_heap;
if (object_heap_init (&drv_ctx->image_heap,
sizeof (struct object_image), IMAGE_ID_OFFSET))
goto err_image_heap;
if (object_heap_init (&drv_ctx->subpic_heap,
sizeof (struct object_subpic), IMAGE_ID_OFFSET))
goto err_subpic_heap;
drv_ctx->batch =
media_batchbuffer_new (&drv_ctx->drv_data, I915_EXEC_RENDER, 0);
drv_ctx->pp_batch =
media_batchbuffer_new (&drv_ctx->drv_data, I915_EXEC_RENDER, 0);
drv_ctx->render_batch =
media_batchbuffer_new (&drv_ctx->drv_data, I915_EXEC_RENDER, 0);
media_drv_mutex_init (&drv_ctx->render_mutex);
media_drv_mutex_init (&drv_ctx->pp_mutex);
return true;
err_subpic_heap:
object_heap_destroy(&drv_ctx->subpic_heap);
err_image_heap:
object_heap_destroy (&drv_ctx->buffer_heap);
err_buffer_heap:
object_heap_destroy (&drv_ctx->surface_heap);
err_surface_heap:
object_heap_destroy (&drv_ctx->context_heap);
err_context_heap:
object_heap_destroy (&drv_ctx->config_heap);
err_config_heap:
return false;
}
void
intel_batchbuffer_emit_mi_flush(struct intel_batchbuffer *batch)
{
struct intel_driver_data *intel = batch->intel;
if (IS_GEN6(intel->device_info) ||
IS_GEN7(intel->device_info) ||
IS_GEN8(intel->device_info)) {
if (batch->flag == I915_EXEC_RENDER) {
if (IS_GEN8(intel->device_info)) {
BEGIN_BATCH(batch, 6);
OUT_BATCH(batch, CMD_PIPE_CONTROL | (6 - 2));
OUT_BATCH(batch,
CMD_PIPE_CONTROL_CS_STALL |
CMD_PIPE_CONTROL_WC_FLUSH |
CMD_PIPE_CONTROL_TC_FLUSH |
CMD_PIPE_CONTROL_DC_FLUSH |
CMD_PIPE_CONTROL_NOWRITE);
OUT_BATCH(batch, 0); /* write address */
OUT_BATCH(batch, 0);
OUT_BATCH(batch, 0); /* write data */
OUT_BATCH(batch, 0);
ADVANCE_BATCH(batch);
} else if (IS_GEN6(intel->device_info)) {
assert(batch->wa_render_bo);
BEGIN_BATCH(batch, 4 * 3);
OUT_BATCH(batch, CMD_PIPE_CONTROL | (4 - 2));
OUT_BATCH(batch,
CMD_PIPE_CONTROL_CS_STALL |
CMD_PIPE_CONTROL_STALL_AT_SCOREBOARD);
OUT_BATCH(batch, 0); /* address */
OUT_BATCH(batch, 0); /* write data */
OUT_BATCH(batch, CMD_PIPE_CONTROL | (4 - 2));
OUT_BATCH(batch, CMD_PIPE_CONTROL_WRITE_QWORD);
OUT_RELOC(batch,
batch->wa_render_bo,
I915_GEM_DOMAIN_INSTRUCTION,
I915_GEM_DOMAIN_INSTRUCTION,
0);
OUT_BATCH(batch, 0); /* write data */
/* now finally the _real flush */
OUT_BATCH(batch, CMD_PIPE_CONTROL | (4 - 2));
OUT_BATCH(batch,
CMD_PIPE_CONTROL_WC_FLUSH |
CMD_PIPE_CONTROL_TC_FLUSH |
CMD_PIPE_CONTROL_NOWRITE);
OUT_BATCH(batch, 0); /* write address */
OUT_BATCH(batch, 0); /* write data */
ADVANCE_BATCH(batch);
} else {
BEGIN_BATCH(batch, 4);
OUT_BATCH(batch, CMD_PIPE_CONTROL | (4 - 2));
OUT_BATCH(batch,
CMD_PIPE_CONTROL_WC_FLUSH |
CMD_PIPE_CONTROL_TC_FLUSH |
CMD_PIPE_CONTROL_DC_FLUSH |
CMD_PIPE_CONTROL_NOWRITE);
OUT_BATCH(batch, 0); /* write address */
OUT_BATCH(batch, 0); /* write data */
ADVANCE_BATCH(batch);
}
} else {
if (batch->flag == I915_EXEC_BLT) {
BEGIN_BLT_BATCH(batch, 4);
OUT_BLT_BATCH(batch, MI_FLUSH_DW);
OUT_BLT_BATCH(batch, 0);
OUT_BLT_BATCH(batch, 0);
OUT_BLT_BATCH(batch, 0);
ADVANCE_BLT_BATCH(batch);
}else if (batch->flag == I915_EXEC_VEBOX) {
BEGIN_VEB_BATCH(batch, 4);
OUT_VEB_BATCH(batch, MI_FLUSH_DW);
OUT_VEB_BATCH(batch, 0);
OUT_VEB_BATCH(batch, 0);
OUT_VEB_BATCH(batch, 0);
ADVANCE_VEB_BATCH(batch);
} else {
assert(batch->flag == I915_EXEC_BSD);
BEGIN_BCS_BATCH(batch, 4);
OUT_BCS_BATCH(batch, MI_FLUSH_DW | MI_FLUSH_DW_VIDEO_PIPELINE_CACHE_INVALIDATE);
OUT_BCS_BATCH(batch, 0);
OUT_BCS_BATCH(batch, 0);
OUT_BCS_BATCH(batch, 0);
ADVANCE_BCS_BATCH(batch);
}
}
} else {
if (batch->flag == I915_EXEC_RENDER) {
BEGIN_BATCH(batch, 1);
OUT_BATCH(batch, MI_FLUSH | MI_FLUSH_STATE_INSTRUCTION_CACHE_INVALIDATE);
ADVANCE_BATCH(batch);
} else {
assert(batch->flag == I915_EXEC_BSD);
BEGIN_BCS_BATCH(batch, 1);
OUT_BCS_BATCH(batch, MI_FLUSH | MI_FLUSH_STATE_INSTRUCTION_CACHE_INVALIDATE);
ADVANCE_BCS_BATCH(batch);
}
}
}
static inline int
mi_set_context(struct intel_ring_buffer *ring,
struct i915_hw_context *new_context,
u32 hw_flags)
{
int ret;
u32 flags = 0;
u32 scratch_addr = get_pipe_control_scratch_addr(ring) + 128;
/* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB
* invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value
* explicitly, so we rely on the value at ring init, stored in
* itlb_before_ctx_switch.
*/
if (IS_GEN6(ring->dev) && ring->itlb_before_ctx_switch) {
ret = ring->flush(ring, 0, 0);
if (ret)
return ret;
}
if (IS_GEN7(ring->dev))
ret = intel_ring_begin(ring, 6+4+7);
else
ret = intel_ring_begin(ring, 6);
if (ret)
return ret;
if (IS_GEN7(ring->dev))
intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE);
else
intel_ring_emit(ring, MI_NOOP);
intel_ring_emit(ring, MI_NOOP);
intel_ring_emit(ring, MI_SET_CONTEXT);
intel_ring_emit(ring, new_context->obj->gtt_offset |
MI_MM_SPACE_GTT |
MI_SAVE_EXT_STATE_EN |
MI_RESTORE_EXT_STATE_EN |
hw_flags);
/* w/a: MI_SET_CONTEXT must always be followed by MI_NOOP */
intel_ring_emit(ring, MI_NOOP);
if (IS_GEN7(ring->dev)) {
/* WaSendDummy3dPrimitveAfterSetContext */
/* Software must send a pipe_control with a CS stall
and a post sync operation and then a dummy DRAW after
every MI_SET_CONTEXT and after any PIPELINE_SELECT that
is enabling 3D mode. A dummy draw is a 3DPRIMITIVE command
with Indirect Parameter Enable set to 0, UAV Coherency
Required set to 0, Predicate Enable set to 0,
End Offset Enable set to 0, and Vertex Count Per Instance
set to 0, All other parameters are a don't care */
/* Send pipe control with CS Stall and postsync op
before 3D_PRIMITIVE */
flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
intel_ring_emit(ring, flags);
intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
intel_ring_emit(ring, 0);
/* Send a dummy 3D_PRIMITVE */
intel_ring_emit(ring, GFX_OP_3DPRIMITIVE());
intel_ring_emit(ring, 4); /* PrimTopoType*/
intel_ring_emit(ring, 0); /* VertexCountPerInstance */
intel_ring_emit(ring, 0); /* StartVertexLocation */
intel_ring_emit(ring, 0); /* InstanceCount */
intel_ring_emit(ring, 0); /* StartInstanceLocation */
intel_ring_emit(ring, 0); /* BaseVertexLocation */
}
if (IS_GEN7(ring->dev))
intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE);
else
intel_ring_emit(ring, MI_NOOP);
intel_ring_advance(ring);
i915_add_request_noflush(ring);
return ret;
}
static bool
init_dev(struct ilo_dev_info *dev, const struct intel_winsys_info *info)
{
dev->devid = info->devid;
dev->has_llc = info->has_llc;
dev->has_gen7_sol_reset = info->has_gen7_sol_reset;
dev->has_address_swizzling = info->has_address_swizzling;
/*
* From the Sandy Bridge PRM, volume 4 part 2, page 18:
*
* "[DevSNB]: The GT1 product's URB provides 32KB of storage, arranged
* as 1024 256-bit rows. The GT2 product's URB provides 64KB of
* storage, arranged as 2048 256-bit rows. A row corresponds in size
* to an EU GRF register. Read/write access to the URB is generally
* supported on a row-granular basis."
*
* From the Ivy Bridge PRM, volume 4 part 2, page 17:
*
* "URB Size URB Rows URB Rows when SLM Enabled
* 128k 4096 2048
* 256k 8096 4096"
*/
if (IS_HASWELL(info->devid)) {
dev->gen = ILO_GEN(7.5);
if (IS_HSW_GT3(info->devid)) {
dev->gt = 3;
dev->urb_size = 512 * 1024;
}
else if (IS_HSW_GT2(info->devid)) {
dev->gt = 2;
dev->urb_size = 256 * 1024;
}
else {
dev->gt = 1;
dev->urb_size = 128 * 1024;
}
}
else if (IS_GEN7(info->devid)) {
dev->gen = ILO_GEN(7);
if (IS_IVB_GT2(info->devid)) {
dev->gt = 2;
dev->urb_size = 256 * 1024;
}
else {
dev->gt = 1;
dev->urb_size = 128 * 1024;
}
}
else if (IS_GEN6(info->devid)) {
dev->gen = ILO_GEN(6);
if (IS_SNB_GT2(info->devid)) {
dev->gt = 2;
dev->urb_size = 64 * 1024;
}
else {
dev->gt = 1;
dev->urb_size = 32 * 1024;
}
}
else {
ilo_err("unknown GPU generation\n");
return false;
}
return true;
}
void
init_instdone_definitions(uint32_t devid)
{
if (IS_GEN7(devid)) {
init_gen7_instdone();
} else if (IS_GEN6(devid)) {
/* Now called INSTDONE_1 in the docs. */
gen6_instdone1_bit(GEN6_MA_3_DONE, "Message Arbiter 3");
gen6_instdone1_bit(GEN6_EU_32_DONE, "EU 32");
gen6_instdone1_bit(GEN6_EU_31_DONE, "EU 31");
gen6_instdone1_bit(GEN6_EU_30_DONE, "EU 30");
gen6_instdone1_bit(GEN6_MA_3_DONE, "Message Arbiter 2");
gen6_instdone1_bit(GEN6_EU_22_DONE, "EU 22");
gen6_instdone1_bit(GEN6_EU_21_DONE, "EU 21");
gen6_instdone1_bit(GEN6_EU_20_DONE, "EU 20");
gen6_instdone1_bit(GEN6_MA_3_DONE, "Message Arbiter 1");
gen6_instdone1_bit(GEN6_EU_12_DONE, "EU 12");
gen6_instdone1_bit(GEN6_EU_11_DONE, "EU 11");
gen6_instdone1_bit(GEN6_EU_10_DONE, "EU 10");
gen6_instdone1_bit(GEN6_MA_3_DONE, "Message Arbiter 0");
gen6_instdone1_bit(GEN6_EU_02_DONE, "EU 02");
gen6_instdone1_bit(GEN6_EU_01_DONE, "EU 01");
gen6_instdone1_bit(GEN6_EU_00_DONE, "EU 00");
gen6_instdone1_bit(GEN6_IC_3_DONE, "IC 3");
gen6_instdone1_bit(GEN6_IC_2_DONE, "IC 2");
gen6_instdone1_bit(GEN6_IC_1_DONE, "IC 1");
gen6_instdone1_bit(GEN6_IC_0_DONE, "IC 0");
gen6_instdone1_bit(GEN6_ISC_10_DONE, "ISC 1/0");
gen6_instdone1_bit(GEN6_ISC_32_DONE, "ISC 3/2");
gen6_instdone1_bit(GEN6_VSC_DONE, "VSC");
gen6_instdone1_bit(GEN6_IEF_DONE, "IEF");
gen6_instdone1_bit(GEN6_VFE_DONE, "VFE");
gen6_instdone1_bit(GEN6_TD_DONE, "TD");
gen6_instdone1_bit(GEN6_TS_DONE, "TS");
gen6_instdone1_bit(GEN6_GW_DONE, "GW");
gen6_instdone1_bit(GEN6_HIZ_DONE, "HIZ");
gen6_instdone1_bit(GEN6_AVS_DONE, "AVS");
/* Now called INSTDONE_2 in the docs. */
gen6_instdone2_bit(GEN6_GAM_DONE, "GAM");
gen6_instdone2_bit(GEN6_CS_DONE, "CS");
gen6_instdone2_bit(GEN6_WMBE_DONE, "WMBE");
gen6_instdone2_bit(GEN6_SVRW_DONE, "SVRW");
gen6_instdone2_bit(GEN6_RCC_DONE, "RCC");
gen6_instdone2_bit(GEN6_SVG_DONE, "SVG");
gen6_instdone2_bit(GEN6_ISC_DONE, "ISC");
gen6_instdone2_bit(GEN6_MT_DONE, "MT");
gen6_instdone2_bit(GEN6_RCPFE_DONE, "RCPFE");
gen6_instdone2_bit(GEN6_RCPBE_DONE, "RCPBE");
gen6_instdone2_bit(GEN6_VDI_DONE, "VDI");
gen6_instdone2_bit(GEN6_RCZ_DONE, "RCZ");
gen6_instdone2_bit(GEN6_DAP_DONE, "DAP");
gen6_instdone2_bit(GEN6_PSD_DONE, "PSD");
gen6_instdone2_bit(GEN6_IZ_DONE, "IZ");
gen6_instdone2_bit(GEN6_WMFE_DONE, "WMFE");
gen6_instdone2_bit(GEN6_SVSM_DONE, "SVSM");
gen6_instdone2_bit(GEN6_QC_DONE, "QC");
gen6_instdone2_bit(GEN6_FL_DONE, "FL");
gen6_instdone2_bit(GEN6_SC_DONE, "SC");
gen6_instdone2_bit(GEN6_DM_DONE, "DM");
gen6_instdone2_bit(GEN6_FT_DONE, "FT");
gen6_instdone2_bit(GEN6_DG_DONE, "DG");
gen6_instdone2_bit(GEN6_SI_DONE, "SI");
gen6_instdone2_bit(GEN6_SO_DONE, "SO");
gen6_instdone2_bit(GEN6_PL_DONE, "PL");
gen6_instdone2_bit(GEN6_VME_DONE, "VME");
gen6_instdone2_bit(GEN6_SF_DONE, "SF");
gen6_instdone2_bit(GEN6_CL_DONE, "CL");
gen6_instdone2_bit(GEN6_GS_DONE, "GS");
gen6_instdone2_bit(GEN6_VS0_DONE, "VS0");
gen6_instdone2_bit(GEN6_VF_DONE, "VF");
} else if (IS_GEN5(devid)) {
gen4_instdone_bit(ILK_ROW_0_EU_0_DONE, "Row 0, EU 0");
gen4_instdone_bit(ILK_ROW_0_EU_1_DONE, "Row 0, EU 1");
gen4_instdone_bit(ILK_ROW_0_EU_2_DONE, "Row 0, EU 2");
gen4_instdone_bit(ILK_ROW_0_EU_3_DONE, "Row 0, EU 3");
gen4_instdone_bit(ILK_ROW_1_EU_0_DONE, "Row 1, EU 0");
gen4_instdone_bit(ILK_ROW_1_EU_1_DONE, "Row 1, EU 1");
gen4_instdone_bit(ILK_ROW_1_EU_2_DONE, "Row 1, EU 2");
gen4_instdone_bit(ILK_ROW_1_EU_3_DONE, "Row 1, EU 3");
gen4_instdone_bit(ILK_ROW_2_EU_0_DONE, "Row 2, EU 0");
gen4_instdone_bit(ILK_ROW_2_EU_1_DONE, "Row 2, EU 1");
gen4_instdone_bit(ILK_ROW_2_EU_2_DONE, "Row 2, EU 2");
gen4_instdone_bit(ILK_ROW_2_EU_3_DONE, "Row 2, EU 3");
gen4_instdone_bit(ILK_VCP_DONE, "VCP");
gen4_instdone_bit(ILK_ROW_0_MATH_DONE, "Row 0 math");
gen4_instdone_bit(ILK_ROW_1_MATH_DONE, "Row 1 math");
gen4_instdone_bit(ILK_ROW_2_MATH_DONE, "Row 2 math");
gen4_instdone_bit(ILK_VC1_DONE, "VC1");
gen4_instdone_bit(ILK_ROW_0_MA_DONE, "Row 0 MA");
gen4_instdone_bit(ILK_ROW_1_MA_DONE, "Row 1 MA");
gen4_instdone_bit(ILK_ROW_2_MA_DONE, "Row 2 MA");
gen4_instdone_bit(ILK_ROW_0_ISC_DONE, "Row 0 ISC");
gen4_instdone_bit(ILK_ROW_1_ISC_DONE, "Row 1 ISC");
gen4_instdone_bit(ILK_ROW_2_ISC_DONE, "Row 2 ISC");
gen4_instdone_bit(ILK_VFE_DONE, "VFE");
gen4_instdone_bit(ILK_TD_DONE, "TD");
gen4_instdone_bit(ILK_SVTS_DONE, "SVTS");
gen4_instdone_bit(ILK_TS_DONE, "TS");
gen4_instdone_bit(ILK_GW_DONE, "GW");
gen4_instdone_bit(ILK_AI_DONE, "AI");
gen4_instdone_bit(ILK_AC_DONE, "AC");
gen4_instdone_bit(ILK_AM_DONE, "AM");
init_g4x_instdone1();
} else if (IS_GEN4(devid)) {
gen4_instdone_bit(I965_ROW_0_EU_0_DONE, "Row 0, EU 0");
gen4_instdone_bit(I965_ROW_0_EU_1_DONE, "Row 0, EU 1");
gen4_instdone_bit(I965_ROW_0_EU_2_DONE, "Row 0, EU 2");
gen4_instdone_bit(I965_ROW_0_EU_3_DONE, "Row 0, EU 3");
gen4_instdone_bit(I965_ROW_1_EU_0_DONE, "Row 1, EU 0");
gen4_instdone_bit(I965_ROW_1_EU_1_DONE, "Row 1, EU 1");
gen4_instdone_bit(I965_ROW_1_EU_2_DONE, "Row 1, EU 2");
gen4_instdone_bit(I965_ROW_1_EU_3_DONE, "Row 1, EU 3");
gen4_instdone_bit(I965_SF_DONE, "Strips and Fans");
gen4_instdone_bit(I965_SE_DONE, "Setup Engine");
gen4_instdone_bit(I965_WM_DONE, "Windowizer");
gen4_instdone_bit(I965_DISPATCHER_DONE, "Dispatcher");
gen4_instdone_bit(I965_PROJECTION_DONE, "Projection and LOD");
gen4_instdone_bit(I965_DG_DONE, "Dependent address generator");
gen4_instdone_bit(I965_QUAD_CACHE_DONE, "Texture fetch");
gen4_instdone_bit(I965_TEXTURE_FETCH_DONE, "Texture fetch");
gen4_instdone_bit(I965_TEXTURE_DECOMPRESS_DONE, "Texture decompress");
gen4_instdone_bit(I965_SAMPLER_CACHE_DONE, "Sampler cache");
gen4_instdone_bit(I965_FILTER_DONE, "Filtering");
gen4_instdone_bit(I965_BYPASS_DONE, "Bypass FIFO");
gen4_instdone_bit(I965_PS_DONE, "Pixel shader");
gen4_instdone_bit(I965_CC_DONE, "Color calculator");
gen4_instdone_bit(I965_MAP_FILTER_DONE, "Map filter");
gen4_instdone_bit(I965_MAP_L2_IDLE, "Map L2");
gen4_instdone_bit(I965_MA_ROW_0_DONE, "Message Arbiter row 0");
gen4_instdone_bit(I965_MA_ROW_1_DONE, "Message Arbiter row 1");
gen4_instdone_bit(I965_IC_ROW_0_DONE, "Instruction cache row 0");
gen4_instdone_bit(I965_IC_ROW_1_DONE, "Instruction cache row 1");
gen4_instdone_bit(I965_CP_DONE, "Command Processor");
if (IS_G4X(devid)) {
init_g4x_instdone1();
} else {
init_g965_instdone1();
}
} else if (IS_GEN3(devid)) {
gen3_instdone_bit(IDCT_DONE, "IDCT");
gen3_instdone_bit(IQ_DONE, "IQ");
gen3_instdone_bit(PR_DONE, "PR");
gen3_instdone_bit(VLD_DONE, "VLD");
gen3_instdone_bit(IP_DONE, "Instruction parser");
gen3_instdone_bit(FBC_DONE, "Framebuffer Compression");
gen3_instdone_bit(BINNER_DONE, "Binner");
gen3_instdone_bit(SF_DONE, "Strips and fans");
gen3_instdone_bit(SE_DONE, "Setup engine");
gen3_instdone_bit(WM_DONE, "Windowizer");
gen3_instdone_bit(IZ_DONE, "Intermediate Z");
gen3_instdone_bit(PERSPECTIVE_INTERP_DONE, "Perspective interpolation");
gen3_instdone_bit(DISPATCHER_DONE, "Dispatcher");
gen3_instdone_bit(PROJECTION_DONE, "Projection and LOD");
gen3_instdone_bit(DEPENDENT_ADDRESS_DONE, "Dependent address calculation");
gen3_instdone_bit(TEXTURE_FETCH_DONE, "Texture fetch");
gen3_instdone_bit(TEXTURE_DECOMPRESS_DONE, "Texture decompression");
gen3_instdone_bit(SAMPLER_CACHE_DONE, "Sampler Cache");
gen3_instdone_bit(FILTER_DONE, "Filtering");
gen3_instdone_bit(BYPASS_FIFO_DONE, "Bypass FIFO");
gen3_instdone_bit(PS_DONE, "Pixel shader");
gen3_instdone_bit(CC_DONE, "Color calculator");
gen3_instdone_bit(MAP_FILTER_DONE, "Map filter");
gen3_instdone_bit(MAP_L2_IDLE, "Map L2");
} else {
assert(IS_GEN2(devid));
gen3_instdone_bit(I830_GMBUS_DONE, "GMBUS");
gen3_instdone_bit(I830_FBC_DONE, "FBC");
gen3_instdone_bit(I830_BINNER_DONE, "BINNER");
gen3_instdone_bit(I830_MPEG_DONE, "MPEG");
gen3_instdone_bit(I830_MECO_DONE, "MECO");
gen3_instdone_bit(I830_MCD_DONE, "MCD");
gen3_instdone_bit(I830_MCSTP_DONE, "MCSTP");
gen3_instdone_bit(I830_CC_DONE, "CC");
gen3_instdone_bit(I830_DG_DONE, "DG");
gen3_instdone_bit(I830_DCMP_DONE, "DCMP");
gen3_instdone_bit(I830_FTCH_DONE, "FTCH");
gen3_instdone_bit(I830_IT_DONE, "IT");
gen3_instdone_bit(I830_MG_DONE, "MG");
gen3_instdone_bit(I830_MEC_DONE, "MEC");
gen3_instdone_bit(I830_PC_DONE, "PC");
gen3_instdone_bit(I830_QCC_DONE, "QCC");
gen3_instdone_bit(I830_TB_DONE, "TB");
gen3_instdone_bit(I830_WM_DONE, "WM");
gen3_instdone_bit(I830_EF_DONE, "EF");
gen3_instdone_bit(I830_BLITTER_DONE, "Blitter");
gen3_instdone_bit(I830_MAP_L2_DONE, "Map L2 cache");
gen3_instdone_bit(I830_SECONDARY_RING_3_DONE, "Secondary ring 3");
gen3_instdone_bit(I830_SECONDARY_RING_2_DONE, "Secondary ring 2");
gen3_instdone_bit(I830_SECONDARY_RING_1_DONE, "Secondary ring 1");
gen3_instdone_bit(I830_SECONDARY_RING_0_DONE, "Secondary ring 0");
gen3_instdone_bit(I830_PRIMARY_RING_1_DONE, "Primary ring 1");
gen3_instdone_bit(I830_PRIMARY_RING_0_DONE, "Primary ring 0");
}
}
