IMG_BOOL MRSTLFBFlipToSurface(MRSTLFB_DEVINFO *psDevInfo,
unsigned long uiAddr)
{
int dspbase = (psDevInfo->ui32MainPipe == 0 ? DSPABASE : DSPBBASE);
int dspsurf = (psDevInfo->ui32MainPipe == 0 ? DSPASURF : DSPBSURF);
struct drm_device * dev = psDevInfo->psDrmDevice;
struct drm_psb_private *dev_priv =
(struct drm_psb_private *) psDevInfo->psDrmDevice->dev_private;
MRSTLFB_SWAPCHAIN *psCurrentSwapChain = psDevInfo->psCurrentSwapChain;
if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, false))
{
if (IS_MRST(dev)) {
MRSTLFBVSyncWriteReg(psDevInfo, dspsurf, uiAddr);
} else if (IS_MDFLD(dev)) {
if (psCurrentSwapChain != NULL) {
if (psCurrentSwapChain->ui32SwapChainPropertyFlag
& PVRSRV_SWAPCHAIN_ATTACHED_PLANE_A) {
dspsurf = DSPASURF;
MRSTLFBVSyncWriteReg(psDevInfo, dspsurf, uiAddr);
if (dev_priv->b_async_flip_enable &&
dev_priv->async_flip_update_fb)
if (dev_priv->async_flip_update_fb(
dev, 0) == IMG_FALSE)
return IMG_FALSE;
}
#if defined(CONFIG_MDFD_DUAL_MIPI)
if (psCurrentSwapChain->ui32SwapChainPropertyFlag
& PVRSRV_SWAPCHAIN_ATTACHED_PLANE_C) {
dspsurf = DSPCSURF;
MRSTLFBVSyncWriteReg(psDevInfo, dspsurf, uiAddr);
if (dev_priv->b_async_flip_enable &&
dev_priv->async_flip_update_fb)
if (dev_priv->async_flip_update_fb(
dev, 2) == IMG_FALSE)
return IMG_FALSE;
}
#endif
#ifdef CONFIG_MDFD_HDMI
/* To avoid Plane B still fetches data from original frame
* buffer. */
if (psCurrentSwapChain->ui32SwapChainPropertyFlag
& PVRSRV_SWAPCHAIN_ATTACHED_PLANE_B) {
dspsurf = DSPBSURF;
MRSTLFBVSyncWriteReg(psDevInfo, dspsurf, uiAddr);
}
#endif
} else {
printk(KERN_WARNING "Current Swapchain is null, no attached plane info\
available, omit address update\n");
if (drm_psb_debug & PSB_D_GENERAL)
dump_stack();
}
} else {
MRSTLFBVSyncWriteReg(psDevInfo, dspbase, uiAddr);
}
ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
}
static void mid_get_fuse_settings(struct drm_device *dev)
{
struct drm_psb_private *dev_priv = dev->dev_private;
struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
uint32_t fuse_value = 0;
uint32_t fuse_value_tmp = 0;
#define FB_REG06 0xD0810600
#define FB_MIPI_DISABLE (1 << 11)
#define FB_REG09 0xD0810900
#define FB_REG09 0xD0810900
#define FB_SKU_MASK 0x7000
#define FB_SKU_SHIFT 12
#define FB_SKU_100 0
#define FB_SKU_100L 1
#define FB_SKU_83 2
if (pci_root == NULL) {
WARN_ON(1);
return;
}
pci_write_config_dword(pci_root, 0xD0, FB_REG06);
pci_read_config_dword(pci_root, 0xD4, &fuse_value);
/* FB_MIPI_DISABLE doesn't mean LVDS on with Medfield */
if (IS_MRST(dev))
dev_priv->iLVDS_enable = fuse_value & FB_MIPI_DISABLE;
DRM_INFO("internal display is %s\n",
dev_priv->iLVDS_enable ? "LVDS display" : "MIPI display");
/* Prevent runtime suspend at start*/
if (dev_priv->iLVDS_enable) {
dev_priv->is_lvds_on = true;
dev_priv->is_mipi_on = false;
} else {
dev_priv->is_mipi_on = true;
dev_priv->is_lvds_on = false;
}
dev_priv->video_device_fuse = fuse_value;
pci_write_config_dword(pci_root, 0xD0, FB_REG09);
pci_read_config_dword(pci_root, 0xD4, &fuse_value);
dev_dbg(dev->dev, "SKU values is 0x%x.\n", fuse_value);
fuse_value_tmp = (fuse_value & FB_SKU_MASK) >> FB_SKU_SHIFT;
dev_priv->fuse_reg_value = fuse_value;
switch (fuse_value_tmp) {
case FB_SKU_100:
dev_priv->core_freq = 200;
break;
case FB_SKU_100L:
dev_priv->core_freq = 100;
break;
case FB_SKU_83:
dev_priv->core_freq = 166;
break;
default:
dev_warn(dev->dev, "Invalid SKU values, SKU value = 0x%08x\n",
fuse_value_tmp);
dev_priv->core_freq = 0;
}
dev_dbg(dev->dev, "LNC core clk is %dMHz.\n", dev_priv->core_freq);
pci_dev_put(pci_root);
}
static void psb_xrandr_coordinate_init(VADriverContextP ctx)
{
INIT_DRIVER_DATA;
psb_xrandr_output_p p_output;
psb_xrandr_info->output_changed = 1;
for (p_output = psb_xrandr_info->output_head; p_output; p_output = p_output->next) {
if (p_output->connection == RR_Connected) {
if (!strcmp(p_output->name, "MIPI0")) {
if (p_output->crtc) {
psb_xrandr_info->mipi0_enabled = 1;
psb_xrandr_info->local_output[0] = p_output;
psb_xrandr_info->local_crtc[0] = p_output->crtc;
if (psb_xrandr_info->mipi0_rotation != p_output->crtc->rotation) {
psb_xrandr_info->mipi0_rotation = p_output->crtc->rotation;
driver_data->mipi0_rotation = RRrotation2VArotation(psb_xrandr_info->mipi0_rotation);
driver_data->xrandr_dirty |= PSB_NEW_ROTATION;
}
} else {
psb_xrandr_info->mipi0_enabled = 0;
psb_xrandr_info->local_output[0] = NULL;
psb_xrandr_info->local_crtc[0] = NULL;
}
} else if (!strcmp(p_output->name, "MIPI1")) {
if (p_output->crtc) {
psb_xrandr_info->mipi1_enabled = 1;
psb_xrandr_info->local_output[1] = p_output;
psb_xrandr_info->local_crtc[1] = p_output->crtc;
if (psb_xrandr_info->mipi1_rotation != p_output->crtc->rotation) {
psb_xrandr_info->mipi1_rotation = p_output->crtc->rotation;
driver_data->mipi1_rotation = RRrotation2VArotation(psb_xrandr_info->mipi1_rotation);
driver_data->xrandr_dirty |= PSB_NEW_ROTATION;
}
} else {
psb_xrandr_info->mipi1_enabled = 0;
psb_xrandr_info->local_output[1] = NULL;
psb_xrandr_info->local_crtc[1] = NULL;
}
} else if (!strcmp(p_output->name, "TMDS0-1")) {
if (p_output->crtc) {
psb_xrandr_info->hdmi_enabled = 1;
psb_xrandr_info->extend_output = p_output;
psb_xrandr_info->extend_crtc = p_output->crtc;
if (psb_xrandr_info->hdmi_rotation != p_output->crtc->rotation) {
psb_xrandr_info->hdmi_rotation = p_output->crtc->rotation;
driver_data->hdmi_rotation = RRrotation2VArotation(psb_xrandr_info->hdmi_rotation);
driver_data->xrandr_dirty |= PSB_NEW_ROTATION;
}
} else {
psb_xrandr_info->hdmi_enabled = 0;
psb_xrandr_info->extend_output = NULL;
psb_xrandr_info->extend_crtc = NULL;
}
} else if (!strcmp(p_output->name, "LVDS0") && IS_MRST(driver_data)) {
if (p_output->crtc) {
psb_xrandr_info->lvds0_enabled = 1;
psb_xrandr_info->local_output[0] = p_output;
psb_xrandr_info->local_crtc[0] = p_output->crtc;
} else {
psb_xrandr_info->lvds0_enabled = 0;
psb_xrandr_info->local_output[0] = NULL;
psb_xrandr_info->local_crtc[0] = NULL;
}
}
}
}
/* for MRST */
if (IS_MRST(driver_data) && psb_xrandr_info->lvds0_enabled) {
psb_xrandr_info->hdmi_extvideo_prop->ExtDesktopMode = SINGLE;
psb_xrandr_info->output_device_mode = SINGLE_LVDS0;
psb_xrandr_info->local_crtc[0]->location = NORMAL;
return;
}
/* HDMI + either MIPI0 or MIPI1 */
if (psb_xrandr_info->hdmi_enabled) {
/* Get HDMI properties if it is enabled*/
psb_xrandr_hdmi_property(ctx);
/* Only HDMI */
if (!psb_xrandr_info->mipi0_enabled && !psb_xrandr_info->mipi1_enabled)
psb_xrandr_info->output_device_mode = SINGLE_HDMI;
/* HDMI + MIPI0 */
if (psb_xrandr_info->mipi0_enabled && !psb_xrandr_info->mipi1_enabled)
psb_xrandr_info->output_device_mode = MIPI0_HDMI;
/* HDMI + MIPI1 */
if (!psb_xrandr_info->mipi0_enabled && psb_xrandr_info->mipi1_enabled)
psb_xrandr_info->output_device_mode = MIPI1_HDMI;
/* HDMI + MIPI0 + MIPI1 */
if (psb_xrandr_info->mipi0_enabled && psb_xrandr_info->mipi1_enabled)
psb_xrandr_info->output_device_mode = MIPI0_MIPI1_HDMI;
psb_xrandr_hdmi_location_init(psb_xrandr_info->output_device_mode);
} else {
/* MIPI0 + MIPI1 */
if (psb_xrandr_info->mipi0_enabled && psb_xrandr_info->mipi1_enabled) {
psb_xrandr_info->output_device_mode = MIPI0_MIPI1;
} else {
/* MIPI0/MIPI1 */
if (psb_xrandr_info->mipi0_enabled)
psb_xrandr_info->output_device_mode = SINGLE_MIPI0;
else if (psb_xrandr_info->mipi1_enabled)
psb_xrandr_info->output_device_mode = SINGLE_MIPI1;
}
psb_xrandr_mipi_location_init(psb_xrandr_info->output_device_mode);
}
}
IMG_BOOL MRSTLFBFlipToSurface(MRSTLFB_DEVINFO *psDevInfo,
unsigned long uiAddr)
{
int dspbase = (psDevInfo->ui32MainPipe == 0 ? DSPABASE : DSPBBASE);
int dspsurf = (psDevInfo->ui32MainPipe == 0 ? DSPASURF : DSPBSURF);
struct drm_device * dev = psDevInfo->psDrmDevice;
struct drm_psb_private *dev_priv =
(struct drm_psb_private *) psDevInfo->psDrmDevice->dev_private;
MRSTLFB_SWAPCHAIN *psCurrentSwapChain = psDevInfo->psCurrentSwapChain;
struct mdfld_dsi_config *dsi_config;
struct mdfld_dsi_hw_context *ctx;
unsigned int tmp;
if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, false))
{
if (IS_MRST(dev)) {
MRSTLFBVSyncWriteReg(psDevInfo, dspsurf, uiAddr);
} else if (IS_MDFLD(dev)) {
if (psCurrentSwapChain != NULL) {
if (psCurrentSwapChain->ui32SwapChainPropertyFlag
& PVRSRV_SWAPCHAIN_ATTACHED_PLANE_A) {
dspsurf = DSPASURF;
tmp = PSB_RVDC32(DSPACNTR);
if (!(tmp & DISPLAY_PLANE_ENABLE))
PSB_WVDC32(tmp | DISPLAY_PLANE_ENABLE,
DSPACNTR);
MRSTLFBVSyncWriteReg(psDevInfo, dspsurf, uiAddr);
dsi_config = dev_priv->dsi_configs[0];
if (dsi_config) {
ctx = &dsi_config->dsi_hw_context;
ctx->dspsurf = uiAddr;
}
if (mdfld_dsi_dsr_update_panel_fb(dsi_config)) {
ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
return IMG_FALSE;
}
}
#if defined(CONFIG_MDFD_DUAL_MIPI)
if (psCurrentSwapChain->ui32SwapChainPropertyFlag
& PVRSRV_SWAPCHAIN_ATTACHED_PLANE_C) {
dspsurf = DSPCSURF;
tmp = PSB_RVDC32(DSPACNTR + 0x2000);
if (!(tmp & DISPLAY_PLANE_ENABLE))
PSB_WVDC32(tmp | DISPLAY_PLANE_ENABLE,
DSPACNTR + 0x2000);
MRSTLFBVSyncWriteReg(psDevInfo, dspsurf, uiAddr);
dsi_config = dev_priv->dsi_configs[1];
if (dsi_config) {
ctx = &dsi_config->dsi_hw_context;
ctx->dspsurf = uiAddr;
}
if (mdfld_dsi_dsr_update_panel_fb(dsi_config)) {
ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
return IMG_FALSE;
}
}
#endif
#ifdef CONFIG_SUPPORT_HDMI
/* To avoid Plane B still fetches data from original frame
* buffer. */
if (psCurrentSwapChain->ui32SwapChainPropertyFlag
& PVRSRV_SWAPCHAIN_ATTACHED_PLANE_B) {
dspsurf = DSPBSURF;
tmp = PSB_RVDC32(DSPACNTR + 0x1000);
if (!(tmp & DISPLAY_PLANE_ENABLE))
PSB_WVDC32(tmp | DISPLAY_PLANE_ENABLE,
DSPACNTR + 0x1000);
MRSTLFBVSyncWriteReg(psDevInfo, dspsurf, uiAddr);
}
#endif
} else {
printk(KERN_WARNING "Current Swapchain is null, no attached plane info\
available, omit address update\n");
if (drm_psb_debug & PSB_D_GENERAL)
dump_stack();
}
} else {
MRSTLFBVSyncWriteReg(psDevInfo, dspbase, uiAddr);
}
ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
}
static PVRSRV_ERROR SysLocateDevices(SYS_DATA *psSysData)
{
IMG_UINT32 ui32BaseAddr = 0;
IMG_UINT32 ui32IRQ = 0;
#if defined(SGX_FEATURE_HOST_PORT)
IMG_UINT32 ui32HostPortAddr = 0;
#endif
SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData;
#if defined(SUPPORT_EXTERNAL_SYSTEM_CACHE)
struct drm_psb_private *dev_priv = (struct drm_psb_private *) gpDrmDevice->dev_private;
#endif
ui32BaseAddr = OSPCIAddrRangeStart(psSysSpecData->hSGXPCI, POULSBO_ADDR_RANGE_INDEX);
#if defined(SGX_FEATURE_HOST_PORT)
ui32HostPortAddr = OSPCIAddrRangeStart(psSysSpecData->hSGXPCI, POULSBO_HP_ADDR_RANGE_INDEX);
#endif
if (OSPCIIRQ(psSysSpecData->hSGXPCI, &ui32IRQ) != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"SysLocateDevices: Couldn't get IRQ"));
return PVRSRV_ERROR_INVALID_DEVICE;
}
PVR_TRACE(("ui32BaseAddr: %08X", ui32BaseAddr));
#if defined(SGX_FEATURE_HOST_PORT)
PVR_TRACE(("ui32HostPortAddr: %08X", ui32HostPortAddr));
#endif
PVR_TRACE(("IRQ: %d", ui32IRQ));
gsSGXDeviceMap.ui32Flags = 0x0;
gsSGXDeviceMap.ui32IRQ = ui32IRQ;
#if defined(SUPPORT_DRI_DRM_EXT)
gsSGXDeviceMap.sRegsSysPBase.uiAddr = ui32BaseAddr + ((IS_MRST(psSysSpecData->psDRMDev) || IS_MDFLD(psSysSpecData->psDRMDev)) ? MRST_SGX_REGS_OFFSET : POULSBO_SGX_REGS_OFFSET);
#else
gsSGXDeviceMap.sRegsSysPBase.uiAddr = ui32BaseAddr + SGX_REGS_OFFSET;
#endif
gsSGXDeviceMap.sRegsCpuPBase = SysSysPAddrToCpuPAddr(gsSGXDeviceMap.sRegsSysPBase);
gsSGXDeviceMap.ui32RegsSize = SGX_REG_SIZE;
#if defined(SGX_FEATURE_HOST_PORT)
gsSGXDeviceMap.ui32Flags = SGX_HOSTPORT_PRESENT;
gsSGXDeviceMap.sHPSysPBase.uiAddr = ui32HostPortAddr;
gsSGXDeviceMap.sHPCpuPBase = SysSysPAddrToCpuPAddr(gsSGXDeviceMap.sHPSysPBase);
gsSGXDeviceMap.ui32HPSize = SYS_SGX_HP_SIZE;
#endif
#if defined(MRST_SLAVEPORT)
gsSGXDeviceMap.sSPSysPBase.uiAddr = ui32BaseAddr + MRST_SGX_SP_OFFSET;
gsSGXDeviceMap.sSPCpuPBase = SysSysPAddrToCpuPAddr(gsSGXDeviceMap.sSPSysPBase);
gsSGXDeviceMap.ui32SPSize = SGX_SP_SIZE;
#endif
gsSGXDeviceMap.sLocalMemSysPBase.uiAddr = 0;
gsSGXDeviceMap.sLocalMemDevPBase.uiAddr = 0;
gsSGXDeviceMap.sLocalMemCpuPBase.uiAddr = 0;
gsSGXDeviceMap.ui32LocalMemSize = 0;
#if defined(SUPPORT_EXTERNAL_SYSTEM_CACHE)
gsSGXDeviceMap.sExtSysCacheRegsDevPBase.uiAddr = SYS_EXT_SYS_CACHE_GBL_INV_REG_OFFSET;
gsSGXDeviceMap.ui32ExtSysCacheRegsSize = SGX_EXT_SYSTEM_CACHE_REGS_SIZE;
MDFLD_GL3_WRITE(gsSGXDeviceMap.sExtSysCacheRegsDevPBase.uiAddr, MDFLD_GL3_USE_WRT_INVAL);
#endif
#if !defined(NO_HARDWARE)
{
IMG_SYS_PHYADDR sPoulsboRegsCpuPBase;
sPoulsboRegsCpuPBase.uiAddr = ui32BaseAddr + POULSBO_REGS_OFFSET;
gsPoulsboRegsCPUVaddr = OSMapPhysToLin(SysSysPAddrToCpuPAddr(sPoulsboRegsCpuPBase),
POULSBO_REG_SIZE,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
IMG_NULL);
sPoulsboRegsCpuPBase.uiAddr = ui32BaseAddr + POULSBO_DISPLAY_REGS_OFFSET;
gsPoulsboDisplayRegsCPUVaddr = OSMapPhysToLin(SysSysPAddrToCpuPAddr(sPoulsboRegsCpuPBase),
POULSBO_DISPLAY_REG_SIZE,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
IMG_NULL);
}
#endif
#if defined(PDUMP)
{
static IMG_CHAR pszPDumpDevName[] = "SGXMEM";
gsSGXDeviceMap.pszPDumpDevName = pszPDumpDevName;
}
#endif
return PVRSRV_OK;
}
static PVRSRV_ERROR PCIInitDev(SYS_DATA *psSysData)
{
SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData;
IMG_UINT32 ui32MaxOffset = MRST_MAX_OFFSET;
#if defined(SUPPORT_DRI_DRM_EXT)
if (!IS_MDFLD(psSysSpecData->psDRMDev) && !IS_MRST(psSysSpecData->psDRMDev) && !IS_POULSBO(psSysSpecData->psDRMDev))
{
PVR_DPF((PVR_DBG_ERROR,"PCIInitDev: Device not supported"));
return PVRSRV_ERROR_NOT_SUPPORTED;
}
psSysSpecData->hSGXPCI = OSPCISetDev((IMG_VOID *)psSysSpecData->psPCIDev, 0);
ui32MaxOffset = (IS_MRST(psSysSpecData->psDRMDev) || IS_MDFLD(psSysSpecData->psDRMDev)) ? MRST_MAX_OFFSET : POULSBO_MAX_OFFSET;
#else
#if defined(LDM_PCI) || defined(SUPPORT_DRI_DRM)
psSysSpecData->hSGXPCI = OSPCISetDev((IMG_VOID *)psSysSpecData->psPCIDev, HOST_PCI_INIT_FLAG_BUS_MASTER | HOST_PCI_INIT_FLAG_MSI);
#else
psSysSpecData->hSGXPCI = OSPCIAcquireDev(SYS_SGX_DEV_VENDOR_ID, SYS_SGX_DEV_DEVICE_ID, HOST_PCI_INIT_FLAG_BUS_MASTER | HOST_PCI_INIT_FLAG_MSI);
#endif
#endif
if (!psSysSpecData->hSGXPCI)
{
PVR_DPF((PVR_DBG_ERROR,"PCIInitDev: Failed to acquire PCI device"));
return PVRSRV_ERROR_PCI_DEVICE_NOT_FOUND;
}
SYS_SPECIFIC_DATA_SET(psSysSpecData, SYS_SPECIFIC_DATA_PCI_ACQUIRE_DEV);
PVR_TRACE(("PCI memory region: %x to %x", OSPCIAddrRangeStart(psSysSpecData->hSGXPCI, POULSBO_ADDR_RANGE_INDEX), OSPCIAddrRangeEnd(psSysSpecData->hSGXPCI, POULSBO_ADDR_RANGE_INDEX)));
#if defined(SGX_FEATURE_HOST_PORT)
PVR_TRACE(("Host Port region: %x to %x", OSPCIAddrRangeStart(psSysSpecData->hSGXPCI, POULSBO_HP_ADDR_RANGE_INDEX), OSPCIAddrRangeEnd(psSysSpecData->hSGXPCI, POULSBO_HP_ADDR_RANGE_INDEX)));
#endif
if (OSPCIAddrRangeLen(psSysSpecData->hSGXPCI, POULSBO_ADDR_RANGE_INDEX) < ui32MaxOffset)
{
PVR_DPF((PVR_DBG_ERROR,"PCIInitDev: Device memory region isn't big enough"));
return PVRSRV_ERROR_PCI_REGION_TOO_SMALL;
}
if (OSPCIRequestAddrRange(psSysSpecData->hSGXPCI, POULSBO_ADDR_RANGE_INDEX) != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"PCIInitDev: Device memory region not available"));
return PVRSRV_ERROR_PCI_REGION_UNAVAILABLE;
}
SYS_SPECIFIC_DATA_SET(psSysSpecData, SYS_SPECIFIC_DATA_PCI_REQUEST_SGX_ADDR_RANGE);
#if defined(SGX_FEATURE_HOST_PORT)
if (OSPCIRequestAddrRange(psSysSpecData->hSGXPCI, POULSBO_HP_ADDR_RANGE_INDEX) != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"PCIInitDev: Host Port region not available"));
return PVRSRV_ERROR_PCI_REGION_UNAVAILABLE;
}
SYS_SPECIFIC_DATA_SET(psSysSpecData, SYS_SPECIFIC_DATA_PCI_REQUEST_HOST_PORT_RANGE);
#endif
return PVRSRV_OK;
}
