// IRQL = PASSIVE_LEVEL int rtmp_ee_prom_read16( IN PRTMP_ADAPTER pAd, IN USHORT Offset, OUT USHORT *pValue) { UINT32 x; USHORT data; #ifdef RT30xx #ifdef ANT_DIVERSITY_SUPPORT if (pAd->NicConfig2.field.AntDiversity) { pAd->EepromAccess = TRUE; } #endif // ANT_DIVERSITY_SUPPORT // #endif // RT30xx // Offset /= 2; // reset bits and set EECS RTMP_IO_READ32(pAd, E2PROM_CSR, &x); x &= ~(EEDI | EEDO | EESK); x |= EECS; RTMP_IO_WRITE32(pAd, E2PROM_CSR, x); // patch can not access e-Fuse issue if (!(IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd) || IS_RT3593(pAd))) { // kick a pulse RaiseClock(pAd, &x); LowerClock(pAd, &x); } // output the read_opcode and register number in that order ShiftOutBits(pAd, EEPROM_READ_OPCODE, 3); ShiftOutBits(pAd, Offset, pAd->EEPROMAddressNum); // Now read the data (16 bits) in from the selected EEPROM word data = ShiftInBits(pAd); EEpromCleanup(pAd); #ifdef RT30xx #ifdef ANT_DIVERSITY_SUPPORT // Antenna and EEPROM access are both using EESK pin, // Therefor we should avoid accessing EESK at the same time // Then restore antenna after EEPROM access if ((pAd->NicConfig2.field.AntDiversity)/* || (pAd->RfIcType == RFIC_3020)*/) { pAd->EepromAccess = FALSE; AsicSetRxAnt(pAd, pAd->RxAnt.Pair1PrimaryRxAnt); } #endif // ANT_DIVERSITY_SUPPORT // #endif // RT30xx // *pValue = data; return NDIS_STATUS_SUCCESS; }
VOID RtmpChipOpsRFHook( IN RTMP_ADAPTER *pAd) { RTMP_CHIP_OP *pChipOps = &pAd->chipOps; pChipOps->pRFRegTable = NULL; pChipOps->pBBPRegTable = NULL; pChipOps->AsicRfInit = NULL; pChipOps->AsicRfTurnOn = NULL; pChipOps->AsicRfTurnOff = NULL; pChipOps->AsicReverseRfFromSleepMode = NULL; pChipOps->AsicHaltAction = NULL; /* We depends on RfICType and MACVersion to assign the corresponding operation callbacks. */ #ifdef RT30xx #ifdef RT3593 if (IS_RT3593(pAd)) { pChipOps->AsicRfTurnOff = RT30xxLoadRFSleepModeSetup; pChipOps->pRFRegTable = RF3053RegTable; pChipOps->AsicRfInit = NICInitRT3593RFRegisters; pChipOps->AsicReverseRfFromSleepMode = RT30xxReverseRFSleepModeSetup; pChipOps->AsicHaltAction = RT30xxHaltAction; } #endif // RT3593 // if (IS_RT30xx(pAd)) { /* WARNING: Currently following table are shared by all RT30xx based IC, change it carefully when you add a new IC here. */ pChipOps->pRFRegTable = RT3020_RFRegTable; pChipOps->AsicHaltAction = RT30xxHaltAction; pChipOps->AsicRfTurnOff = RT30xxLoadRFSleepModeSetup; pChipOps->AsicReverseRfFromSleepMode = RT30xxReverseRFSleepModeSetup; #ifdef RT3070 if((IS_RT3070(pAd) || IS_RT3071(pAd)) && (pAd->infType == RTMP_DEV_INF_USB)) { pChipOps->AsicRfInit = NICInitRT3070RFRegisters; } #endif // RT3070 // } #endif // RT30xx // if (pChipOps->pBBPRegTable != NULL) pChipOps->bbpRegTbSize = (sizeof(*(pChipOps->pBBPRegTable)) / sizeof(REG_PAIR)); DBGPRINT(RT_DEBUG_TRACE, ("Chip specific bbpRegTbSize=%d!\n", pChipOps->bbpRegTbSize)); }
/* ========================================================================== Description: dynamic tune BBP R66 to find a balance between sensibility and noise isolation IRQL = DISPATCH_LEVEL ========================================================================== */ UCHAR RT35xx_ChipAGCAdjust( IN RTMP_ADAPTER *pAd, IN CHAR Rssi, IN UCHAR OrigR66Value) { UCHAR R66 = OrigR66Value; CHAR lanGain = GET_LNA_GAIN(pAd); if (!(IS_RT3572(pAd) || IS_RT3593(pAd))) { DBGPRINT(RT_DEBUG_ERROR, ("RT35xx_ChipAGCAdjust - Mismatch MACVersion = 0x%x \n", pAd->MACVersion)); return R66; } if (pAd->LatchRfRegs.Channel <= 14) { /*BG band*/ R66 = 0x1C + 2 * lanGain; if (Rssi > RSSI_FOR_MID_LOW_SENSIBILITY) R66 += 0x20; } else { /*A band*/ if (pAd->CommonCfg.BBPCurrentBW == BW_20) { R66 = 0x32 + (lanGain*5) / 3; if (Rssi > RSSI_FOR_MID_LOW_SENSIBILITY) R66 += 0x10; } else { R66 = 0x3A + (lanGain*5)/3; if (Rssi > RSSI_FOR_MID_LOW_SENSIBILITY) R66 += 0x10; } #ifdef RT3593 if (Rssi > RSSI_FOR_MID_LOW_SENSIBILITY) { RT3593_R66_MID_LOW_SENS_GET(pAd, R66); } else { RT3593_R66_NON_MID_LOW_SEMS_GET(pAd, R66); } #endif /* RT3593 */ } if (OrigR66Value != R66) AsicBBPWriteWithRxChain(pAd, BBP_R66, R66, RX_CHAIN_ALL); return R66; }
int rtmp_ee_prom_write16( IN PRTMP_ADAPTER pAd, IN USHORT Offset, IN USHORT Data) { UINT32 x; #ifdef RT30xx #endif // RT30xx // Offset /= 2; EWEN(pAd); // reset bits and set EECS RTMP_IO_READ32(pAd, E2PROM_CSR, &x); x &= ~(EEDI | EEDO | EESK); x |= EECS; RTMP_IO_WRITE32(pAd, E2PROM_CSR, x); // patch can not access e-Fuse issue if (!(IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd) || IS_RT3593(pAd))) { // kick a pulse RaiseClock(pAd, &x); LowerClock(pAd, &x); } // output the read_opcode ,register number and data in that order ShiftOutBits(pAd, EEPROM_WRITE_OPCODE, 3); ShiftOutBits(pAd, Offset, pAd->EEPROMAddressNum); ShiftOutBits(pAd, Data, 16); // 16-bit access // read DO status RTMP_IO_READ32(pAd, E2PROM_CSR, &x); EEpromCleanup(pAd); RTMPusecDelay(10000); //delay for twp(MAX)=10ms EWDS(pAd); EEpromCleanup(pAd); #ifdef RT30xx #endif // RT30xx // return NDIS_STATUS_SUCCESS; }
// IRQL = PASSIVE_LEVEL int rtmp_ee_prom_read16( IN PRTMP_ADAPTER pAd, IN USHORT Offset, OUT USHORT *pValue) { UINT32 x; USHORT data; #ifdef RT30xx #endif // RT30xx // Offset /= 2; // reset bits and set EECS RTMP_IO_READ32(pAd, E2PROM_CSR, &x); x &= ~(EEDI | EEDO | EESK); x |= EECS; RTMP_IO_WRITE32(pAd, E2PROM_CSR, x); // patch can not access e-Fuse issue if (!(IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd) || IS_RT3593(pAd))) { // kick a pulse RaiseClock(pAd, &x); LowerClock(pAd, &x); } // output the read_opcode and register number in that order ShiftOutBits(pAd, EEPROM_READ_OPCODE, 3); ShiftOutBits(pAd, Offset, pAd->EEPROMAddressNum); // Now read the data (16 bits) in from the selected EEPROM word data = ShiftInBits(pAd); EEpromCleanup(pAd); #ifdef RT30xx #endif // RT30xx // *pValue = data; return NDIS_STATUS_SUCCESS; }
VOID RT30xx_RTMPSetAGCInitValue( IN PRTMP_ADAPTER pAd, IN UCHAR BandWidth) { UCHAR R66 = 0x30; if (pAd->LatchRfRegs.Channel <= 14) { /* BG band*/ /* Gary was verified Amazon AP and find that RT307x has BBP_R66 invalid default value */ if (IS_RT3070(pAd)||IS_RT3090(pAd) || IS_RT3390(pAd) || IS_RT3593(pAd)) { R66 = 0x1C + 2*GET_LNA_GAIN(pAd); { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, R66); } } } }
/* ======================================================================== Routine Description: 3572/3592 R66 writing must select BBP_R27 Arguments: Return Value: IRQL = Note: ======================================================================== */ NTSTATUS RT3572WriteBBPR66( IN PRTMP_ADAPTER pAd, IN UCHAR Value) { NTSTATUS NStatus = STATUS_UNSUCCESSFUL; UCHAR bbpData = 0; if (!IS_RT3572(pAd) && !IS_RT3593(pAd)) { DBGPRINT(RT_DEBUG_ERROR, ("%s: Incorrect MAC version, pAd->MACVersion = 0x%X\n", __FUNCTION__, pAd->MACVersion)); return NStatus; } RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R27, &bbpData); /* R66 controls the gain of Rx0*/ bbpData &= ~(0x60); /*clear bit 5,6*/ #ifdef RTMP_MAC_USB if (RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R27, bbpData) == STATUS_SUCCESS) #endif /* RTMP_MAC_USB */ { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, Value); } /* R66 controls the gain of Rx1*/ bbpData |= 0x20; /* set bit 5*/ #ifdef RTMP_MAC_USB if (RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R27, bbpData) == STATUS_SUCCESS) #endif /* RTMP_MAC_USB */ { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, Value); NStatus = STATUS_SUCCESS; } return NStatus; }
VOID RT35xx_RxSensitivityTuning( IN PRTMP_ADAPTER pAd) { UCHAR R66; R66 = 0x26 + GET_LNA_GAIN(pAd); #ifdef RALINK_ATE if (ATE_ON(pAd)) { ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, (0x26 + GET_LNA_GAIN(pAd))); } else #endif /* RALINK_ATE */ #ifdef RT35xx if (IS_RT3572(pAd) || IS_RT3593(pAd)) { RT3572WriteBBPR66(pAd, (0x26 + GET_LNA_GAIN(pAd))); } #endif /* RT35xx */ DBGPRINT(RT_DEBUG_TRACE,("turn off R17 tuning, restore to 0x%02x\n", R66)); }
/* ========================================================================== Description: Setup Frame format. NOTE: This routine should only be used in ATE mode. ========================================================================== */ INT ATESetUpFrame( IN PRTMP_ADAPTER pAd, IN UINT32 TxIdx) { PATE_INFO pATEInfo = &(pAd->ate); UINT pos = 0; TXINFO_STRUC *pTxInfo; TXD_STRUC *pTxD; #ifdef RT_BIG_ENDIAN TXD_STRUC *pDestTxD; UCHAR tx_hw_info[TXD_SIZE]; #endif /* RT_BIG_ENDIAN */ PNDIS_PACKET pPacket=NULL; PUCHAR pDest=NULL; PVOID AllocVa=NULL; NDIS_PHYSICAL_ADDRESS AllocPa; HTTRANSMIT_SETTING TxHTPhyMode; RTMP_TX_RING *pTxRing = &pAd->TxRing[QID_AC_BE]; TXWI_STRUC *pTxWI = (TXWI_STRUC *)pTxRing->Cell[TxIdx].DmaBuf.AllocVa; PUCHAR pDMAHeaderBufVA = (PUCHAR) pTxRing->Cell[TxIdx].DmaBuf.AllocVa; UINT8 TXWISize = pAd->chipCap.TXWISize; #ifdef RALINK_QA PHEADER_802_11 pHeader80211; #endif /* RALINK_QA */ UCHAR bw, sgi, stbc, mcs, phy_mode, frag, cfack, ts, ampdu, ack, nseq, bawinsize, pkt_id, txop; USHORT byte_cnt; bw = sgi = stbc = mcs = phy_mode = frag = cfack = ts =0; ampdu = ack = nseq = bawinsize = pkt_id = txop = 0; byte_cnt = 0; #ifdef RLT_MAC if (pAd->chipCap.hif_type == HIF_RLT) { bw = pATEInfo->TxWI.TXWI_N.BW; sgi = pATEInfo->TxWI.TXWI_N.ShortGI; stbc = pATEInfo->TxWI.TXWI_N.STBC; mcs = pATEInfo->TxWI.TXWI_N.MCS; phy_mode = pATEInfo->TxWI.TXWI_N.PHYMODE; frag = pATEInfo->TxWI.TXWI_N.FRAG; cfack = pATEInfo->TxWI.TXWI_N.CFACK, ts = pATEInfo->TxWI.TXWI_N.TS; ampdu = pATEInfo->TxWI.TXWI_N.AMPDU; ack = pATEInfo->TxWI.TXWI_N.ACK; nseq = pATEInfo->TxWI.TXWI_N.NSEQ; bawinsize =pATEInfo->TxWI.TXWI_N.BAWinSize; byte_cnt = pATEInfo->TxWI.TXWI_N.MPDUtotalByteCnt; pkt_id = pATEInfo->TxWI.TXWI_N.TxPktId; txop = pATEInfo->TxWI.TXWI_N.txop; cfack = pATEInfo->TxWI.TXWI_N.CFACK; } #endif /* RLT_MAC */ #ifdef RTMP_MAC if (pAd->chipCap.hif_type == HIF_RTMP) { bw = pATEInfo->TxWI.TXWI_O.BW; sgi = pATEInfo->TxWI.TXWI_O.ShortGI; stbc = pATEInfo->TxWI.TXWI_O.STBC; mcs = pATEInfo->TxWI.TXWI_O.MCS; phy_mode = pATEInfo->TxWI.TXWI_O.PHYMODE; frag = pATEInfo->TxWI.TXWI_O.FRAG; cfack = pATEInfo->TxWI.TXWI_O.CFACK, ts = pATEInfo->TxWI.TXWI_O.TS; ampdu = pATEInfo->TxWI.TXWI_O.AMPDU; ack = pATEInfo->TxWI.TXWI_O.ACK; nseq = pATEInfo->TxWI.TXWI_O.NSEQ; bawinsize =pATEInfo->TxWI.TXWI_O.BAWinSize; byte_cnt = pATEInfo->TxWI.TXWI_O.MPDUtotalByteCnt; pkt_id = pATEInfo->TxWI.TXWI_O.PacketId; txop = pATEInfo->TxWI.TXWI_O.txop; cfack = pATEInfo->TxWI.TXWI_O.CFACK; } #endif /* RTMP_MAC */ /* fill TxWI */ TxHTPhyMode.field.BW = bw; TxHTPhyMode.field.ShortGI = sgi; TxHTPhyMode.field.STBC = stbc; TxHTPhyMode.field.MCS = mcs; TxHTPhyMode.field.MODE = phy_mode; if (pATEInfo->bQATxStart == TRUE) { /* always use QID_AC_BE and FIFO_EDCA */ ATEWriteTxWI(pAd, pTxWI, frag, cfack, ts, ampdu, ack, nseq, bawinsize, 0, byte_cnt, pkt_id, 0, 0, txop, cfack, &TxHTPhyMode); #ifdef TXBF_SUPPORT #ifdef RTMP_MAC if (IS_RT2883(pAd) || IS_RT3883(pAd) || IS_RT3593(pAd)) { /* Must copy rsv bits to actual TxWI */ //pTxWI->TXWI_O.Reserved = pATEInfo->TxWI.TXWI_O.Reserved; pTxWI->TXWI_O.iTxBF = pATEInfo->TxWI.TXWI_O.iTxBF; pTxWI->TXWI_O.Sounding = pATEInfo->TxWI.TXWI_O.Sounding; pTxWI->TXWI_O.eTxBF = pATEInfo->TxWI.TXWI_O.eTxBF; pTxWI->TXWI_O.Autofallback = pATEInfo->TxWI.TXWI_O.Autofallback; pTxWI->TXWI_O.NDPSndBW = pATEInfo->TxWI.TXWI_O.NDPSndBW; pTxWI->TXWI_O.NDPSndRate = pATEInfo->TxWI.TXWI_O.NDPSndRate; } #endif #ifdef RLT_MAC if (IS_MT76x2(pAd)) { /* Must copy rsv bits to actual TxWI */ pTxWI->TXWI_N.Rsv4 = pATEInfo->TxWI.TXWI_N.Rsv4; pTxWI->TXWI_N.iTxBF = pATEInfo->TxWI.TXWI_N.iTxBF; pTxWI->TXWI_N.Sounding = pATEInfo->TxWI.TXWI_N.Sounding; pTxWI->TXWI_N.eTxBF = pATEInfo->TxWI.TXWI_N.eTxBF; //pTxWI->TXWI_N.Autofallback = pATEInfo->TxWI.TXWI_N.Autofallback; pTxWI->TXWI_N.NDPSndBW = pATEInfo->TxWI.TXWI_N.NDPSndBW; pTxWI->TXWI_N.NDPSndRate = pATEInfo->TxWI.TXWI_N.NDPSndRate; pTxWI->TXWI_N.TXBF_PT_SCA = pATEInfo->TxWI.TXWI_N.TXBF_PT_SCA; } #endif #endif /* TXBF_SUPPORT */ } else { ATEWriteTxWI(pAd, pTxWI, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, 4, 0, pATEInfo->TxLength, 0, 0, 0, IFS_HTTXOP, FALSE, &TxHTPhyMode); #ifdef TXBF_SUPPORT if (pATEInfo->bTxBF == 1) { #ifdef RTMP_MAC if (IS_RT2883(pAd) || IS_RT3883(pAd) || IS_RT3593(pAd)) { //pTxWI->TXWI_O.Reserved = 0; pTxWI->TXWI_O.Sounding = (pATEInfo->txSoundingMode == 1 ? 1 : 0); if(pATEInfo->txSoundingMode) { pTxWI->TXWI_O.iTxBF = FALSE; pTxWI->TXWI_O.eTxBF = FALSE; } else { pTxWI->TXWI_O.iTxBF = pATEInfo->TxWI.TXWI_O.iTxBF; pTxWI->TXWI_O.eTxBF = pATEInfo->TxWI.TXWI_O.eTxBF; } pTxWI->TXWI_O.Autofallback = pATEInfo->TxWI.TXWI_O.Autofallback; pTxWI->TXWI_O.NDPSndBW = pATEInfo->TxWI.TXWI_O.BW; if (pATEInfo->txSoundingMode == 3) pTxWI->TXWI_O.NDPSndRate = 2; else if (pATEInfo->txSoundingMode == 2) pTxWI->TXWI_O.NDPSndRate = 1; else pTxWI->TXWI_O.NDPSndRate = 0; } #endif #ifdef RLT_MAC if (IS_MT76x2(pAd)) { pTxWI->TXWI_N.Rsv4 = 0; pTxWI->TXWI_N.Sounding = (pATEInfo->txSoundingMode == 1 ? 1 : 0); if(pATEInfo->txSoundingMode) { pTxWI->TXWI_N.iTxBF = FALSE; pTxWI->TXWI_N.eTxBF = FALSE; } else { pTxWI->TXWI_N.iTxBF = pATEInfo->TxWI.TXWI_N.iTxBF; pTxWI->TXWI_N.eTxBF = pATEInfo->TxWI.TXWI_N.eTxBF; } //pTxWI->TXWI_N.Autofallback = pATEInfo->TxWI.TXWI_N.Autofallback; pTxWI->TXWI_N.NDPSndBW = pATEInfo->TxWI.TXWI_N.BW; if (pATEInfo->txSoundingMode == 3) pTxWI->TXWI_N.NDPSndRate = 2; else if (pATEInfo->txSoundingMode == 2) pTxWI->TXWI_N.NDPSndRate = 1; else pTxWI->TXWI_N.NDPSndRate = 0; pTxWI->TXWI_N.TXBF_PT_SCA = pATEInfo->TxWI.TXWI_N.TXBF_PT_SCA; } #endif } #endif /* TXBF_SUPPORT */ } /* fill 802.11 header */ #ifdef RALINK_QA if (pATEInfo->bQATxStart == TRUE) { NdisMoveMemory(pDMAHeaderBufVA + TXWISize, pATEInfo->Header, pATEInfo->HLen); } else #endif /* RALINK_QA */ { pATEInfo->HLen = LENGTH_802_11; #ifdef TXBF_SUPPORT TemplateFrame[0] = 0x08; /* Data */ TemplateFrame[1] = 0x00; if (pATEInfo->bTxBF && pATEInfo->txSoundingMode!=0) { /* QoS Data */ //pATEInfo->HLen = 32; pATEInfo->HLen = 30; TemplateFrame[0] = 0x88; TemplateFrame[1] = 0x80; switch (pATEInfo->txSoundingMode) { case 1: /* Data Sounding */ TemplateFrame[28] = pAd->CommonCfg.ETxBfNoncompress? 0x80: 0xc0; TemplateFrame[29] = 0x00; break; case 2: case 3: /* 2 or 3 Stream NDP */ TemplateFrame[28] = pAd->CommonCfg.ETxBfNoncompress? 0x80: 0xc0; TemplateFrame[29] = 0x01; /* NDP Announce */ break; default: TemplateFrame[28] = TemplateFrame[29] = 0x0; } } #endif /* TXBF_SUPPORT */ NdisMoveMemory(pDMAHeaderBufVA + TXWISize, TemplateFrame, pATEInfo->HLen); NdisMoveMemory(pDMAHeaderBufVA + TXWISize + 4, pATEInfo->Addr1, MAC_ADDR_LEN); NdisMoveMemory(pDMAHeaderBufVA + TXWISize + 10, pATEInfo->Addr2, MAC_ADDR_LEN); NdisMoveMemory(pDMAHeaderBufVA + TXWISize + 16, pATEInfo->Addr3, MAC_ADDR_LEN); } #ifdef RT_BIG_ENDIAN RTMPFrameEndianChange(pAd, (((PUCHAR)pDMAHeaderBufVA) + TXWISize), DIR_READ, FALSE); #endif /* RT_BIG_ENDIAN */ /* alloc buffer for payload */ #ifdef RALINK_QA if ((pATEInfo->bQATxStart == TRUE) && (pATEInfo->DLen != 0)) { pPacket = RTMP_AllocateRxPacketBuffer(pAd, ((POS_COOKIE)(pAd->OS_Cookie))->pci_dev, pATEInfo->DLen + 0x100, FALSE, &AllocVa, &AllocPa); } else #endif /* RALINK_QA */ { pPacket = RTMP_AllocateRxPacketBuffer(pAd, ((POS_COOKIE)(pAd->OS_Cookie))->pci_dev, pATEInfo->TxLength, FALSE, &AllocVa, &AllocPa); } if (pPacket == NULL) { pATEInfo->TxCount = 0; DBGPRINT_ERR(("%s : fail to alloc packet space.\n", __FUNCTION__)); return -1; } pTxRing->Cell[TxIdx].pNextNdisPacket = pPacket; pDest = (PUCHAR) AllocVa; #ifdef RALINK_QA if ((pATEInfo->bQATxStart == TRUE) && (pATEInfo->DLen != 0)) { GET_OS_PKT_LEN(pPacket) = pATEInfo->DLen; #ifndef LINUX GET_OS_PKT_TOTAL_LEN(pPacket) = pATEInfo->DLen; #endif /* LIMUX */ } else #endif /* RALINK_QA */ { GET_OS_PKT_LEN(pPacket) = pATEInfo->TxLength - pATEInfo->HLen; #ifndef LINUX GET_OS_PKT_TOTAL_LEN(pPacket) = pATEInfo->TxLength - pATEInfo->HLen; #endif /* LINUX */ } /* prepare frame payload */ #ifdef RALINK_QA if ((pATEInfo->bQATxStart == TRUE) && (pATEInfo->DLen != 0)) { /* copy pattern to payload */ if ((pATEInfo->PLen != 0)) { for (pos = 0; pos < pATEInfo->DLen; pos += pATEInfo->PLen) { memcpy(GET_OS_PKT_DATAPTR(pPacket) + pos, pATEInfo->Pattern, pATEInfo->PLen); } } } else #endif /* RALINK_QA */ { for (pos = 0; pos < GET_OS_PKT_LEN(pPacket); pos++) { if ( pATEInfo->bFixedPayload ) { pDest[pos] = pATEInfo->Payload; // pDest[pos] = 0xA5; } else { pDest[pos] = RandomByte(pAd); } } } /* build Tx descriptor */ #ifndef RT_BIG_ENDIAN pTxD = (PTXD_STRUC) pTxRing->Cell[TxIdx].AllocVa; pTxInfo = (TXINFO_STRUC *)(pTxRing->Cell[TxIdx].AllocVa + sizeof(TXD_STRUC)); #else pDestTxD = (PTXD_STRUC)pTxRing->Cell[TxIdx].AllocVa; NdisMoveMemory(&tx_hw_info[0], (UCHAR *)pDestTxD, TXD_SIZE); pTxD = (TXD_STRUC *)&tx_hw_info[0]; pTxInfo = (TXINFO_STRUC *)(&tx_hw_info[0] + sizeof(TXD_STRUC)); #endif /* !RT_BIG_ENDIAN */ #ifdef RALINK_QA if (pATEInfo->bQATxStart == TRUE) { /* prepare TxD */ NdisZeroMemory(pTxD, TXD_SIZE); /* build Tx descriptor */ pTxD->SDPtr0 = RTMP_GetPhysicalAddressLow(pTxRing->Cell[TxIdx].DmaBuf.AllocPa); pTxD->SDLen0 = TXWISize + pATEInfo->HLen; pTxD->SDPtr1 = AllocPa; pTxD->SDLen1 = GET_OS_PKT_LEN(pPacket); pTxD->LastSec0 = (pTxD->SDLen1 == 0) ? 1 : 0; pTxD->LastSec1 = 1; ral_write_txd(pAd, pTxD, pTxInfo, FALSE, FIFO_EDCA); pDest = (PUCHAR)pTxWI; pDest += TXWISize; pHeader80211 = (PHEADER_802_11)pDest; /* modify sequence number... */ if (pATEInfo->TxDoneCount == 0) pATEInfo->seq = pHeader80211->Sequence; else pHeader80211->Sequence = ++pATEInfo->seq; } else #endif /* RALINK_QA */ { TX_BLK txblk; txblk.SrcBufLen = GET_OS_PKT_LEN(pPacket); txblk.pSrcBufData = AllocVa; NdisZeroMemory(pTxD, TXD_SIZE); /* build Tx descriptor */ pTxD->SDPtr0 = RTMP_GetPhysicalAddressLow (pTxRing->Cell[TxIdx].DmaBuf.AllocPa); pTxD->SDLen0 = TXWISize + pATEInfo->HLen /* LENGTH_802_11 */; pTxD->SDPtr1 = PCI_MAP_SINGLE(pAd, &txblk, 0, 1, RTMP_PCI_DMA_TODEVICE); pTxD->SDLen1 = GET_OS_PKT_LEN(pPacket); pTxD->LastSec0 = (pTxD->SDLen1 == 0) ? 1 : 0; pTxD->LastSec1 = 1; ral_write_txd(pAd, pTxD, pTxInfo, FALSE, FIFO_EDCA); } #ifdef RT_BIG_ENDIAN RTMPWIEndianChange(pAd, (PUCHAR)pTxWI, TYPE_TXWI); RTMPFrameEndianChange(pAd, (((PUCHAR)pDMAHeaderBufVA) + TXWISize), DIR_WRITE, FALSE); RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD); WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD); #endif /* RT_BIG_ENDIAN */ //#endif return 0; }
/* ======================================================================== Routine Description: For RF filter calibration purpose Arguments: pAd Pointer to our adapter Return Value: None IRQL = PASSIVE_LEVEL ======================================================================== */ VOID RTMPFilterCalibration( IN PRTMP_ADAPTER pAd) { UCHAR R55x = 0, value, FilterTarget = 0x1E, BBPValue=0; UINT loop = 0, count = 0, loopcnt = 0, ReTry = 0; UCHAR RF_R24_Value = 0; #ifdef RT3593 if (IS_RT3593(pAd)) { return; } else #endif // RT3593 // { // Give bbp filter initial value pAd->Mlme.CaliBW20RfR24 = 0x1F; pAd->Mlme.CaliBW40RfR24 = 0x2F; //Bit[5] must be 1 for BW 40 do { if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)) return; if (loop == 1) //BandWidth = 40 MHz { // Write 0x27 to RF_R24 to program filter RT30xxReadRFRegister(pAd, RF_R24, (PUCHAR)(&RF_R24_Value)); RF_R24_Value = (RF_R24_Value & 0xC0) | 0x27; // <bit 5>:tx_h20M<bit 5> and <bit 4:0>:tx_agc_fc<bit 4:0> RT30xxWriteRFRegister(pAd, RF_R24, RF_R24_Value); if (IS_RT3071(pAd) || IS_RT3572(pAd)) FilterTarget = 0x15; else FilterTarget = 0x19; // when calibrate BW40, BBP mask must set to BW40. RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &BBPValue); BBPValue&= (~0x18); BBPValue|= (0x10); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, BBPValue); // set to BW40 RT30xxReadRFRegister(pAd, RF_R31, &value); value |= 0x20; RT30xxWriteRFRegister(pAd, RF_R31, value); } else //BandWidth = 20 MHz { // Write 0x07 to RF_R24 to program filter RT30xxReadRFRegister(pAd, RF_R24, (PUCHAR)(&RF_R24_Value)); RF_R24_Value = (RF_R24_Value & 0xC0) | 0x07; // <bit 5>:tx_h20M<bit 5> and <bit 4:0>:tx_agc_fc<bit 4:0> RT30xxWriteRFRegister(pAd, RF_R24, RF_R24_Value); if (IS_RT3071(pAd) || IS_RT3572(pAd)) FilterTarget = 0x13; else FilterTarget = 0x16; // set to BW20 RT30xxReadRFRegister(pAd, RF_R31, &value); value &= (~0x20); RT30xxWriteRFRegister(pAd, RF_R31, value); } // Write 0x01 to RF_R22 to enable baseband loopback mode RT30xxReadRFRegister(pAd, RF_R22, &value); value |= 0x01; RT30xxWriteRFRegister(pAd, RF_R22, value); // Write 0x00 to BBP_R24 to set power & frequency of passband test tone RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R24, 0); do { if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)) return; // Write 0x90 to BBP_R25 to transmit test tone RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R25, 0x90); RTMPusecDelay(1000); // Read BBP_R55[6:0] for received power, set R55x = BBP_R55[6:0] RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R55, &value); R55x = value & 0xFF; } while ((ReTry++ < 100) && (R55x == 0)); // Write 0x06 to BBP_R24 to set power & frequency of stopband test tone RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R24, 0x06); while(TRUE) { if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)) return; // Write 0x90 to BBP_R25 to transmit test tone RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R25, 0x90); //We need to wait for calibration RTMPusecDelay(1000); RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R55, &value); value &= 0xFF; if ((R55x - value) < FilterTarget) { RF_R24_Value ++; } else if ((R55x - value) == FilterTarget) { RF_R24_Value ++; count ++; } else { break; } // prevent infinite loop cause driver hang. if (loopcnt++ > 100) { DBGPRINT(RT_DEBUG_ERROR, ("RTMPFilterCalibration - can't find a valid value, loopcnt=%d stop calibrating", loopcnt)); break; } // Write RF_R24 to program filter RT30xxWriteRFRegister(pAd, RF_R24, RF_R24_Value); } if (count > 0) { RF_R24_Value = RF_R24_Value - ((count) ? (1) : (0)); } // Store for future usage if (loopcnt < 100) { if (loop++ == 0) { //BandWidth = 20 MHz pAd->Mlme.CaliBW20RfR24 = (UCHAR)RF_R24_Value; } else { //BandWidth = 40 MHz pAd->Mlme.CaliBW40RfR24 = (UCHAR)RF_R24_Value; break; } } else break; RT30xxWriteRFRegister(pAd, RF_R24, RF_R24_Value); // reset count count = 0; } while(TRUE); // // Set back to initial state // RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R24, 0); RT30xxReadRFRegister(pAd, RF_R22, &value); value &= ~(0x01); RT30xxWriteRFRegister(pAd, RF_R22, value); // set BBP back to BW20 RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &BBPValue); BBPValue&= (~0x18); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, BBPValue); DBGPRINT(RT_DEBUG_TRACE, ("RTMPFilterCalibration - CaliBW20RfR24=0x%x, CaliBW40RfR24=0x%x\n", pAd->Mlme.CaliBW20RfR24, pAd->Mlme.CaliBW40RfR24)); } }
INT ATESetUpNDPAFrame( IN PRTMP_ADAPTER pAd, IN UINT32 TxIdx) { PATE_INFO pATEInfo = &(pAd->ate); UINT pos = 0; TXINFO_STRUC *pTxInfo; TXD_STRUC *pTxD; #ifdef RT_BIG_ENDIAN TXD_STRUC *pDestTxD; UCHAR tx_hw_info[TXD_SIZE]; #endif /* RT_BIG_ENDIAN */ PNDIS_PACKET pPacket=NULL; PUCHAR pDest=NULL; PVOID AllocVa=NULL; NDIS_PHYSICAL_ADDRESS AllocPa; HTTRANSMIT_SETTING TxHTPhyMode; UCHAR *buf; VHT_NDPA_FRAME *vht_ndpa; SNDING_STA_INFO *sta_info; RTMP_TX_RING *pTxRing = &pAd->TxRing[QID_AC_BE]; TXWI_STRUC *pTxWI = (TXWI_STRUC *)pTxRing->Cell[TxIdx].DmaBuf.AllocVa; PUCHAR pDMAHeaderBufVA = (PUCHAR) pTxRing->Cell[TxIdx].DmaBuf.AllocVa; UINT8 TXWISize = pAd->chipCap.TXWISize; #ifdef RALINK_QA PHEADER_802_11 pHeader80211; #endif /* RALINK_QA */ UCHAR bw, sgi, stbc, mcs, phy_mode, frag, cfack, ts, ampdu, ack, nseq, bawinsize, pkt_id, txop; USHORT byte_cnt; bw = sgi = stbc = mcs = phy_mode = frag = cfack = ts =0; ampdu = ack = nseq = bawinsize = pkt_id = txop = 0; byte_cnt = 0; #ifdef RLT_MAC if (pAd->chipCap.hif_type == HIF_RLT) { bw = pATEInfo->TxWI.TXWI_N.BW; sgi = pATEInfo->TxWI.TXWI_N.ShortGI; stbc = pATEInfo->TxWI.TXWI_N.STBC; mcs = pATEInfo->TxWI.TXWI_N.MCS; phy_mode = pATEInfo->TxWI.TXWI_N.PHYMODE; frag = pATEInfo->TxWI.TXWI_N.FRAG; cfack = pATEInfo->TxWI.TXWI_N.CFACK, ts = pATEInfo->TxWI.TXWI_N.TS; ampdu = pATEInfo->TxWI.TXWI_N.AMPDU; ack = pATEInfo->TxWI.TXWI_N.ACK; nseq = pATEInfo->TxWI.TXWI_N.NSEQ; bawinsize =pATEInfo->TxWI.TXWI_N.BAWinSize; byte_cnt = pATEInfo->TxWI.TXWI_N.MPDUtotalByteCnt; pkt_id = pATEInfo->TxWI.TXWI_N.TxPktId; txop = pATEInfo->TxWI.TXWI_N.txop; cfack = pATEInfo->TxWI.TXWI_N.CFACK; } #endif /* RLT_MAC */ #ifdef RTMP_MAC if (pAd->chipCap.hif_type == HIF_RTMP) { bw = pATEInfo->TxWI.TXWI_O.BW; sgi = pATEInfo->TxWI.TXWI_O.ShortGI; stbc = pATEInfo->TxWI.TXWI_O.STBC; mcs = pATEInfo->TxWI.TXWI_O.MCS; phy_mode = pATEInfo->TxWI.TXWI_O.PHYMODE; frag = pATEInfo->TxWI.TXWI_O.FRAG; cfack = pATEInfo->TxWI.TXWI_O.CFACK, ts = pATEInfo->TxWI.TXWI_O.TS; ampdu = pATEInfo->TxWI.TXWI_O.AMPDU; ack = pATEInfo->TxWI.TXWI_O.ACK; nseq = pATEInfo->TxWI.TXWI_O.NSEQ; bawinsize =pATEInfo->TxWI.TXWI_O.BAWinSize; byte_cnt = pATEInfo->TxWI.TXWI_O.MPDUtotalByteCnt; pkt_id = pATEInfo->TxWI.TXWI_O.PacketId; txop = pATEInfo->TxWI.TXWI_O.txop; cfack = pATEInfo->TxWI.TXWI_O.CFACK; } #endif /* RTMP_MAC */ /* fill TxWI */ TxHTPhyMode.field.BW = bw; TxHTPhyMode.field.ShortGI = sgi; TxHTPhyMode.field.STBC = stbc; TxHTPhyMode.field.MCS = mcs; TxHTPhyMode.field.MODE = phy_mode; if (pATEInfo->bQATxStart == TRUE) { /* always use QID_AC_BE and FIFO_EDCA */ ATEWriteTxWI(pAd, pTxWI, frag, cfack, ts, ampdu, ack, nseq, bawinsize, 0, byte_cnt, pkt_id, 0, 0, txop, cfack, &TxHTPhyMode); #ifdef TXBF_SUPPORT #ifdef RTMP_MAC if (IS_RT2883(pAd) || IS_RT3883(pAd) || IS_RT3593(pAd)) { /* Must copy rsv bits to actual TxWI */ //pTxWI->TXWI_O.rsv = pATEInfo->TxWI.TXWI_O.rsv; pTxWI->TXWI_O.iTxBF = pATEInfo->TxWI.TXWI_O.iTxBF; pTxWI->TXWI_O.Sounding = pATEInfo->TxWI.TXWI_O.Sounding; pTxWI->TXWI_O.eTxBF = pATEInfo->TxWI.TXWI_O.eTxBF; pTxWI->TXWI_O.Autofallback = pATEInfo->TxWI.TXWI_O.Autofallback; pTxWI->TXWI_O.NDPSndBW = pATEInfo->TxWI.TXWI_O.NDPSndBW; pTxWI->TXWI_O.NDPSndRate = pATEInfo->TxWI.TXWI_O.NDPSndRate; } #endif #ifdef RLT_MAC if (IS_MT76x2(pAd)) { /* Must copy rsv bits to actual TxWI */ pTxWI->TXWI_N.Rsv4 = pATEInfo->TxWI.TXWI_N.Rsv4; pTxWI->TXWI_N.iTxBF = pATEInfo->TxWI.TXWI_N.iTxBF; pTxWI->TXWI_N.Sounding = pATEInfo->TxWI.TXWI_N.Sounding; pTxWI->TXWI_N.eTxBF = pATEInfo->TxWI.TXWI_N.eTxBF; //pTxWI->TXWI_N.Autofallback = pATEInfo->TxWI.TXWI_N.Autofallback; pTxWI->TXWI_N.NDPSndBW = pATEInfo->TxWI.TXWI_N.NDPSndBW; pTxWI->TXWI_N.NDPSndRate = pATEInfo->TxWI.TXWI_N.NDPSndRate; pTxWI->TXWI_N.TXBF_PT_SCA = pATEInfo->TxWI.TXWI_N.TXBF_PT_SCA; } #endif #endif /* TXBF_SUPPORT */ } else { ATEWriteTxWI(pAd, pTxWI, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, 4, 0, pATEInfo->TxLength, 0, 0, 0, IFS_HTTXOP, FALSE, &TxHTPhyMode); #ifdef TXBF_SUPPORT if (pATEInfo->bTxBF == 1) { #ifdef RTMP_MAC if (IS_RT2883(pAd) || IS_RT3883(pAd) || IS_RT3593(pAd)) { //pTxWI->TXWI_O.rsv = 0; pTxWI->TXWI_O.iTxBF = pATEInfo->TxWI.TXWI_O.iTxBF; pTxWI->TXWI_O.Sounding = (pATEInfo->txSoundingMode == 1 ? 1 : 0); pTxWI->TXWI_O.eTxBF = pATEInfo->TxWI.TXWI_O.eTxBF; pTxWI->TXWI_O.Autofallback = pATEInfo->TxWI.TXWI_O.Autofallback; pTxWI->TXWI_O.NDPSndBW = pATEInfo->TxWI.TXWI_O.BW; if (pATEInfo->txSoundingMode == 3) pTxWI->TXWI_O.NDPSndRate = 2; else if (pATEInfo->txSoundingMode == 2) pTxWI->TXWI_O.NDPSndRate = 1; else pTxWI->TXWI_O.NDPSndRate = 0; } #endif #ifdef RLT_MAC if (IS_MT76x2(pAd)) { pTxWI->TXWI_N.Rsv4 = 0; pTxWI->TXWI_N.iTxBF = pATEInfo->TxWI.TXWI_N.iTxBF; pTxWI->TXWI_N.Sounding = (pATEInfo->txSoundingMode == 1 ? 1 : 0); pTxWI->TXWI_N.eTxBF = pATEInfo->TxWI.TXWI_N.eTxBF; //pTxWI->TXWI_N.Autofallback = pATEInfo->TxWI.TXWI_N.Autofallback; pTxWI->TXWI_N.NDPSndBW = pATEInfo->TxWI.TXWI_N.BW; if (pATEInfo->txSoundingMode == 3) pTxWI->TXWI_N.NDPSndRate = 2; else if (pATEInfo->txSoundingMode == 2) pTxWI->TXWI_N.NDPSndRate = 1; else pTxWI->TXWI_N.NDPSndRate = 0; pTxWI->TXWI_N.TXBF_PT_SCA = pATEInfo->TxWI.TXWI_N.TXBF_PT_SCA; } #endif } #endif /* TXBF_SUPPORT */ } /* fill 802.11 header */ #ifdef RALINK_QA if (pATEInfo->bQATxStart == TRUE) { NdisMoveMemory(pDMAHeaderBufVA + TXWISize, pATEInfo->Header, pATEInfo->HLen); } else #endif /* RALINK_QA */ { buf = (pDMAHeaderBufVA + TXWISize); vht_ndpa = (VHT_NDPA_FRAME *)buf; pATEInfo->HLen = sizeof(VHT_NDPA_FRAME); vht_ndpa->fc.Type = FC_TYPE_CNTL; vht_ndpa->fc.SubType = SUBTYPE_VHT_NDPA; COPY_MAC_ADDR(vht_ndpa->ra, pATEInfo->Addr1); COPY_MAC_ADDR(vht_ndpa->ta, pATEInfo->Addr3); hex_dump("NDPA Frame",buf,pATEInfo->HLen); /* Currnetly we only support 1 STA for a VHT DNPA */ sta_info = vht_ndpa->sta_info; sta_info->aid12 = 1; sta_info->fb_type = SNDING_FB_SU; sta_info->nc_idx = 0; vht_ndpa->token.token_num = 0; vht_ndpa->duration = 100; } #ifdef RT_BIG_ENDIAN RTMPFrameEndianChange(pAd, (((PUCHAR)pDMAHeaderBufVA) + TXWISize), DIR_READ, FALSE); #endif /* RT_BIG_ENDIAN */ /* alloc buffer for payload */ #ifdef RALINK_QA if ((pATEInfo->bQATxStart == TRUE) && (pATEInfo->DLen != 0)) { pPacket = RTMP_AllocateRxPacketBuffer(pAd, ((POS_COOKIE)(pAd->OS_Cookie))->pci_dev, pATEInfo->DLen + 0x100, FALSE, &AllocVa, &AllocPa); } else #endif /* RALINK_QA */ { pPacket = RTMP_AllocateRxPacketBuffer(pAd, ((POS_COOKIE)(pAd->OS_Cookie))->pci_dev, pATEInfo->TxLength, FALSE, &AllocVa, &AllocPa); } if (pPacket == NULL) { pATEInfo->TxCount = 0; DBGPRINT_ERR(("%s : fail to alloc packet space.\n", __FUNCTION__)); return -1; } pTxRing->Cell[TxIdx].pNextNdisPacket = pPacket; pDest = (PUCHAR) AllocVa; #ifdef RALINK_QA if ((pATEInfo->bQATxStart == TRUE) && (pATEInfo->DLen != 0)) { GET_OS_PKT_LEN(pPacket) = pATEInfo->DLen; #ifndef LINUX GET_OS_PKT_TOTAL_LEN(pPacket) = pATEInfo->DLen; #endif /* LIMUX */ } else #endif /* RALINK_QA */ { GET_OS_PKT_LEN(pPacket) = pATEInfo->TxLength - pATEInfo->HLen; #ifndef LINUX GET_OS_PKT_TOTAL_LEN(pPacket) = pATEInfo->TxLength - pATEInfo->HLen; #endif /* LINUX */ } /* prepare frame payload */ #ifdef RALINK_QA if ((pATEInfo->bQATxStart == TRUE) && (pATEInfo->DLen != 0)) { /* copy pattern to payload */ if ((pATEInfo->PLen != 0)) { for (pos = 0; pos < pATEInfo->DLen; pos += pATEInfo->PLen) { memcpy(GET_OS_PKT_DATAPTR(pPacket) + pos, pATEInfo->Pattern, pATEInfo->PLen); } } } else #endif /* RALINK_QA */ { for (pos = 0; pos < GET_OS_PKT_LEN(pPacket); pos++) { pDest[pos] = 0x00; } } /* build Tx descriptor */ #ifndef RT_BIG_ENDIAN pTxD = (PTXD_STRUC) pTxRing->Cell[TxIdx].AllocVa; pTxInfo = (TXINFO_STRUC *)(pTxRing->Cell[TxIdx].AllocVa + sizeof(TXD_STRUC)); #else pDestTxD = (PTXD_STRUC)pTxRing->Cell[TxIdx].AllocVa; NdisMoveMemory(&tx_hw_info[0], (UCHAR *)pDestTxD, TXD_SIZE); pTxD = (TXD_STRUC *)&tx_hw_info[0]; pTxInfo = (TXINFO_STRUC *)(&tx_hw_info[0] + sizeof(TXD_STRUC)); #endif /* !RT_BIG_ENDIAN */ #ifdef RALINK_QA if (pATEInfo->bQATxStart == TRUE) { /* prepare TxD */ NdisZeroMemory(pTxD, TXD_SIZE); /* build Tx descriptor */ pTxD->SDPtr0 = RTMP_GetPhysicalAddressLow(pTxRing->Cell[TxIdx].DmaBuf.AllocPa); pTxD->SDLen0 = TXWISize + pATEInfo->HLen; pTxD->SDPtr1 = AllocPa; pTxD->SDLen1 = GET_OS_PKT_LEN(pPacket); pTxD->LastSec0 = (pTxD->SDLen1 == 0) ? 1 : 0; pTxD->LastSec1 = 1; ral_write_txd(pAd, pTxD, pTxInfo, FALSE, FIFO_EDCA); pDest = (PUCHAR)pTxWI; pDest += TXWISize; pHeader80211 = (PHEADER_802_11)pDest; /* modify sequence number... */ if (pATEInfo->TxDoneCount == 0) pATEInfo->seq = pHeader80211->Sequence; else pHeader80211->Sequence = ++pATEInfo->seq; } else #endif /* RALINK_QA */ { TX_BLK txblk; txblk.SrcBufLen = GET_OS_PKT_LEN(pPacket); txblk.pSrcBufData = AllocVa; NdisZeroMemory(pTxD, TXD_SIZE); /* build Tx descriptor */ pTxD->SDPtr0 = RTMP_GetPhysicalAddressLow (pTxRing->Cell[TxIdx].DmaBuf.AllocPa); pTxD->SDLen0 = TXWISize + pATEInfo->HLen /* LENGTH_802_11 */; pTxD->SDPtr1 = PCI_MAP_SINGLE(pAd, &txblk, 0, 1, RTMP_PCI_DMA_TODEVICE); pTxD->SDLen1 = GET_OS_PKT_LEN(pPacket); pTxD->LastSec0 = (pTxD->SDLen1 == 0) ? 1 : 0; pTxD->LastSec1 = 1; ral_write_txd(pAd, pTxD, pTxInfo, FALSE, FIFO_EDCA); } #ifdef RT_BIG_ENDIAN RTMPWIEndianChange(pAd, (PUCHAR)pTxWI, TYPE_TXWI); RTMPFrameEndianChange(pAd, (((PUCHAR)pDMAHeaderBufVA) + TXWISize), DIR_WRITE, FALSE); RTMPDescriptorEndianChange((PUCHAR)pTxD, TYPE_TXD); WriteBackToDescriptor((PUCHAR)pDestTxD, (PUCHAR)pTxD, FALSE, TYPE_TXD); #endif /* RT_BIG_ENDIAN */ return 0; }
VOID RT35xx_ChipBBPAdjust( IN RTMP_ADAPTER *pAd) { UINT32 Value; UCHAR byteValue = 0; #ifdef RT3593 /* 3x3 device will not run AsicEvaluateRxAnt*/ if (IS_RT3593(pAd)) { UCHAR BBPValue = 0; /* Receiver Antenna Selection*/ RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BBPValue); if(pAd->Antenna.field.RxPath == 3) { BBPValue |= (0x10); } else if(pAd->Antenna.field.RxPath == 2) { BBPValue |= (0x8); } else if(pAd->Antenna.field.RxPath == 1) { BBPValue |= (0x0); } RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BBPValue); /*Number of transmitter chains*/ RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R1, &BBPValue); BBPValue &= (~0x18); if (pAd->Antenna.field.TxPath == 3) BBPValue |= 0x10; else if (pAd->Antenna.field.TxPath == 2) BBPValue |= 0x08; RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R1, BBPValue); } #endif /* RT3593 */ #ifdef DOT11_N_SUPPORT if ((pAd->CommonCfg.HtCapability.HtCapInfo.ChannelWidth == BW_40) && (pAd->CommonCfg.RegTransmitSetting.field.EXTCHA == EXTCHA_ABOVE)) { pAd->CommonCfg.BBPCurrentBW = BW_40; pAd->CommonCfg.CentralChannel = pAd->CommonCfg.Channel + 2; /* TX : control channel at lower */ RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value); Value &= (~0x1); RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value); /* RX : control channel at lower */ RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &byteValue); byteValue &= (~0x20); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, byteValue); RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &byteValue); byteValue &= (~0x18); byteValue |= 0x10; RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, byteValue); if (pAd->CommonCfg.Channel > 14) { /* request by Gary 20070208 for middle and long range A Band*/ if (IS_RT3572(pAd)) AsicBBPWriteWithRxChain(pAd, BBP_R66, 0x48, RX_CHAIN_ALL); } else { /* request by Gary 20070208 for middle and long range G Band*/ if (IS_RT3572(pAd)) AsicBBPWriteWithRxChain(pAd, BBP_R66, 0x38, RX_CHAIN_ALL); } if (pAd->MACVersion == 0x28600100) { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x1A); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, 0x0A); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x16); } else { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x12); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, 0x0A); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x10); } DBGPRINT(RT_DEBUG_TRACE, ("ApStartUp : ExtAbove, ChannelWidth=%d, Channel=%d, ExtChanOffset=%d(%d) \n", pAd->CommonCfg.HtCapability.HtCapInfo.ChannelWidth, pAd->CommonCfg.Channel, pAd->CommonCfg.RegTransmitSetting.field.EXTCHA, pAd->CommonCfg.AddHTInfo.AddHtInfo.ExtChanOffset)); } else if ((pAd->CommonCfg.Channel > 2) && (pAd->CommonCfg.HtCapability.HtCapInfo.ChannelWidth == BW_40) && (pAd->CommonCfg.RegTransmitSetting.field.EXTCHA == EXTCHA_BELOW)) { pAd->CommonCfg.BBPCurrentBW = BW_40; if (pAd->CommonCfg.Channel == 14) pAd->CommonCfg.CentralChannel = pAd->CommonCfg.Channel - 1; else pAd->CommonCfg.CentralChannel = pAd->CommonCfg.Channel - 2; /* TX : control channel at upper */ RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value); Value |= (0x1); RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value); /* RX : control channel at upper */ RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &byteValue); byteValue |= (0x20); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, byteValue); RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &byteValue); byteValue &= (~0x18); byteValue |= 0x10; RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, byteValue); if (pAd->CommonCfg.Channel > 14) { /* request by Gary 20070208 for middle and long range A Band*/ if (IS_RT3572(pAd)) AsicBBPWriteWithRxChain(pAd, BBP_R66, 0x48, RX_CHAIN_ALL); } else { /* request by Gary 20070208 for middle and long range G band*/ if (IS_RT3572(pAd)) AsicBBPWriteWithRxChain(pAd, BBP_R66, 0x38, RX_CHAIN_ALL); } if (pAd->MACVersion == 0x28600100) { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x1A); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, 0x0A); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x16); } else { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x12); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, 0x0A); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x10); } DBGPRINT(RT_DEBUG_TRACE, ("ApStartUp : ExtBlow, ChannelWidth=%d, Channel=%d, ExtChanOffset=%d(%d) \n", pAd->CommonCfg.HtCapability.HtCapInfo.ChannelWidth, pAd->CommonCfg.Channel, pAd->CommonCfg.RegTransmitSetting.field.EXTCHA, pAd->CommonCfg.AddHTInfo.AddHtInfo.ExtChanOffset)); } else #endif /* DOT11_N_SUPPORT */ { pAd->CommonCfg.BBPCurrentBW = BW_20; pAd->CommonCfg.CentralChannel = pAd->CommonCfg.Channel; /* TX : control channel at lower */ RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value); Value &= (~0x1); RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value); RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &byteValue); byteValue &= (~0x18); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, byteValue); /* 20 MHz bandwidth*/ if (pAd->CommonCfg.Channel > 14) { /* request by Gary 20070208*/ if (IS_RT3572(pAd)) AsicBBPWriteWithRxChain(pAd, BBP_R66, 0x40, RX_CHAIN_ALL); } else { /* request by Gary 20070208*/ /*RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, 0x30);*/ /* request by Brian 20070306*/ if (IS_RT3572(pAd)) AsicBBPWriteWithRxChain(pAd, BBP_R66, 0x38, RX_CHAIN_ALL); } if (pAd->MACVersion == 0x28600100) { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x16); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, 0x08); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x11); } else { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x12); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, 0x0a); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x10); } #ifdef DOT11_N_SUPPORT DBGPRINT(RT_DEBUG_TRACE, ("ApStartUp : 20MHz, ChannelWidth=%d, Channel=%d, ExtChanOffset=%d(%d) \n", pAd->CommonCfg.HtCapability.HtCapInfo.ChannelWidth, pAd->CommonCfg.Channel, pAd->CommonCfg.RegTransmitSetting.field.EXTCHA, pAd->CommonCfg.AddHTInfo.AddHtInfo.ExtChanOffset)); #endif /* DOT11_N_SUPPORT */ } if (pAd->CommonCfg.Channel > 14) { /* request by Gary 20070208 for middle and long range A Band*/ RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, 0x1D); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, 0x1D); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, 0x1D); /*RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0x1D);*/ } else { /* request by Gary 20070208 for middle and long range G band*/ RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, 0x2D); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, 0x2D); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, 0x2D); /*RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0x2D);*/ } }
RTMP_BUILD_DRV_OPS_FUNCTION_BODY #endif /* OS_ABL_FUNC_SUPPORT */ #endif /* LINUX */ int rt28xx_init( IN VOID *pAdSrc, IN PSTRING pDefaultMac, IN PSTRING pHostName) { PRTMP_ADAPTER pAd = (PRTMP_ADAPTER)pAdSrc; UINT index; UCHAR TmpPhy; NDIS_STATUS Status; if (pAd == NULL) return FALSE; /* reset Adapter flags*/ RTMP_CLEAR_FLAGS(pAd); /* Init BssTab & ChannelInfo tabbles for auto channel select.*/ #ifdef CONFIG_AP_SUPPORT IF_DEV_CONFIG_OPMODE_ON_AP(pAd) { AutoChBssTableInit(pAd); ChannelInfoInit(pAd); } #endif /* CONFIG_AP_SUPPORT */ #ifdef DOT11_N_SUPPORT /* Allocate BA Reordering memory*/ if (ba_reordering_resource_init(pAd, MAX_REORDERING_MPDU_NUM) != TRUE) goto err1; #endif /* DOT11_N_SUPPORT */ /* Make sure MAC gets ready.*/ index = 0; if (WaitForAsicReady(pAd) != TRUE) goto err1; DBGPRINT(RT_DEBUG_TRACE, ("MAC[Ver:Rev=0x%08x]\n", pAd->MACVersion)); if (MAX_LEN_OF_MAC_TABLE > MAX_AVAILABLE_CLIENT_WCID(pAd)) { DBGPRINT(RT_DEBUG_ERROR, ("MAX_LEN_OF_MAC_TABLE can not be larger than MAX_AVAILABLE_CLIENT_WCID!!!!\n")); goto err1; } #ifdef RTMP_MAC_PCI #if defined(RT3090) || defined(RT3592) || defined(RT3390) || defined(RT3593) || defined(RT5390) || defined(RT5392) || defined(RT5592) /*Iverson patch PCIE L1 issue to make sure that driver can be read,write ,BBP and RF register at pcie L.1 level */ if ((IS_RT3090(pAd) || IS_RT3572(pAd) ||IS_RT3390(pAd) || IS_RT3593(pAd) || IS_RT5390(pAd) || IS_RT5392(pAd) || IS_RT5592(pAd)) &&pAd->infType==RTMP_DEV_INF_PCIE) { UINT32 MacValue = 0; RTMP_IO_READ32(pAd, AUX_CTRL, &MacValue); MacValue |= 0x402; RTMP_IO_WRITE32(pAd, AUX_CTRL, MacValue); DBGPRINT(RT_DEBUG_TRACE, ("AUX_CTRL = 0x%x\n", MacValue)); } #endif /* To fix driver disable/enable hang issue when radio off*/ RTMP_IO_WRITE32(pAd, PWR_PIN_CFG, 0x2); #endif /* RTMP_MAC_PCI */ /* Disable DMA*/ RT28XXDMADisable(pAd); /* Load 8051 firmware*/ Status = NICLoadFirmware(pAd); if (Status != NDIS_STATUS_SUCCESS) { DBGPRINT_ERR(("NICLoadFirmware failed, Status[=0x%08x]\n", Status)); goto err1; } NICLoadRateSwitchingParams(pAd); /* Disable interrupts here which is as soon as possible*/ /* This statement should never be true. We might consider to remove it later*/ #ifdef RTMP_MAC_PCI if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_ACTIVE)) { RTMP_ASIC_INTERRUPT_DISABLE(pAd); } #endif /* RTMP_MAC_PCI */ #ifdef RESOURCE_PRE_ALLOC Status = RTMPInitTxRxRingMemory(pAd); #else Status = RTMPAllocTxRxRingMemory(pAd); #endif /* RESOURCE_PRE_ALLOC */ if (Status != NDIS_STATUS_SUCCESS) { DBGPRINT_ERR(("RTMPAllocTxRxMemory failed, Status[=0x%08x]\n", Status)); goto err2; } RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_IN_USE); /* initialize MLME*/ Status = RtmpMgmtTaskInit(pAd); if (Status != NDIS_STATUS_SUCCESS) goto err3; Status = MlmeInit(pAd); if (Status != NDIS_STATUS_SUCCESS) { DBGPRINT_ERR(("MlmeInit failed, Status[=0x%08x]\n", Status)); goto err4; } #ifdef RT_SOC_SUPPORT #ifdef VIDEO_TURBINE_SUPPORT VideoConfigInit(pAd); #endif /* VIDEO_TURBINE_SUPPORT */ #endif /* RT_SOC_SUPPORT */ /* Initialize pAd->StaCfg, pAd->ApCfg, pAd->CommonCfg to manufacture default*/ UserCfgInit(pAd); Status = RtmpNetTaskInit(pAd); if (Status != NDIS_STATUS_SUCCESS) goto err5; /* COPY_MAC_ADDR(pAd->ApCfg.MBSSID[apidx].Bssid, netif->hwaddr);*/ /* pAd->bForcePrintTX = TRUE;*/ CfgInitHook(pAd); #ifdef CONFIG_AP_SUPPORT if ((pAd->OpMode == OPMODE_AP) ) APInitialize(pAd); #endif /* CONFIG_AP_SUPPORT */ #ifdef BLOCK_NET_IF initblockQueueTab(pAd); #endif /* BLOCK_NET_IF */ Status = MeasureReqTabInit(pAd); if (Status != NDIS_STATUS_SUCCESS) { DBGPRINT_ERR(("MeasureReqTabInit failed, Status[=0x%08x]\n",Status)); goto err6; } Status = TpcReqTabInit(pAd); if (Status != NDIS_STATUS_SUCCESS) { DBGPRINT_ERR(("TpcReqTabInit failed, Status[=0x%08x]\n",Status)); goto err6; } /* Init the hardware, we need to init asic before read registry, otherwise mac register will be reset*/ Status = NICInitializeAdapter(pAd, TRUE); if (Status != NDIS_STATUS_SUCCESS) { DBGPRINT_ERR(("NICInitializeAdapter failed, Status[=0x%08x]\n", Status)); if (Status != NDIS_STATUS_SUCCESS) goto err6; } #ifdef CONFIG_AP_SUPPORT IF_DEV_CONFIG_OPMODE_ON_AP(pAd) { } #endif /* CONFIG_AP_SUPPORT */ /* Read parameters from Config File */ /* unknown, it will be updated in NICReadEEPROMParameters */ pAd->RfIcType = RFIC_UNKNOWN; Status = RTMPReadParametersHook(pAd); /* Set eeprom related hook functions */ Status = RtmpChipOpsEepromHook(pAd, pAd->infType); DBGPRINT(RT_DEBUG_OFF, ("1. Phy Mode = %d\n", pAd->CommonCfg.PhyMode)); if (Status != NDIS_STATUS_SUCCESS) { DBGPRINT_ERR(("RTMPReadParametersHook failed, Status[=0x%08x]\n",Status)); goto err6; } #ifdef DOT11_N_SUPPORT /*Init Ba Capability parameters.*/ /* RT28XX_BA_INIT(pAd);*/ pAd->CommonCfg.DesiredHtPhy.MpduDensity = (UCHAR)pAd->CommonCfg.BACapability.field.MpduDensity; pAd->CommonCfg.DesiredHtPhy.AmsduEnable = (USHORT)pAd->CommonCfg.BACapability.field.AmsduEnable; pAd->CommonCfg.DesiredHtPhy.AmsduSize = (USHORT)pAd->CommonCfg.BACapability.field.AmsduSize; pAd->CommonCfg.DesiredHtPhy.MimoPs = (USHORT)pAd->CommonCfg.BACapability.field.MMPSmode; /* UPdata to HT IE*/ pAd->CommonCfg.HtCapability.HtCapInfo.MimoPs = (USHORT)pAd->CommonCfg.BACapability.field.MMPSmode; pAd->CommonCfg.HtCapability.HtCapInfo.AMsduSize = (USHORT)pAd->CommonCfg.BACapability.field.AmsduSize; pAd->CommonCfg.HtCapability.HtCapParm.MpduDensity = (UCHAR)pAd->CommonCfg.BACapability.field.MpduDensity; #endif /* DOT11_N_SUPPORT */ /* after reading Registry, we now know if in AP mode or STA mode*/ /* Load 8051 firmware; crash when FW image not existent*/ /* Status = NICLoadFirmware(pAd);*/ /* if (Status != NDIS_STATUS_SUCCESS)*/ /* break;*/ DBGPRINT(RT_DEBUG_OFF, ("2. Phy Mode = %d\n", pAd->CommonCfg.PhyMode)); /* We should read EEPROM for all cases. rt2860b*/ NICReadEEPROMParameters(pAd, (PSTRING)pDefaultMac); DBGPRINT(RT_DEBUG_OFF, ("3. Phy Mode = %d\n", pAd->CommonCfg.PhyMode)); #ifdef LED_CONTROL_SUPPORT /* Send LED Setting to MCU */ RTMPInitLEDMode(pAd); #endif /* LED_CONTROL_SUPPORT */ NICInitAsicFromEEPROM(pAd); /* rt2860b */ #ifdef RALINK_ATE if (ATEInit(pAd) != NDIS_STATUS_SUCCESS) { DBGPRINT(RT_DEBUG_ERROR, ("%s(): ATE initialization failed !\n", __FUNCTION__)); goto err6; } #endif /* RALINK_ATE */ #ifdef RTMP_FREQ_CALIBRATION_SUPPORT #endif /* RTMP_FREQ_CALIBRATION_SUPPORT */ #ifdef RTMP_INTERNAL_TX_ALC /* Initialize the desired TSSI table*/ RTMP_CHIP_ASIC_TSSI_TABLE_INIT(pAd); #endif /* RTMP_INTERNAL_TX_ALC */ #ifdef RTMP_TEMPERATURE_COMPENSATION /* Temperature compensation, initialize the lookup table */ DBGPRINT(RT_DEBUG_OFF, ("bAutoTxAgcG = %d\n", pAd->bAutoTxAgcG)); if (pAd->chipCap.bTempCompTxALC && pAd->bAutoTxAgcG) InitLookupTable(pAd); #endif /* RTMP_TEMPERATURE_COMPENSATION */ #ifdef RTMP_FREQ_CALIBRATION_SUPPORT #endif /* RTMP_FREQ_CALIBRATION_SUPPORT */ /* Set PHY to appropriate mode*/ TmpPhy = pAd->CommonCfg.PhyMode; pAd->CommonCfg.PhyMode = 0xff; RTMPSetPhyMode(pAd, TmpPhy); #ifdef DOT11_N_SUPPORT SetCommonHT(pAd); #endif /* DOT11_N_SUPPORT */ /* No valid channels.*/ if (pAd->ChannelListNum == 0) { DBGPRINT(RT_DEBUG_ERROR, ("Wrong configuration. No valid channel found. Check \"ContryCode\" and \"ChannelGeography\" setting.\n")); goto err6; } #ifdef DOT11_N_SUPPORT DBGPRINT(RT_DEBUG_OFF, ("MCS Set = %02x %02x %02x %02x %02x\n", pAd->CommonCfg.HtCapability.MCSSet[0], pAd->CommonCfg.HtCapability.MCSSet[1], pAd->CommonCfg.HtCapability.MCSSet[2], pAd->CommonCfg.HtCapability.MCSSet[3], pAd->CommonCfg.HtCapability.MCSSet[4])); #endif /* DOT11_N_SUPPORT */ #ifdef CONFIG_AP_SUPPORT IF_DEV_CONFIG_OPMODE_ON_AP(pAd) { #ifdef AP_QLOAD_SUPPORT /* init QBSS Element */ QBSS_LoadInit(pAd); #endif /* AP_QLOAD_SUPPORT */ } #endif /* CONFIG_AP_SUPPORT */ /* APInitialize(pAd);*/ #ifdef IKANOS_VX_1X0 VR_IKANOS_FP_Init(pAd->ApCfg.BssidNum, pAd->PermanentAddress); #endif /* IKANOS_VX_1X0 */ #ifdef RALINK_ATE #ifdef RT5592 #ifdef RTMP_RF_RW_SUPPORT /* both for RT5572 and RT5592 */ if (IS_RT5592(pAd)) { RT55x2ATEFilterCalibration(pAd); } #endif /* RTMP_RF_RW_SUPPORT */ #endif /* RT5592 */ #endif /* RALINK_ATE */ #ifdef CONFIG_AP_SUPPORT /* Initialize RF register to default value*/ if (pAd->OpMode == OPMODE_AP) { AsicSwitchChannel(pAd, pAd->CommonCfg.Channel, FALSE); AsicLockChannel(pAd, pAd->CommonCfg.Channel); } #endif /* CONFIG_AP_SUPPORT */ /* Some modules init must be called before APStartUp(). Or APStartUp() will make up beacon content and call other modules API to get some information to fill. */ #ifdef CONFIG_TSO_SUPPORT if (RTMP_TEST_MORE_FLAG(pAd, fRTMP_ADAPTER_TSO_SUPPORT)) RTMPTsoEnable(pAd); #endif /* CONFIG_TSO_SUPPORT */ if (pAd && (Status != NDIS_STATUS_SUCCESS)) { /* Undo everything if it failed*/ if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_IN_USE)) { /* NdisMDeregisterInterrupt(&pAd->Interrupt);*/ RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_IN_USE); } /* RTMPFreeAdapter(pAd); we will free it in disconnect()*/ } else if (pAd) { /* Microsoft HCT require driver send a disconnect event after driver initialization.*/ OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_MEDIA_STATE_CONNECTED); OPSTATUS_CLEAR_FLAG(pAd, fOP_AP_STATUS_MEDIA_STATE_CONNECTED); RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_MEDIA_STATE_CHANGE); DBGPRINT(RT_DEBUG_TRACE, ("NDIS_STATUS_MEDIA_DISCONNECT Event B!\n")); #ifdef CONFIG_AP_SUPPORT IF_DEV_CONFIG_OPMODE_ON_AP(pAd) { if (pAd->ApCfg.bAutoChannelAtBootup || (pAd->CommonCfg.Channel == 0)) { UINT8 BBPValue = 0; /* Enable Interrupt first due to we need to scan channel to receive beacons.*/ RTMP_IRQ_ENABLE(pAd); /* Now Enable RxTx*/ RTMPEnableRxTx(pAd); RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_START_UP); /* Let BBP register at 20MHz to do scan */ RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &BBPValue); BBPValue &= (~0x18); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, BBPValue); DBGPRINT(RT_DEBUG_ERROR, ("SYNC - BBP R4 to 20MHz.l\n")); /* Now we can receive the beacon and do the listen beacon*/ /* use default BW to select channel*/ pAd->CommonCfg.Channel = AP_AUTO_CH_SEL(pAd, pAd->ApCfg.AutoChannelAlg); pAd->ApCfg.bAutoChannelAtBootup = FALSE; } #ifdef DOT11_N_SUPPORT /* If phymode > PHY_11ABGN_MIXED and BW=40 check extension channel, after select channel */ N_ChannelCheck(pAd); #ifdef DOT11N_DRAFT3 /* We only do this Overlapping BSS Scan when system up, for the other situation of channel changing, we depends on station's report to adjust ourself. */ if (pAd->CommonCfg.bForty_Mhz_Intolerant == TRUE) { DBGPRINT(RT_DEBUG_TRACE, ("Disable 20/40 BSSCoex Channel Scan(BssCoex=%d, 40MHzIntolerant=%d)\n", pAd->CommonCfg.bBssCoexEnable, pAd->CommonCfg.bForty_Mhz_Intolerant)); } else if(pAd->CommonCfg.bBssCoexEnable == TRUE) { DBGPRINT(RT_DEBUG_TRACE, ("Enable 20/40 BSSCoex Channel Scan(BssCoex=%d)\n", pAd->CommonCfg.bBssCoexEnable)); APOverlappingBSSScan(pAd); } RTMP_11N_D3_TimerInit(pAd); /* RTMPInitTimer(pAd, &pAd->CommonCfg.Bss2040CoexistTimer, GET_TIMER_FUNCTION(Bss2040CoexistTimeOut), pAd, FALSE);*/ #endif /* DOT11N_DRAFT3 */ #endif /* DOT11_N_SUPPORT */ APStartUp(pAd); DBGPRINT(RT_DEBUG_OFF, ("Main bssid = %02x:%02x:%02x:%02x:%02x:%02x\n", PRINT_MAC(pAd->ApCfg.MBSSID[BSS0].Bssid))); } #endif /* CONFIG_AP_SUPPORT */ }/* end of else*/ /* Set up the Mac address*/ #ifdef CONFIG_AP_SUPPORT RtmpOSNetDevAddrSet(pAd->OpMode, pAd->net_dev, &pAd->CurrentAddress[0], NULL); #endif /* CONFIG_AP_SUPPORT */ /* Various AP function init*/ #ifdef CONFIG_AP_SUPPORT IF_DEV_CONFIG_OPMODE_ON_AP(pAd) { #ifdef MBSS_SUPPORT /* the function can not be moved to RT2860_probe() even register_netdev() is changed as register_netdevice(). Or in some PC, kernel will panic (Fedora 4) */ /* RT28xx_MBSS_Init(pAd, pAd->net_dev); os abl move to rt_main_dev.c*/ #endif /* MBSS_SUPPORT */ #ifdef WDS_SUPPORT /* RT28xx_WDS_Init(pAd, pAd->net_dev);*/ #endif /* WDS_SUPPORT */ #ifdef APCLI_SUPPORT /* RT28xx_ApCli_Init(pAd, pAd->net_dev);*/ #endif /* APCLI_SUPPORT */ } #endif /* CONFIG_AP_SUPPORT */ #ifdef UAPSD_SUPPORT UAPSD_Init(pAd); #endif /* UAPSD_SUPPORT */ /* assign function pointers*/ #ifdef MAT_SUPPORT /* init function pointers, used in OS_ABL */ RTMP_MATOpsInit(pAd); #endif /* MAT_SUPPORT */ #ifdef RT_SOC_SUPPORT if (pAd->infType == RTMP_DEV_INF_RBUS || pAd->infType == RTMP_DEV_INF_PCIE) { #ifdef VIDEO_TURBINE_SUPPORT VideoTurbineDynamicTune(pAd); #endif /* VIDEO_TURBINE_SUPPORT */ #ifdef RT3XXX_ANTENNA_DIVERSITY_SUPPORT RT3XXX_AntDiversity_Init(pAd); #endif /* RT3XXX_ANTENNA_DIVERSITY_SUPPORT */ } #endif /* RT_SOC_SUPPORT */ #ifdef CONFIG_AP_SUPPORT IF_DEV_CONFIG_OPMODE_ON_AP(pAd) { #ifdef MAT_SUPPORT MATEngineInit(pAd); #endif /* MAT_SUPPORT */ #ifdef CLIENT_WDS CliWds_ProxyTabInit(pAd); #endif /* CLIENT_WDS */ } #endif /* CONFIG_AP_SUPPORT */ /* auto-fall back settings */ RTMP_IO_WRITE32(pAd, HT_FBK_CFG1, 0xedcba980); #ifdef DOT11N_SS3_SUPPORT if (pAd->CommonCfg.TxStream >= 3) { RTMP_IO_WRITE32(pAd, TX_FBK_CFG_3S_0, 0x12111008); RTMP_IO_WRITE32(pAd, TX_FBK_CFG_3S_1, 0x16151413); } #endif /* DOT11N_SS3_SUPPORT */ #ifdef STREAM_MODE_SUPPORT RtmpStreamModeInit(pAd); #endif /* STREAM_MODE_SUPPORT */ #if defined(RT2883) || defined(RT3883) || defined(RT3593) if (IS_RT2883(pAd) || IS_RT3883(pAd) || IS_RT3593(pAd)) { UINT8 BBPValue = 0; BBP_IO_READ8_BY_REG_ID(pAd, BBP_R65, &BBPValue); if (pAd->CommonCfg.FineAGC) BBPValue |= 0x40; /* turn on fine AGC*/ else BBPValue &= ~0x40; /* turn off fine AGC*/ BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R65, BBPValue); } #endif /* defined(RT2883) || defined(RT3883) || defined(RT3593) */ #ifdef DOT11_N_SUPPORT #ifdef TXBF_SUPPORT if (pAd->CommonCfg.ITxBfTimeout) { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R179, 0x02); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R180, 0); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R182, pAd->CommonCfg.ITxBfTimeout & 0xFF); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R180, 1); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R182, (pAd->CommonCfg.ITxBfTimeout>>8) & 0xFF); }
int rt28xx_init( IN PRTMP_ADAPTER pAd, IN PSTRING pDefaultMac, IN PSTRING pHostName) { UINT index; UCHAR TmpPhy; NDIS_STATUS Status; UINT32 MacCsr0 = 0; UINT16 ChipId = 0; // reset Adapter flags RTMP_CLEAR_FLAGS(pAd); // Init BssTab & ChannelInfo tabbles for auto channel select. #ifdef CONFIG_AP_SUPPORT IF_DEV_CONFIG_OPMODE_ON_AP(pAd) { //#ifdef AUTO_CH_SELECT_ENHANCE AutoChBssTableInit(pAd); ChannelInfoInit(pAd); //#endif // AUTO_CH_SELECT_ENHANCE // } #endif // CONFIG_AP_SUPPORT // #ifdef DOT11_N_SUPPORT // Allocate BA Reordering memory if (ba_reordering_resource_init(pAd, MAX_REORDERING_MPDU_NUM) != TRUE) goto err1; #endif // DOT11_N_SUPPORT // // Make sure MAC gets ready. index = 0; do { RTMP_IO_READ32(pAd, MAC_CSR0, &MacCsr0); pAd->MACVersion = MacCsr0; /* The purpose is to identify RT5390H */ RT28xx_EEPROM_READ16(pAd, 0x00, ChipId); pAd->ChipId = ChipId; if ((pAd->MACVersion != 0x00) && (pAd->MACVersion != 0xFFFFFFFF)) break; if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)) goto err1; RTMPusecDelay(10); } while (index++ < 100); DBGPRINT(RT_DEBUG_TRACE, ("MAC_CSR0 [ Ver:Rev=0x%08x]\n", pAd->MACVersion)); #ifdef RT5390 if (IS_RT5390H(pAd)) DBGPRINT(RT_DEBUG_ERROR, ("The chip belongs to 0x%04x\n", pAd->ChipId)); #endif /* RT5390 */ #ifdef SPECIFIC_BCN_BUF_SUPPORT pAd->BcnCB.DYN_MAX_MBSSID_NUM = 1; if (IS_RT5390(pAd) || IS_RT3593(pAd)) { pAd->BcnCB.bHighShareMemSupport = 1; pAd->BcnCB.DYN_HW_BEACON_BASE0 = 0x4000; pAd->BcnCB.DYN_HW_BEACON_MAX_SIZE = 0x2000; pAd->BcnCB.DYN_HW_BEACON_MAX_COUNT = 16; #ifdef MBSS_SUPPORT #ifdef APCLI_SUPPORT pAd->BcnCB.DYN_MAX_MBSSID_NUM = 8 - MAX_MESH_NUM; #else pAd->BcnCB.DYN_MAX_MBSSID_NUM = 16 - MAX_MESH_NUM; #endif // APCLI_SUPPORT // #endif // MBSS_SUPPORT // } else { pAd->BcnCB.bHighShareMemSupport = 0; pAd->BcnCB.DYN_HW_BEACON_BASE0 = 0x7800; pAd->BcnCB.DYN_HW_BEACON_MAX_SIZE = 0x1000; pAd->BcnCB.DYN_HW_BEACON_MAX_COUNT = 8; #ifdef MBSS_SUPPORT pAd->BcnCB.DYN_MAX_MBSSID_NUM = (pAd->BcnCB.DYN_HW_BEACON_MAX_COUNT - MAX_MESH_NUM - MAX_APCLI_NUM); #endif // MBSS_SUPPORT // } #endif // SPECIFIC_BCN_BUF_SUPPORT // #ifdef RTMP_MAC_PCI #if defined(RT3090) || defined(RT3592) || defined(RT3390) || defined(RT3593) || defined(RT5390) /*Iverson patch PCIE L1 issue to make sure that driver can be read,write ,BBP and RF register at pcie L.1 level */ if ((IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd) || IS_RT3593(pAd) || IS_RT5390(pAd))&&pAd->infType==RTMP_DEV_INF_PCIE) { RTMP_IO_READ32(pAd, AUX_CTRL, &MacCsr0); MacCsr0 |= 0x402; RTMP_IO_WRITE32(pAd, AUX_CTRL, MacCsr0); DBGPRINT(RT_DEBUG_TRACE, ("AUX_CTRL = 0x%x\n", MacCsr0)); } #endif // RT3090 // // To fix driver disable/enable hang issue when radio off RTMP_IO_WRITE32(pAd, PWR_PIN_CFG, 0x2); #endif // RTMP_MAC_PCI // // Disable DMA RT28XXDMADisable(pAd); // Load 8051 firmware Status = NICLoadFirmware(pAd); if (Status != NDIS_STATUS_SUCCESS) { DBGPRINT_ERR(("NICLoadFirmware failed, Status[=0x%08x]\n", Status)); goto err1; } NICLoadRateSwitchingParams(pAd); // Disable interrupts here which is as soon as possible // This statement should never be true. We might consider to remove it later #ifdef RTMP_MAC_PCI if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_ACTIVE)) { RTMP_ASIC_INTERRUPT_DISABLE(pAd); } #endif // RTMP_MAC_PCI // #ifdef RESOURCE_PRE_ALLOC Status = RTMPInitTxRxRingMemory(pAd); #else Status = RTMPAllocTxRxRingMemory(pAd); #endif // RESOURCE_PRE_ALLOC // if (Status != NDIS_STATUS_SUCCESS) { DBGPRINT_ERR(("RTMPAllocTxRxMemory failed, Status[=0x%08x]\n", Status)); goto err2; } RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_IN_USE); // initialize MLME // Status = RtmpMgmtTaskInit(pAd); if (Status != NDIS_STATUS_SUCCESS) goto err3; Status = MlmeInit(pAd); if (Status != NDIS_STATUS_SUCCESS) { DBGPRINT_ERR(("MlmeInit failed, Status[=0x%08x]\n", Status)); goto err4; } #ifdef RMTP_RBUS_SUPPORT #ifdef VIDEO_TURBINE_SUPPORT VideoConfigInit(pAd); #endif // VIDEO_TURBINE_SUPPORT // #endif // RMTP_RBUS_SUPPORT // // Initialize pAd->StaCfg, pAd->ApCfg, pAd->CommonCfg to manufacture default // UserCfgInit(pAd); Status = RtmpNetTaskInit(pAd); if (Status != NDIS_STATUS_SUCCESS) goto err5; // COPY_MAC_ADDR(pAd->ApCfg.MBSSID[apidx].Bssid, netif->hwaddr); // pAd->bForcePrintTX = TRUE; CfgInitHook(pAd); #ifdef CONFIG_AP_SUPPORT IF_DEV_CONFIG_OPMODE_ON_AP(pAd) APInitialize(pAd); #endif // CONFIG_AP_SUPPORT // #ifdef BLOCK_NET_IF initblockQueueTab(pAd); #endif // BLOCK_NET_IF // Status = MeasureReqTabInit(pAd); if (Status != NDIS_STATUS_SUCCESS) { DBGPRINT_ERR(("MeasureReqTabInit failed, Status[=0x%08x]\n",Status)); goto err6; } Status = TpcReqTabInit(pAd); if (Status != NDIS_STATUS_SUCCESS) { DBGPRINT_ERR(("TpcReqTabInit failed, Status[=0x%08x]\n",Status)); goto err6; } // // Init the hardware, we need to init asic before read registry, otherwise mac register will be reset // Status = NICInitializeAdapter(pAd, TRUE); if (Status != NDIS_STATUS_SUCCESS) { DBGPRINT_ERR(("NICInitializeAdapter failed, Status[=0x%08x]\n", Status)); if (Status != NDIS_STATUS_SUCCESS) goto err6; } #ifdef CONFIG_AP_SUPPORT IF_DEV_CONFIG_OPMODE_ON_AP(pAd) { } #endif // CONFIG_AP_SUPPORT // // Read parameters from Config File /* unknown, it will be updated in NICReadEEPROMParameters */ pAd->RfIcType = RFIC_UNKNOWN; Status = RTMPReadParametersHook(pAd); DBGPRINT(RT_DEBUG_OFF, ("1. Phy Mode = %d\n", pAd->CommonCfg.PhyMode)); if (Status != NDIS_STATUS_SUCCESS) { DBGPRINT_ERR(("RTMPReadParametersHook failed, Status[=0x%08x]\n",Status)); goto err6; } #ifdef DOT11_N_SUPPORT //Init Ba Capability parameters. // RT28XX_BA_INIT(pAd); pAd->CommonCfg.DesiredHtPhy.MpduDensity = (UCHAR)pAd->CommonCfg.BACapability.field.MpduDensity; pAd->CommonCfg.DesiredHtPhy.AmsduEnable = (USHORT)pAd->CommonCfg.BACapability.field.AmsduEnable; pAd->CommonCfg.DesiredHtPhy.AmsduSize = (USHORT)pAd->CommonCfg.BACapability.field.AmsduSize; pAd->CommonCfg.DesiredHtPhy.MimoPs = (USHORT)pAd->CommonCfg.BACapability.field.MMPSmode; // UPdata to HT IE pAd->CommonCfg.HtCapability.HtCapInfo.MimoPs = (USHORT)pAd->CommonCfg.BACapability.field.MMPSmode; pAd->CommonCfg.HtCapability.HtCapInfo.AMsduSize = (USHORT)pAd->CommonCfg.BACapability.field.AmsduSize; pAd->CommonCfg.HtCapability.HtCapParm.MpduDensity = (UCHAR)pAd->CommonCfg.BACapability.field.MpduDensity; #endif // DOT11_N_SUPPORT // // after reading Registry, we now know if in AP mode or STA mode // Load 8051 firmware; crash when FW image not existent // Status = NICLoadFirmware(pAd); // if (Status != NDIS_STATUS_SUCCESS) // break; DBGPRINT(RT_DEBUG_OFF, ("2. Phy Mode = %d\n", pAd->CommonCfg.PhyMode)); // We should read EEPROM for all cases. rt2860b NICReadEEPROMParameters(pAd, (PUCHAR)pDefaultMac); DBGPRINT(RT_DEBUG_OFF, ("3. Phy Mode = %d\n", pAd->CommonCfg.PhyMode)); NICInitAsicFromEEPROM(pAd); //rt2860b #ifdef RTMP_INTERNAL_TX_ALC // // Initialize the desired TSSI table // InitDesiredTSSITable(pAd); #endif // RTMP_INTERNAL_TX_ALC // #if defined(RT5390) || defined(RT5370) // // Temperature compensation, initialize the lookup table // DBGPRINT(RT_DEBUG_ERROR, ("IS_RT5392 = %d, bAutoTxAgcG = %d\n", IS_RT5392(pAd), pAd->bAutoTxAgcG)); if (IS_RT5392(pAd) && pAd->bAutoTxAgcG && pAd->CommonCfg.TempComp != 0) { InitLookupTable(pAd); } #endif // defined(RT5390) || defined(RT5370) // // Set PHY to appropriate mode TmpPhy = pAd->CommonCfg.PhyMode; pAd->CommonCfg.PhyMode = 0xff; RTMPSetPhyMode(pAd, TmpPhy); #ifdef DOT11_N_SUPPORT SetCommonHT(pAd); #endif // DOT11_N_SUPPORT // // No valid channels. if (pAd->ChannelListNum == 0) { DBGPRINT(RT_DEBUG_ERROR, ("Wrong configuration. No valid channel found. Check \"ContryCode\" and \"ChannelGeography\" setting.\n")); goto err6; } #ifdef DOT11_N_SUPPORT DBGPRINT(RT_DEBUG_OFF, ("MCS Set = %02x %02x %02x %02x %02x\n", pAd->CommonCfg.HtCapability.MCSSet[0], pAd->CommonCfg.HtCapability.MCSSet[1], pAd->CommonCfg.HtCapability.MCSSet[2], pAd->CommonCfg.HtCapability.MCSSet[3], pAd->CommonCfg.HtCapability.MCSSet[4])); #endif // DOT11_N_SUPPORT // #ifdef CONFIG_AP_SUPPORT IF_DEV_CONFIG_OPMODE_ON_AP(pAd) { #ifdef AP_QLOAD_SUPPORT /* init QBSS Element */ QBSS_LoadInit(pAd); #endif // AP_QLOAD_SUPPORT // //#ifdef DOT11K_RRM_SUPPORT // RRM_CfgInit(pAd); //#endif // DOT11K_RRM_SUPPORT // } #endif // CONFIG_AP_SUPPORT // // APInitialize(pAd); #ifdef IKANOS_VX_1X0 VR_IKANOS_FP_Init(pAd->ApCfg.BssidNum, pAd->PermanentAddress); #endif // IKANOS_VX_1X0 // #ifdef CONFIG_AP_SUPPORT // // Initialize RF register to default value // if (pAd->OpMode == OPMODE_AP) { AsicSwitchChannel(pAd, pAd->CommonCfg.Channel, FALSE); AsicLockChannel(pAd, pAd->CommonCfg.Channel); } #endif // CONFIG_AP_SUPPORT // /* Some modules init must be called before APStartUp(). Or APStartUp() will make up beacon content and call other modules API to get some information to fill. */ #ifdef WMM_ACM_SUPPORT #ifdef CONFIG_AP_SUPPORT ACMP_Init(pAd, pAd->CommonCfg.APEdcaParm.bACM[0], pAd->CommonCfg.APEdcaParm.bACM[1], pAd->CommonCfg.APEdcaParm.bACM[2], pAd->CommonCfg.APEdcaParm.bACM[3], 0); #endif // CONFIG_AP_SUPPORT // #endif // WMM_ACM_SUPPORT // if (pAd && (Status != NDIS_STATUS_SUCCESS)) { // // Undo everything if it failed // if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_IN_USE)) { // NdisMDeregisterInterrupt(&pAd->Interrupt); RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_IN_USE); } // RTMPFreeAdapter(pAd); // we will free it in disconnect() } else if (pAd) { // Microsoft HCT require driver send a disconnect event after driver initialization. OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_MEDIA_STATE_CONNECTED); RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_MEDIA_STATE_CHANGE); DBGPRINT(RT_DEBUG_TRACE, ("NDIS_STATUS_MEDIA_DISCONNECT Event B!\n")); #ifdef CONFIG_AP_SUPPORT IF_DEV_CONFIG_OPMODE_ON_AP(pAd) { if (pAd->ApCfg.bAutoChannelAtBootup || (pAd->CommonCfg.Channel == 0)) { UINT8 BBPValue = 0; // Enable Interrupt first due to we need to scan channel to receive beacons. RTMP_IRQ_ENABLE(pAd); // Now Enable RxTx RTMPEnableRxTx(pAd); RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_START_UP); // Let BBP register at 20MHz to do scan RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &BBPValue); BBPValue &= (~0x18); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, BBPValue); DBGPRINT(RT_DEBUG_ERROR, ("SYNC - BBP R4 to 20MHz.l\n")); // Now we can receive the beacon and do the listen beacon // use default BW to select channel pAd->CommonCfg.Channel = AP_AUTO_CH_SEL(pAd, pAd->ApCfg.AutoChannelAlg); pAd->ApCfg.bAutoChannelAtBootup = FALSE; } #ifdef DOT11_N_SUPPORT // If phymode > PHY_11ABGN_MIXED and BW=40 check extension channel, after select channel N_ChannelCheck(pAd); #ifdef DOT11N_DRAFT3 /* We only do this Overlapping BSS Scan when system up, for the other situation of channel changing, we depends on station's report to adjust ourself. */ if (pAd->CommonCfg.bForty_Mhz_Intolerant == TRUE) { DBGPRINT(RT_DEBUG_TRACE, ("Disable 20/40 BSSCoex Channel Scan(BssCoex=%d, 40MHzIntolerant=%d)\n", pAd->CommonCfg.bBssCoexEnable, pAd->CommonCfg.bForty_Mhz_Intolerant)); } else if(pAd->CommonCfg.bBssCoexEnable == TRUE) { DBGPRINT(RT_DEBUG_TRACE, ("Enable 20/40 BSSCoex Channel Scan(BssCoex=%d)\n", pAd->CommonCfg.bBssCoexEnable)); APOverlappingBSSScan(pAd); } RTMP_11N_D3_TimerInit(pAd); // RTMPInitTimer(pAd, &pAd->CommonCfg.Bss2040CoexistTimer, GET_TIMER_FUNCTION(Bss2040CoexistTimeOut), pAd, FALSE); #endif // DOT11N_DRAFT3 // #endif // DOT11_N_SUPPORT // #ifdef RT3090 #ifdef TONE_RADAR_DETECT_SUPPORT if (IS_RT3090A(pAd) || IS_RT3390(pAd) || IS_RT5390(pAd)) pAd->CommonCfg.carrier_func=TONE_RADAR_V2; else pAd->CommonCfg.carrier_func=TONE_RADAR_V1; #endif // TONE_RADAR_DETECT_SUPPORT // #endif // RT3090 // APStartUp(pAd); DBGPRINT(RT_DEBUG_OFF, ("Main bssid = %02x:%02x:%02x:%02x:%02x:%02x\n", PRINT_MAC(pAd->ApCfg.MBSSID[BSS0].Bssid))); } #endif // CONFIG_AP_SUPPORT // }// end of else #ifdef WSC_INCLUDED #ifdef CONFIG_AP_SUPPORT IF_DEV_CONFIG_OPMODE_ON_AP(pAd) { INT apidx; #ifdef HOSTAPD_SUPPORT if (pAd->ApCfg.Hostapd == TRUE) { DBGPRINT(RT_DEBUG_TRACE, ("WPS is control by hostapd now.\n")); } else #endif //HOSTAPD_SUPPORT// for (apidx = 0; apidx < pAd->ApCfg.BssidNum; apidx++) { PWSC_CTRL pWscControl; UCHAR zeros16[16]= {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; pWscControl = &pAd->ApCfg.MBSSID[apidx].WscControl; DBGPRINT(RT_DEBUG_TRACE, ("Generate UUID for apidx(%d)\n", apidx)); if (NdisEqualMemory(&pWscControl->Wsc_Uuid_E[0], zeros16, UUID_LEN_HEX)) WscGenerateUUID(pAd, &pWscControl->Wsc_Uuid_E[0], &pWscControl->Wsc_Uuid_Str[0], apidx, FALSE); WscInit(pAd, FALSE, apidx); } } #endif // CONFIG_AP_SUPPORT // /* WSC hardware push button function 0811 */ WSC_HDR_BTN_Init(pAd); #endif // WSC_INCLUDED // // Set up the Mac address RtmpOSNetDevAddrSet(pAd->net_dev, &pAd->CurrentAddress[0]); // Various AP function init #ifdef CONFIG_AP_SUPPORT IF_DEV_CONFIG_OPMODE_ON_AP(pAd) { #ifdef MBSS_SUPPORT /* the function can not be moved to RT2860_probe() even register_netdev() is changed as register_netdevice(). Or in some PC, kernel will panic (Fedora 4) */ RT28xx_MBSS_Init(pAd, pAd->net_dev); #endif // MBSS_SUPPORT // #ifdef WDS_SUPPORT RT28xx_WDS_Init(pAd, pAd->net_dev); #endif // WDS_SUPPORT // #ifdef APCLI_SUPPORT RT28xx_ApCli_Init(pAd, pAd->net_dev); #endif // APCLI_SUPPORT // } #endif // CONFIG_AP_SUPPORT // #ifdef CONFIG_AP_SUPPORT IF_DEV_CONFIG_OPMODE_ON_AP(pAd) { #ifdef MAT_SUPPORT MATEngineInit(pAd); #endif // MAT_SUPPORT // #ifdef CLIENT_WDS CliWds_ProxyTabInit(pAd); #endif // CLIENT_WDS // } #endif // CONFIG_AP_SUPPORT // #ifdef RT33xx if (IS_RT3390(pAd)) { RTMP_TxEvmCalibration(pAd); } #endif // RT33xx // DBGPRINT_S(Status, ("<==== rt28xx_init, Status=%x\n", Status)); return TRUE; err6: MeasureReqTabExit(pAd); TpcReqTabExit(pAd); err5: RtmpNetTaskExit(pAd); UserCfgExit(pAd); err4: MlmeHalt(pAd); err3: RtmpMgmtTaskExit(pAd); err2: #ifdef RESOURCE_PRE_ALLOC RTMPResetTxRxRingMemory(pAd); #else RTMPFreeTxRxRingMemory(pAd); #endif // RESOURCE_PRE_ALLOC // err1: #ifdef DOT11_N_SUPPORT if(pAd->mpdu_blk_pool.mem) os_free_mem(pAd, pAd->mpdu_blk_pool.mem); // free BA pool #endif // DOT11_N_SUPPORT // // shall not set priv to NULL here because the priv didn't been free yet. //net_dev->priv = 0; #ifdef INF_AMAZON_SE err0: #endif // INF_AMAZON_SE // #ifdef ST err0: #endif // ST // DBGPRINT(RT_DEBUG_ERROR, ("!!! rt28xx Initialized fail !!!\n")); return FALSE; }
VOID RT33xx_ChipSwitchChannel( IN PRTMP_ADAPTER pAd, IN UCHAR Channel, IN BOOLEAN bScan) { CHAR TxPwer = 0, TxPwer2 = DEFAULT_RF_TX_POWER; /*Bbp94 = BBPR94_DEFAULT, TxPwer2 = DEFAULT_RF_TX_POWER;*/ UCHAR index; UINT32 Value = 0; /*BbpReg, Value;*/ UCHAR RFValue; #ifdef DOT11N_SS3_SUPPORT CHAR TxPwer3 = 0; #endif /* DOT11N_SS3_SUPPORT */ #ifdef RT30xx UCHAR Tx0FinePowerCtrl = 0, Tx1FinePowerCtrl = 0; BBP_R109_STRUC BbpR109 = {{0}}; #endif /* RT30xx */ RFValue = 0; /* Search Tx power value*/ /* We can't use ChannelList to search channel, since some central channl's txpowr doesn't list in ChannelList, so use TxPower array instead. */ for (index = 0; index < MAX_NUM_OF_CHANNELS; index++) { if (Channel == pAd->TxPower[index].Channel) { TxPwer = pAd->TxPower[index].Power; TxPwer2 = pAd->TxPower[index].Power2; #ifdef DOT11N_SS3_SUPPORT if (IS_RT2883(pAd) || IS_RT3593(pAd) || IS_RT3883(pAd)) TxPwer3 = pAd->TxPower[index].Power3; #endif /* DOT11N_SS3_SUPPORT */ #ifdef RT30xx /*RT33xx*/ if ((IS_RT3090A(pAd) || IS_RT3390(pAd) || IS_RT5390(pAd)))/*&&*/ /*(pAd->infType == RTMP_DEV_INF_PCI || pAd->infType == RTMP_DEV_INF_PCIE))*/ { Tx0FinePowerCtrl = pAd->TxPower[index].Tx0FinePowerCtrl; Tx1FinePowerCtrl = pAd->TxPower[index].Tx1FinePowerCtrl; } #endif /* RT30xx */ break; } } if (index == MAX_NUM_OF_CHANNELS) { DBGPRINT(RT_DEBUG_ERROR, ("AsicSwitchChannel: Can't find the Channel#%d \n", Channel)); } #ifdef RT30xx /* The RF programming sequence is difference between 3xxx and 2xxx*/ if ((IS_RT30xx(pAd)) && ((pAd->RfIcType == RFIC_3020) || (pAd->RfIcType == RFIC_2020) || (pAd->RfIcType == RFIC_3021) || (pAd->RfIcType == RFIC_3022) || (pAd->RfIcType == RFIC_3320))) { /* modify by WY for Read RF Reg. error */ UCHAR calRFValue; for (index = 0; index < NUM_OF_3020_CHNL; index++) { if (Channel == FreqItems3020[index].Channel) { /* Programming channel parameters*/ RT30xxWriteRFRegister(pAd, RF_R02, FreqItems3020[index].N); /* RT3370/RT3390 RF version is 0x3320 RF_R3 [7:4] is not reserved bits RF_R3[6:4] (pa1_bc_cck) : PA1 Bias CCK RF_R3[7] (pa2_cc_cck) : PA2 Cascode Bias CCK */ RT30xxReadRFRegister(pAd, RF_R03, (PUCHAR)(&RFValue)); RFValue = (RFValue & 0xF0) | (FreqItems3020[index].K & ~0xF0); /* <bit 3:0>:K<bit 3:0>*/ RT30xxWriteRFRegister(pAd, RF_R03, RFValue); RT30xxReadRFRegister(pAd, RF_R06, &RFValue); RFValue = (RFValue & 0xFC) | FreqItems3020[index].R; RT30xxWriteRFRegister(pAd, RF_R06, RFValue); /* Set Tx0 Power*/ RT30xxReadRFRegister(pAd, RF_R12, &RFValue); RFValue = (RFValue & 0xE0) | TxPwer; RT30xxWriteRFRegister(pAd, RF_R12, RFValue); /* Set Tx1 Power*/ RT30xxReadRFRegister(pAd, RF_R13, &RFValue); RFValue = (RFValue & 0xE0) | TxPwer2; RT30xxWriteRFRegister(pAd, RF_R13, RFValue); #ifdef RT33xx #endif /* RT33xx */ /* Tx/Rx Stream setting*/ RT30xxReadRFRegister(pAd, RF_R01, &RFValue); /*if (IS_RT3090(pAd))*/ /* RFValue |= 0x01; Enable RF block.*/ RFValue &= 0xC3; /*clear bit[7~2]*/ if (pAd->Antenna.field.TxPath == 1) RFValue |= 0x20; else if (pAd->Antenna.field.TxPath == 2) ; if (pAd->Antenna.field.RxPath == 1) RFValue |= 0x10; else if (pAd->Antenna.field.RxPath == 2) ; RT30xxWriteRFRegister(pAd, RF_R01, RFValue); /* Set RF offset*/ RT30xxReadRFRegister(pAd, RF_R23, &RFValue); RFValue = (RFValue & 0x80) | pAd->RfFreqOffset; RT30xxWriteRFRegister(pAd, RF_R23, RFValue); /* Set BW*/ if (!bScan && (pAd->CommonCfg.BBPCurrentBW == BW_40)) { calRFValue = pAd->Mlme.CaliBW40RfR24; /*DISABLE_11N_CHECK(pAd);*/ } else { calRFValue = pAd->Mlme.CaliBW20RfR24; } /* RT3370/RT3390 RF version is 0x3320 RF_R24 [7:6] is not reserved bits RF_R24[6] (BB_Rx1_out_en) : enable baseband output and ADC input RF_R24[7] (BB_Tx1_out_en) : enable DAC output or baseband input */ RT30xxReadRFRegister(pAd, RF_R24, (PUCHAR)(&RFValue)); calRFValue = (RFValue & 0xC0) | (calRFValue & ~0xC0); /* <bit 5>:tx_h20M<bit 5> and <bit 4:0>:tx_agc_fc<bit 4:0>*/ RT30xxWriteRFRegister(pAd, RF_R24, calRFValue); /* RT3370/RT3390 RF version is 0x3320 RF_R31 [7:6] is not reserved bits RF_R31[4:0] (rx_agc_fc) : capacitor control in baseband filter RF_R31[5] (rx_ h20M) : rx_ h20M: 0=10 MHz and 1=20MHz RF_R31[7:6] (drv_bc_cck) : Driver Bias CCK */ /* Set BW*/ if (IS_RT3390(pAd)) /* RT3390 has different AGC for Tx and Rx*/ { if (!bScan && (pAd->CommonCfg.BBPCurrentBW == BW_40)) { calRFValue = pAd->Mlme.CaliBW40RfR31; } else { calRFValue = pAd->Mlme.CaliBW20RfR31; } } RT30xxReadRFRegister(pAd, RF_R31, (PUCHAR)(&RFValue)); calRFValue = (RFValue & 0xC0) | (calRFValue & ~0xC0); /* <bit 5>:rx_h20M<bit 5> and <bit 4:0>:rx_agc_fc<bit 4:0> */ RT30xxWriteRFRegister(pAd, RF_R31, calRFValue); /* Enable RF tuning*/ RT30xxReadRFRegister(pAd, RF_R07, &RFValue); RFValue = RFValue | 0x1; RT30xxWriteRFRegister(pAd, RF_R07, RFValue); /* latch channel for future usage.*/ pAd->LatchRfRegs.Channel = Channel; DBGPRINT(RT_DEBUG_TRACE, ("SwitchChannel#%d(RF=%d, Pwr0=%d, Pwr1=%d, %dT), N=0x%02X, K=0x%02X, R=0x%02X\n", Channel, pAd->RfIcType, TxPwer, TxPwer2, pAd->Antenna.field.TxPath, FreqItems3020[index].N, FreqItems3020[index].K, FreqItems3020[index].R)); break; } } } #endif /* RT30xx */ /* Change BBP setting during siwtch from a->g, g->a*/ if (Channel <= 14) { ULONG TxPinCfg = 0x00050F0A;/*Gary 2007/08/09 0x050A0A*/ RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - GET_LNA_GAIN(pAd))); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - GET_LNA_GAIN(pAd))); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - GET_LNA_GAIN(pAd))); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0);/*(0x44 - GET_LNA_GAIN(pAd))); According the Rory's suggestion to solve the middle range issue.*/ /* Rx High power VGA offset for LNA select*/ if (pAd->NicConfig2.field.ExternalLNAForG) { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x62); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x46); } else { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x84); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x50); } /* Turn off unused PA or LNA when only 1T or 1R*/ if (pAd->Antenna.field.TxPath == 1) { TxPinCfg &= 0xFFFFFFF3; } if (pAd->Antenna.field.RxPath == 1) { TxPinCfg &= 0xFFFFF3FF; } RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg); } else { ULONG TxPinCfg = 0x00050F05;/*Gary 2007/8/9 0x050505*/ UINT8 bbpValue; RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - GET_LNA_GAIN(pAd))); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - GET_LNA_GAIN(pAd))); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - GET_LNA_GAIN(pAd))); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0);/*(0x44 - GET_LNA_GAIN(pAd))); According the Rory's suggestion to solve the middle range issue. */ /* Set the BBP_R82 value here */ bbpValue = 0xF2; RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, bbpValue); /* Rx High power VGA offset for LNA select*/ if (pAd->NicConfig2.field.ExternalLNAForA) { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x46); } else { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x50); } /* 5G band selection PIN, bit1 and bit2 are complement*/ RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value); Value &= (~0x6); Value |= (0x02); RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value); /* Turn off unused PA or LNA when only 1T or 1R*/ /* Turn off unused PA or LNA when only 1T or 1R*/ if (pAd->Antenna.field.TxPath == 1) { TxPinCfg &= 0xFFFFFFF3; } if (pAd->Antenna.field.RxPath == 1) { TxPinCfg &= 0xFFFFF3FF; } RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg); } /* GPIO control*/ /* R66 should be set according to Channel and use 20MHz when scanning*/ /*RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, (0x2E + GET_LNA_GAIN(pAd)));*/ if (bScan) RTMPSetAGCInitValue(pAd, BW_20); else RTMPSetAGCInitValue(pAd, pAd->CommonCfg.BBPCurrentBW); /* On 11A, We should delay and wait RF/BBP to be stable*/ /* and the appropriate time should be 1000 micro seconds */ /* 2005/06/05 - On 11G, We also need this delay time. Otherwise it's difficult to pass the WHQL.*/ RTMPusecDelay(1000); }
/* ========================================================================== Description: Reverse RF sleep-mode setup ========================================================================== */ VOID RT30xxReverseRFSleepModeSetup( IN PRTMP_ADAPTER pAd, IN BOOLEAN FlgIsInitState) { UCHAR RFValue; UINT32 MACValue; if(!IS_RT3572(pAd)) { { /* RF_BLOCK_en, RF R1 register Bit 0 to 1*/ RT30xxReadRFRegister(pAd, RF_R01, &RFValue); RFValue |= 0x01; RT30xxWriteRFRegister(pAd, RF_R01, RFValue); /* VCO_IC, RF R7 register Bit 4 & Bit 5 to 1*/ RT30xxReadRFRegister(pAd, RF_R07, &RFValue); RFValue |= 0x20; RT30xxWriteRFRegister(pAd, RF_R07, RFValue); /* Idoh, RF R9 register Bit 1, Bit 2 & Bit 3 to 1*/ RT30xxReadRFRegister(pAd, RF_R09, &RFValue); RFValue |= 0x0E; RT30xxWriteRFRegister(pAd, RF_R09, RFValue); /* RX_CTB_en, RF R21 register Bit 7 to 1*/ RT30xxReadRFRegister(pAd, RF_R21, &RFValue); RFValue |= 0x80; RT30xxWriteRFRegister(pAd, RF_R21, RFValue); } } if (IS_RT3090(pAd) || /* IS_RT3090 including RT309x and RT3071/72*/ IS_RT3572(pAd) || IS_RT3390(pAd) || IS_RT3593(pAd) || (IS_RT3070(pAd) && ((pAd->MACVersion & 0xffff) < 0x0201))) { if ((!IS_RT3572(pAd)) && (!IS_RT3593(pAd))) { RT30xxReadRFRegister(pAd, RF_R27, &RFValue); if ((pAd->MACVersion & 0xffff) < 0x0211) RFValue = (RFValue & (~0x77)) | 0x3; else RFValue = (RFValue & (~0x77)); RT30xxWriteRFRegister(pAd, RF_R27, RFValue); } /* RT3071 version E has fixed this issue*/ if ((pAd->NicConfig2.field.DACTestBit == 1) && ((pAd->MACVersion & 0xffff) < 0x0211)) { /* patch tx EVM issue temporarily*/ RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue); MACValue = ((MACValue & 0xE0FFFFFF) | 0x0D000000); RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue); } else if ((!IS_RT3090(pAd) && !IS_RT3593(pAd))) { RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue); MACValue = ((MACValue & 0xE0FFFFFF) | 0x01000000); RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue); } } if(IS_RT3572(pAd)) RT30xxWriteRFRegister(pAd, RF_R08, 0x80); }
/* ========================================================================== Description: dynamic tune BBP R66 to find a balance between sensibility and noise isolation IRQL = DISPATCH_LEVEL ========================================================================== */ UCHAR RT35xx_ChipStaBBPAdjust( IN RTMP_ADAPTER *pAd, IN CHAR Rssi, IN UCHAR R66) { UCHAR OrigR66Value = 0;/*, R66UpperBound = 0x30, R66LowerBound = 0x30;*/ if (pAd->LatchRfRegs.Channel <= 14) { /*BG band*/ if (IS_RT3572(pAd)|| IS_RT3593(pAd)) { if (Rssi > RSSI_FOR_MID_LOW_SENSIBILITY) { R66 = 0x1C + 2*GET_LNA_GAIN(pAd) + 0x20; if (OrigR66Value != R66) { RT3572WriteBBPR66(pAd, R66); } } else { R66 = 0x1C + 2*GET_LNA_GAIN(pAd); if (OrigR66Value != R66) { RT3572WriteBBPR66(pAd, R66); } } } else DBGPRINT(RT_DEBUG_ERROR, ("RT35xx_ChipStaBBPAdjust - Mismatch MACVersion = 0x%x \n", pAd->MACVersion)); } else { /*A band*/ if (pAd->CommonCfg.BBPCurrentBW == BW_20) { if (Rssi > RSSI_FOR_MID_LOW_SENSIBILITY) { R66 = 0x32 + (GET_LNA_GAIN(pAd)*5)/3 + 0x10; if (OrigR66Value != R66) { if (IS_RT3572(pAd) || IS_RT3593(pAd)) RT3572WriteBBPR66(pAd, R66); } } else { R66 = 0x32 + (GET_LNA_GAIN(pAd)*5)/3; if (OrigR66Value != R66) { if (IS_RT3572(pAd) || IS_RT3593(pAd)) RT3572WriteBBPR66(pAd, R66); } } } else { if (Rssi > RSSI_FOR_MID_LOW_SENSIBILITY) { R66 = 0x3A + (GET_LNA_GAIN(pAd)*5)/3 + 0x10; if (OrigR66Value != R66) { if (IS_RT3572(pAd) || IS_RT3593(pAd)) RT3572WriteBBPR66(pAd, R66); } } else { R66 = 0x3A + (GET_LNA_GAIN(pAd)*5)/3; if (OrigR66Value != R66) { if (IS_RT3572(pAd) || IS_RT3593(pAd)) RT3572WriteBBPR66(pAd, R66); } } } } return 0; }
int rt28xx_init( IN PRTMP_ADAPTER pAd, IN PSTRING pDefaultMac, IN PSTRING pHostName) { UINT index; UCHAR TmpPhy; NDIS_STATUS Status; UINT32 MacCsr0 = 0; #ifdef CONFIG_STA_SUPPORT #ifdef PCIE_PS_SUPPORT IF_DEV_CONFIG_OPMODE_ON_STA(pAd) { // If dirver doesn't wake up firmware here, // NICLoadFirmware will hang forever when interface is up again. if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE) && OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_ADVANCE_POWER_SAVE_PCIE_DEVICE)) { AUTO_WAKEUP_STRUC AutoWakeupCfg; AsicForceWakeup(pAd, TRUE); AutoWakeupCfg.word = 0; RTMP_IO_WRITE32(pAd, AUTO_WAKEUP_CFG, AutoWakeupCfg.word); OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_DOZE); } } #endif // PCIE_PS_SUPPORT // #endif // CONFIG_STA_SUPPORT // // reset Adapter flags RTMP_CLEAR_FLAGS(pAd); // Init BssTab & ChannelInfo tabbles for auto channel select. #ifdef DOT11_N_SUPPORT // Allocate BA Reordering memory if (ba_reordering_resource_init(pAd, MAX_REORDERING_MPDU_NUM) != TRUE) goto err1; #endif // DOT11_N_SUPPORT // // Make sure MAC gets ready. index = 0; do { RTMP_IO_READ32(pAd, MAC_CSR0, &MacCsr0); pAd->MACVersion = MacCsr0; if ((pAd->MACVersion != 0x00) && (pAd->MACVersion != 0xFFFFFFFF)) break; if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)) goto err1; RTMPusecDelay(10); } while (index++ < 100); DBGPRINT(RT_DEBUG_TRACE, ("MAC_CSR0 [ Ver:Rev=0x%08x]\n", pAd->MACVersion)); #ifdef RTMP_MAC_PCI #if defined(RT3090) || defined(RT3592) || defined(RT3390) || defined(RT3593) /*Iverson patch PCIE L1 issue to make sure that driver can be read,write ,BBP and RF register at pcie L.1 level */ if ((IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd) || IS_RT3593(pAd))&&pAd->infType==RTMP_DEV_INF_PCIE) { RTMP_IO_READ32(pAd, AUX_CTRL, &MacCsr0); MacCsr0 |= 0x402; RTMP_IO_WRITE32(pAd, AUX_CTRL, MacCsr0); DBGPRINT(RT_DEBUG_TRACE, ("AUX_CTRL = 0x%x\n", MacCsr0)); } #endif // RT3090 // // To fix driver disable/enable hang issue when radio off RTMP_IO_WRITE32(pAd, PWR_PIN_CFG, 0x2); #endif // RTMP_MAC_PCI // // Disable DMA RT28XXDMADisable(pAd); // Load 8051 firmware Status = NICLoadFirmware(pAd); if (Status != NDIS_STATUS_SUCCESS) { DBGPRINT_ERR(("NICLoadFirmware failed, Status[=0x%08x]\n", Status)); goto err1; } NICLoadRateSwitchingParams(pAd); // Disable interrupts here which is as soon as possible // This statement should never be true. We might consider to remove it later #ifdef RTMP_MAC_PCI if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_ACTIVE)) { RTMP_ASIC_INTERRUPT_DISABLE(pAd); } #endif // RTMP_MAC_PCI // #ifdef RESOURCE_PRE_ALLOC Status = RTMPInitTxRxRingMemory(pAd); #else Status = RTMPAllocTxRxRingMemory(pAd); #endif // RESOURCE_PRE_ALLOC // if (Status != NDIS_STATUS_SUCCESS) { DBGPRINT_ERR(("RTMPAllocTxRxMemory failed, Status[=0x%08x]\n", Status)); goto err2; } RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_IN_USE); // initialize MLME // Status = RtmpMgmtTaskInit(pAd); if (Status != NDIS_STATUS_SUCCESS) goto err3; Status = MlmeInit(pAd); if (Status != NDIS_STATUS_SUCCESS) { DBGPRINT_ERR(("MlmeInit failed, Status[=0x%08x]\n", Status)); goto err4; } #ifdef RMTP_RBUS_SUPPORT #ifdef VIDEO_TURBINE_SUPPORT VideoConfigInit(pAd); #endif // VIDEO_TURBINE_SUPPORT // #endif // RMTP_RBUS_SUPPORT // // Initialize pAd->StaCfg, pAd->ApCfg, pAd->CommonCfg to manufacture default // UserCfgInit(pAd); Status = RtmpNetTaskInit(pAd); if (Status != NDIS_STATUS_SUCCESS) goto err5; // COPY_MAC_ADDR(pAd->ApCfg.MBSSID[apidx].Bssid, netif->hwaddr); // pAd->bForcePrintTX = TRUE; CfgInitHook(pAd); #ifdef BLOCK_NET_IF initblockQueueTab(pAd); #endif // BLOCK_NET_IF // Status = MeasureReqTabInit(pAd); if (Status != NDIS_STATUS_SUCCESS) { DBGPRINT_ERR(("MeasureReqTabInit failed, Status[=0x%08x]\n",Status)); goto err6; } Status = TpcReqTabInit(pAd); if (Status != NDIS_STATUS_SUCCESS) { DBGPRINT_ERR(("TpcReqTabInit failed, Status[=0x%08x]\n",Status)); goto err6; } // // Init the hardware, we need to init asic before read registry, otherwise mac register will be reset // Status = NICInitializeAdapter(pAd, TRUE); if (Status != NDIS_STATUS_SUCCESS) { DBGPRINT_ERR(("NICInitializeAdapter failed, Status[=0x%08x]\n", Status)); if (Status != NDIS_STATUS_SUCCESS) goto err6; } // Read parameters from Config File /* unknown, it will be updated in NICReadEEPROMParameters */ pAd->RfIcType = RFIC_UNKNOWN; Status = RTMPReadParametersHook(pAd); #ifdef CREDENTIAL_STORE RecoverConnectInfo(pAd); #endif /* CREDENTIAL_STORE */ DBGPRINT(RT_DEBUG_OFF, ("1. Phy Mode = %d\n", pAd->CommonCfg.PhyMode)); if (Status != NDIS_STATUS_SUCCESS) { DBGPRINT_ERR(("RTMPReadParametersHook failed, Status[=0x%08x]\n",Status)); goto err6; } #ifdef DOT11_N_SUPPORT //Init Ba Capability parameters. // RT28XX_BA_INIT(pAd); pAd->CommonCfg.DesiredHtPhy.MpduDensity = (UCHAR)pAd->CommonCfg.BACapability.field.MpduDensity; pAd->CommonCfg.DesiredHtPhy.AmsduEnable = (USHORT)pAd->CommonCfg.BACapability.field.AmsduEnable; pAd->CommonCfg.DesiredHtPhy.AmsduSize = (USHORT)pAd->CommonCfg.BACapability.field.AmsduSize; pAd->CommonCfg.DesiredHtPhy.MimoPs = (USHORT)pAd->CommonCfg.BACapability.field.MMPSmode; // UPdata to HT IE pAd->CommonCfg.HtCapability.HtCapInfo.MimoPs = (USHORT)pAd->CommonCfg.BACapability.field.MMPSmode; pAd->CommonCfg.HtCapability.HtCapInfo.AMsduSize = (USHORT)pAd->CommonCfg.BACapability.field.AmsduSize; pAd->CommonCfg.HtCapability.HtCapParm.MpduDensity = (UCHAR)pAd->CommonCfg.BACapability.field.MpduDensity; #endif // DOT11_N_SUPPORT // // after reading Registry, we now know if in AP mode or STA mode // Load 8051 firmware; crash when FW image not existent // Status = NICLoadFirmware(pAd); // if (Status != NDIS_STATUS_SUCCESS) // break; DBGPRINT(RT_DEBUG_OFF, ("2. Phy Mode = %d\n", pAd->CommonCfg.PhyMode)); // We should read EEPROM for all cases. rt2860b NICReadEEPROMParameters(pAd, (PUCHAR)pDefaultMac); #ifdef CONFIG_STA_SUPPORT #endif // CONFIG_STA_SUPPORT // DBGPRINT(RT_DEBUG_OFF, ("3. Phy Mode = %d\n", pAd->CommonCfg.PhyMode)); NICInitAsicFromEEPROM(pAd); //rt2860b #ifdef RTMP_INTERNAL_TX_ALC // // Initialize the desired TSSI table // InitDesiredTSSITable(pAd); #endif // RTMP_INTERNAL_TX_ALC // // Set PHY to appropriate mode TmpPhy = pAd->CommonCfg.PhyMode; pAd->CommonCfg.PhyMode = 0xff; RTMPSetPhyMode(pAd, TmpPhy); #ifdef DOT11_N_SUPPORT SetCommonHT(pAd); #endif // DOT11_N_SUPPORT // // No valid channels. if (pAd->ChannelListNum == 0) { DBGPRINT(RT_DEBUG_ERROR, ("Wrong configuration. No valid channel found. Check \"ContryCode\" and \"ChannelGeography\" setting.\n")); goto err6; } #ifdef DOT11_N_SUPPORT DBGPRINT(RT_DEBUG_OFF, ("MCS Set = %02x %02x %02x %02x %02x\n", pAd->CommonCfg.HtCapability.MCSSet[0], pAd->CommonCfg.HtCapability.MCSSet[1], pAd->CommonCfg.HtCapability.MCSSet[2], pAd->CommonCfg.HtCapability.MCSSet[3], pAd->CommonCfg.HtCapability.MCSSet[4])); #endif // DOT11_N_SUPPORT // // APInitialize(pAd); #ifdef IKANOS_VX_1X0 VR_IKANOS_FP_Init(pAd->ApCfg.BssidNum, pAd->PermanentAddress); #endif // IKANOS_VX_1X0 // /* Some modules init must be called before APStartUp(). Or APStartUp() will make up beacon content and call other modules API to get some information to fill. */ if (pAd && (Status != NDIS_STATUS_SUCCESS)) { // // Undo everything if it failed // if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_IN_USE)) { // NdisMDeregisterInterrupt(&pAd->Interrupt); RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_IN_USE); } // RTMPFreeAdapter(pAd); // we will free it in disconnect() } else if (pAd) { // Microsoft HCT require driver send a disconnect event after driver initialization. OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_MEDIA_STATE_CONNECTED); RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_MEDIA_STATE_CHANGE); DBGPRINT(RT_DEBUG_TRACE, ("NDIS_STATUS_MEDIA_DISCONNECT Event B!\n")); }// end of else // Set up the Mac address RtmpOSNetDevAddrSet(pAd->net_dev, &pAd->CurrentAddress[0]); // Various AP function init #ifdef CONFIG_STA_SUPPORT IF_DEV_CONFIG_OPMODE_ON_STA(pAd) { #ifdef WPA_SUPPLICANT_SUPPORT #ifndef NATIVE_WPA_SUPPLICANT_SUPPORT // send wireless event to wpa_supplicant for infroming interface up. RtmpOSWrielessEventSend(pAd, IWEVCUSTOM, RT_INTERFACE_UP, NULL, NULL, 0); #endif // NATIVE_WPA_SUPPLICANT_SUPPORT // #endif // WPA_SUPPLICANT_SUPPORT // } #endif // CONFIG_STA_SUPPORT // #ifdef RT33xx if (IS_RT3390(pAd)) { RTMP_TxEvmCalibration(pAd); } #endif // RT33xx // DBGPRINT_S(Status, ("<==== rt28xx_init, Status=%x\n", Status)); return TRUE; err6: MeasureReqTabExit(pAd); TpcReqTabExit(pAd); err5: RtmpNetTaskExit(pAd); UserCfgExit(pAd); err4: MlmeHalt(pAd); err3: RtmpMgmtTaskExit(pAd); err2: #ifdef RESOURCE_PRE_ALLOC RTMPResetTxRxRingMemory(pAd); #else RTMPFreeTxRxRingMemory(pAd); #endif // RESOURCE_PRE_ALLOC // err1: #ifdef DOT11_N_SUPPORT if(pAd->mpdu_blk_pool.mem) os_free_mem(pAd, pAd->mpdu_blk_pool.mem); // free BA pool #endif // DOT11_N_SUPPORT // // shall not set priv to NULL here because the priv didn't been free yet. //net_dev->priv = 0; #ifdef INF_AMAZON_SE err0: #endif // INF_AMAZON_SE // #ifdef ST err0: #endif // ST // DBGPRINT(RT_DEBUG_ERROR, ("!!! rt28xx Initialized fail !!!\n")); return FALSE; }
int rtmp_ee_prom_write16( IN PRTMP_ADAPTER pAd, IN USHORT Offset, IN USHORT Data) { UINT32 x; #ifdef RT30xx #ifdef ANT_DIVERSITY_SUPPORT if (pAd->NicConfig2.field.AntDiversity) { pAd->EepromAccess = TRUE; } #endif // ANT_DIVERSITY_SUPPORT // #endif // RT30xx // Offset /= 2; EWEN(pAd); // reset bits and set EECS RTMP_IO_READ32(pAd, E2PROM_CSR, &x); x &= ~(EEDI | EEDO | EESK); x |= EECS; RTMP_IO_WRITE32(pAd, E2PROM_CSR, x); // patch can not access e-Fuse issue if (!(IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd) || IS_RT3593(pAd))) { // kick a pulse RaiseClock(pAd, &x); LowerClock(pAd, &x); } // output the read_opcode ,register number and data in that order ShiftOutBits(pAd, EEPROM_WRITE_OPCODE, 3); ShiftOutBits(pAd, Offset, pAd->EEPROMAddressNum); ShiftOutBits(pAd, Data, 16); // 16-bit access // read DO status RTMP_IO_READ32(pAd, E2PROM_CSR, &x); EEpromCleanup(pAd); RTMPusecDelay(10000); //delay for twp(MAX)=10ms EWDS(pAd); EEpromCleanup(pAd); #ifdef RT30xx #ifdef ANT_DIVERSITY_SUPPORT // Antenna and EEPROM access are both using EESK pin, // Therefor we should avoid accessing EESK at the same time // Then restore antenna after EEPROM access if ((pAd->NicConfig2.field.AntDiversity) /*|| (pAd->RfIcType == RFIC_3020)*/) { pAd->EepromAccess = FALSE; AsicSetRxAnt(pAd, pAd->RxAnt.Pair1PrimaryRxAnt); } #endif // ANT_DIVERSITY_SUPPORT // #endif // RT30xx // return NDIS_STATUS_SUCCESS; }
/* ========================================================================== Description: Reverse RF sleep-mode setup ========================================================================== */ VOID RT30xxReverseRFSleepModeSetup( IN PRTMP_ADAPTER pAd) { UCHAR RFValue; UINT32 MACValue; if(!IS_RT3572(pAd)) { #ifdef RT53xx if (IS_RT5390(pAd)) { UCHAR rfreg; RT30xxReadRFRegister(pAd, RF_R01, &rfreg); if (IS_RT5392(pAd)) { rfreg = ((rfreg & ~0x3F) | 0x3F); } else { rfreg = ((rfreg & ~0x0F) | 0x0F); // Enable rf_block_en, pll_en, rx0_en and tx0_en } RT30xxWriteRFRegister(pAd, RF_R01, rfreg); RT30xxReadRFRegister(pAd, RF_R06, &rfreg); if (IS_RT5390F(pAd) || IS_RT5392C(pAd)) { rfreg = ((rfreg & ~0xC0) | 0xC0); // vco_ic (VCO bias current control, 11: high) } else { rfreg = ((rfreg & ~0xC0) | 0x80); // vco_ic (VCO bias current control, 10: mid.) } RT30xxWriteRFRegister(pAd, RF_R06, rfreg); if (!IS_RT5392(pAd)) { RT30xxReadRFRegister(pAd, RF_R02, &rfreg); rfreg = ((rfreg & ~0x80) | 0x80); // rescal_en (initiate calibration) RT30xxWriteRFRegister(pAd, RF_R02, rfreg); } RT30xxReadRFRegister(pAd, RF_R22, &rfreg); rfreg = ((rfreg & ~0xE0) | 0x20); // cp_ic (reference current control, 001: 0.33 mA) RT30xxWriteRFRegister(pAd, RF_R22, rfreg); RT30xxReadRFRegister(pAd, RF_R42, &rfreg); rfreg = ((rfreg & ~0x40) | 0x40); // rx_ctb_en RT30xxWriteRFRegister(pAd, RF_R42, rfreg); RT30xxReadRFRegister(pAd, RF_R20, &rfreg); rfreg = ((rfreg & ~0x77) | 0x00); // ldo_rf_vc and ldo_pll_vc ( 111: +0.15) RT30xxWriteRFRegister(pAd, RF_R20, rfreg); RT30xxReadRFRegister(pAd, RF_R03, &rfreg); rfreg = ((rfreg & ~0x80) | 0x80); // vcocal_en (initiate VCO calibration (reset after completion)) RT30xxWriteRFRegister(pAd, RF_R03, rfreg); } else #endif // RT53xx // { // RF_BLOCK_en, RF R1 register Bit 0 to 1 RT30xxReadRFRegister(pAd, RF_R01, &RFValue); RFValue |= 0x01; RT30xxWriteRFRegister(pAd, RF_R01, RFValue); // VCO_IC, RF R7 register Bit 5 to 1 (VCO bias current control, 11: high) RT30xxReadRFRegister(pAd, RF_R07, &RFValue); RFValue |= 0x30; RT30xxWriteRFRegister(pAd, RF_R07, RFValue); // Idoh, RF R9 register Bit 1, Bit 2 & Bit 3 to 1 RT30xxReadRFRegister(pAd, RF_R09, &RFValue); RFValue |= 0x0E; RT30xxWriteRFRegister(pAd, RF_R09, RFValue); // RX_CTB_en, RF R21 register Bit 7 to 1 RT30xxReadRFRegister(pAd, RF_R21, &RFValue); RFValue |= 0x80; RT30xxWriteRFRegister(pAd, RF_R21, RFValue); } } if (IS_RT3090(pAd) || // IS_RT3090 including RT309x and RT3071/72 IS_RT3572(pAd) || IS_RT3390(pAd) || IS_RT3593(pAd) || IS_RT5390(pAd) || (IS_RT3070(pAd) && ((pAd->MACVersion & 0xffff) < 0x0201))) { if ((!IS_RT3572(pAd)) && (!IS_RT3593(pAd)) && (!IS_RT5390(pAd)) && (!IS_RT3390(pAd)) && (!IS_RT3090(pAd))) { RT30xxReadRFRegister(pAd, RF_R27, &RFValue); if ((pAd->MACVersion & 0xffff) < 0x0211) RFValue = (RFValue & (~0x77)) | 0x3; else RFValue = (RFValue & (~0x77)); RT30xxWriteRFRegister(pAd, RF_R27, RFValue); } // RT3071 version E has fixed this issue if ((pAd->NicConfig2.field.DACTestBit == 1) && ((pAd->MACVersion & 0xffff) < 0x0211)) { // patch tx EVM issue temporarily RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue); MACValue = ((MACValue & 0xE0FFFFFF) | 0x0D000000); RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue); } // else if ((!IS_RT3090(pAd) && !IS_RT3593(pAd)) || (pAd->CommonCfg.PatchHWControl.field.LDOCfg == 1)) else if ((!IS_RT3090(pAd) && !IS_RT3593(pAd) && !IS_RT5390(pAd))) { RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue); MACValue = ((MACValue & 0xE0FFFFFF) | 0x01000000); RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue); } } if(IS_RT3572(pAd)) RT30xxWriteRFRegister(pAd, RF_R08, 0x80); }
VOID FrequencyCalibration( IN PRTMP_ADAPTER pAd) { BOOLEAN bUpdateRFR = FALSE; UCHAR RFValue = 0; UCHAR PreRFValue = 0; CHAR HighFreqTriggerPoint = 0, LowFreqTriggerPoint = 0; CHAR DecreaseFreqOffset = 0, IncreaseFreqOffset = 0; /* Frequency calibration period: */ /* a) 10 seconds: Check the reported frequency offset*/ /* b) 500 ms: Update the RF frequency if possible*/ if ((pAd->FreqCalibrationCtrl.bEnableFrequencyCalibration == TRUE) && (((pAd->FreqCalibrationCtrl.bApproachFrequency == FALSE) && ((pAd->Mlme.PeriodicRound % FREQUENCY_CALIBRATION_PERIOD) == 0)) || ((pAd->FreqCalibrationCtrl.bApproachFrequency == TRUE) && ((pAd->Mlme.PeriodicRound % (FREQUENCY_CALIBRATION_PERIOD / 20)) == 0)))) { DBGPRINT(RT_DEBUG_TRACE, ("---> %s\n", __FUNCTION__)); if (pAd->FreqCalibrationCtrl.bSkipFirstFrequencyCalibration == TRUE) { pAd->FreqCalibrationCtrl.bSkipFirstFrequencyCalibration = FALSE; DBGPRINT(RT_DEBUG_TRACE, ("%s: Skip cuurent frequency calibration (avoid calibrating frequency at the time the STA is just link-up)\n", __FUNCTION__)); } else { if (pAd->FreqCalibrationCtrl.LatestFreqOffsetOverBeacon != INVALID_FREQUENCY_OFFSET) { /* Sync the thresholds*/ if (pAd->FreqCalibrationCtrl.BeaconPhyMode == MODE_CCK) /* CCK*/ { HighFreqTriggerPoint = HIGH_FREQUENCY_TRIGGER_POINT_CCK; LowFreqTriggerPoint = LOW_FREQUENCY_TRIGGER_POINT_CCK; DecreaseFreqOffset = DECREASE_FREQUENCY_OFFSET_CCK; IncreaseFreqOffset = INCREASE_FREQUENCY_OFFSET_CCK; } else /* OFDM*/ { HighFreqTriggerPoint = HIGH_FREQUENCY_TRIGGER_POINT_OFDM; LowFreqTriggerPoint = LOW_FREQUENCY_TRIGGER_POINT_OFDM; DecreaseFreqOffset = DECREASE_FREQUENCY_OFFSET_OFDM; IncreaseFreqOffset = INCREASE_FREQUENCY_OFFSET_OFDM; } if ((pAd->FreqCalibrationCtrl.LatestFreqOffsetOverBeacon >= HighFreqTriggerPoint) || (pAd->FreqCalibrationCtrl.LatestFreqOffsetOverBeacon <= LowFreqTriggerPoint)) { pAd->FreqCalibrationCtrl.bApproachFrequency = TRUE; } if (pAd->FreqCalibrationCtrl.bApproachFrequency == TRUE) { if ((pAd->FreqCalibrationCtrl.LatestFreqOffsetOverBeacon <= DecreaseFreqOffset) && (pAd->FreqCalibrationCtrl.LatestFreqOffsetOverBeacon >= IncreaseFreqOffset)) { pAd->FreqCalibrationCtrl.bApproachFrequency = FALSE; /* Stop approaching frquency if -10 < reported frequency offset < 10*/ } else if (pAd->FreqCalibrationCtrl.LatestFreqOffsetOverBeacon > DecreaseFreqOffset) { pAd->FreqCalibrationCtrl.AdaptiveFreqOffset--; if (IS_RT3390(pAd)) { RT30xxReadRFRegister(pAd, RF_R23, (PUCHAR)(&RFValue)); RFValue = ((RFValue & ~0x7F) | (pAd->FreqCalibrationCtrl.AdaptiveFreqOffset & 0x7F)); RFValue = min(RFValue, ((UCHAR)0x5F));// warning!! by sw pAd->FreqCalibrationCtrl.AdaptiveFreqOffset = RFValue; /* Keep modified RF R23 value */ RT30xxWriteRFRegister(pAd, RF_R23, (UCHAR)RFValue); RT30xxReadRFRegister(pAd, RF_R07, (PUCHAR)(&RFValue)); RFValue = ((RFValue & ~0x01) | 0x01); /* Tune_en (initiate VCO calibration (reset after completion)) */ RT30xxWriteRFRegister(pAd, RF_R07, (UCHAR)RFValue); } else if (IS_RT5390(pAd)) { RT30xxReadRFRegister(pAd, RF_R17, (PUCHAR)(&RFValue)); PreRFValue = RFValue; RFValue = ((RFValue & ~0x7F) | (pAd->FreqCalibrationCtrl.AdaptiveFreqOffset & 0x7F)); RFValue = min(RFValue, ((UCHAR)0x5F));// warning!! by sw pAd->FreqCalibrationCtrl.AdaptiveFreqOffset = RFValue; /* Keep modified RF R17 value */ if (PreRFValue != RFValue) { AsicSendCommandToMcu(pAd, 0x74, 0xff, RFValue, PreRFValue); } RT30xxReadRFRegister(pAd, RF_R03, (PUCHAR)&RFValue); RFValue = ((RFValue & ~0x80) | 0x80); /* vcocal_en (initiate VCO calibration (reset after completion)) - It should be at the end of RF configuration. */ RT30xxWriteRFRegister(pAd, RF_R03, (UCHAR)RFValue); } else if (IS_RT3593(pAd)) { RT30xxReadRFRegister(pAd, RF_R17, (PUCHAR)(&RFValue)); RFValue = ((RFValue & ~0x7F) | (pAd->FreqCalibrationCtrl.AdaptiveFreqOffset & 0x7F)); RFValue = min(RFValue, ((UCHAR)0x5F));// warning!! by sw pAd->FreqCalibrationCtrl.AdaptiveFreqOffset = RFValue; // Keep modified RF R17 value RT30xxWriteRFRegister(pAd, RF_R17, (UCHAR)RFValue); RT30xxReadRFRegister(pAd, RF_R03, (PUCHAR)&RFValue); RFValue = ((RFValue & ~0x80) | 0x80); /* vcocal_en (initiate VCO calibration (reset after completion)) - It should be at the end of RF configuration. */ RT30xxWriteRFRegister(pAd, RF_R03, (UCHAR)RFValue); } else { DBGPRINT(RT_DEBUG_ERROR, ("%s: Not support IC type (MACVersion = 0x%X)\n", __FUNCTION__, pAd->MACVersion)); } DBGPRINT(RT_DEBUG_TRACE, ("%s: -- frequency offset = 0x%X\n", __FUNCTION__, pAd->FreqCalibrationCtrl.AdaptiveFreqOffset)); } else if (pAd->FreqCalibrationCtrl.LatestFreqOffsetOverBeacon < IncreaseFreqOffset) { pAd->FreqCalibrationCtrl.AdaptiveFreqOffset++; if (IS_RT3390(pAd)) { RT30xxReadRFRegister(pAd, RF_R23, (PUCHAR)(&RFValue)); RFValue = ((RFValue & ~0x7F) | (pAd->FreqCalibrationCtrl.AdaptiveFreqOffset & 0x7F)); RFValue = min(RFValue, ((UCHAR)0x5F));// warning!! by sw pAd->FreqCalibrationCtrl.AdaptiveFreqOffset = RFValue; /* Keep modified RF R23 value */ RT30xxWriteRFRegister(pAd, RF_R23, (UCHAR)RFValue); RT30xxReadRFRegister(pAd, RF_R07, (PUCHAR)(&RFValue)); RFValue = ((RFValue & ~0x01) | 0x01); /* Tune_en (initiate VCO calibration (reset after completion)) */ RT30xxWriteRFRegister(pAd, RF_R07, (UCHAR)RFValue); } else if (IS_RT5390(pAd)) { RT30xxReadRFRegister(pAd, RF_R17, (PUCHAR)(&RFValue)); PreRFValue = RFValue; RFValue = ((RFValue & ~0x7F) | (pAd->FreqCalibrationCtrl.AdaptiveFreqOffset & 0x7F)); RFValue = min(RFValue, ((UCHAR)0x5F));// warning!! by sw pAd->FreqCalibrationCtrl.AdaptiveFreqOffset = RFValue; /* Keep modified RF R17 value */ if (PreRFValue != RFValue) { AsicSendCommandToMcu(pAd, 0x74, 0xff, RFValue, PreRFValue); } RT30xxReadRFRegister(pAd, RF_R03, (PUCHAR)&RFValue); RFValue = ((RFValue & ~0x80) | 0x80); /* vcocal_en (initiate VCO calibration (reset after completion)) - It should be at the end of RF configuration.*/ RT30xxWriteRFRegister(pAd, RF_R03, (UCHAR)RFValue); } else if (IS_RT3593(pAd)) { RT30xxReadRFRegister(pAd, RF_R17, (PUCHAR)(&RFValue)); RFValue = ((RFValue & ~0x7F) | (pAd->FreqCalibrationCtrl.AdaptiveFreqOffset & 0x7F)); RFValue = min(RFValue, ((UCHAR)0x5F));// warning!! by sw pAd->FreqCalibrationCtrl.AdaptiveFreqOffset = RFValue; /* Keep modified RF R17 value */ RT30xxWriteRFRegister(pAd, RF_R17, (UCHAR)RFValue); RT30xxReadRFRegister(pAd, RF_R03, (PUCHAR)&RFValue); RFValue = ((RFValue & ~0x80) | 0x80); /* vcocal_en (initiate VCO calibration (reset after completion)) - It should be at the end of RF configuration. */ RT30xxWriteRFRegister(pAd, RF_R03, (UCHAR)RFValue); } else { DBGPRINT(RT_DEBUG_ERROR, ("%s: Not support IC type (MACVersion = 0x%X)\n", __FUNCTION__, pAd->MACVersion)); } DBGPRINT(RT_DEBUG_TRACE, ("%s: ++ frequency offset = 0x%X\n", __FUNCTION__, pAd->FreqCalibrationCtrl.AdaptiveFreqOffset)); } } DBGPRINT(RT_DEBUG_TRACE, ("%s: AdaptiveFreqOffset = %d, LatestFreqOffsetOverBeacon = %d, bApproachFrequency = %d\n", __FUNCTION__, pAd->FreqCalibrationCtrl.AdaptiveFreqOffset, pAd->FreqCalibrationCtrl.LatestFreqOffsetOverBeacon, pAd->FreqCalibrationCtrl.bApproachFrequency)); } } DBGPRINT(RT_DEBUG_TRACE, ("<--- %s\n", __FUNCTION__)); } }
/* ======================================================================== Routine Description: Write RT30xx RF register through MAC Arguments: Return Value: IRQL = Note: ======================================================================== */ NDIS_STATUS RT30xxWriteRFRegister( IN PRTMP_ADAPTER pAd, IN UCHAR regID, IN UCHAR value) { RF_CSR_CFG_STRUC rfcsr = { { 0 } }; UINT i = 0; #ifdef RT3593 RF_CSR_CFG_EXT_STRUC RfCsrCfgExt = { { 0 } }; #endif // RT3593 // #ifdef RT3593 if (IS_RT3593(pAd)) { ASSERT((regID <= 63)); // R0~R63 do { RTMP_IO_READ32(pAd, RF_CSR_CFG, &RfCsrCfgExt.word); if (!RfCsrCfgExt.field.RF_CSR_KICK) { break; } i++; } while ((i < MAX_BUSY_COUNT) && (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST))) ; // Do nothing if ((i == MAX_BUSY_COUNT) || (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST))) { DBGPRINT_RAW(RT_DEBUG_ERROR, ("Retry count exhausted or device removed!!!\n")); return STATUS_UNSUCCESSFUL; } RfCsrCfgExt.field.RF_CSR_WR = 1; RfCsrCfgExt.field.RF_CSR_KICK = 1; RfCsrCfgExt.field.TESTCSR_RFACC_REGNUM = regID; // R0~R63 RfCsrCfgExt.field.RF_CSR_DATA = value; RTMP_IO_WRITE32(pAd, RF_CSR_CFG, RfCsrCfgExt.word); } else #endif // RT3593 // { ASSERT((regID <= 31)); // R0~R31 do { RTMP_IO_READ32(pAd, RF_CSR_CFG, &rfcsr.word); if (!rfcsr.field.RF_CSR_KICK) break; i++; } while ((i < RETRY_LIMIT) && (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST))); if ((i == RETRY_LIMIT) || (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST))) { DBGPRINT_RAW(RT_DEBUG_ERROR, ("Retry count exhausted or device removed!!!\n")); return STATUS_UNSUCCESSFUL; } rfcsr.field.RF_CSR_WR = 1; rfcsr.field.RF_CSR_KICK = 1; rfcsr.field.TESTCSR_RFACC_REGNUM = regID; // R0~R31 rfcsr.field.RF_CSR_DATA = value; RTMP_IO_WRITE32(pAd, RF_CSR_CFG, rfcsr.word); } return NDIS_STATUS_SUCCESS; }
/* ======================================================================== Routine Description: Read RT30xx RF register through MAC Arguments: Return Value: IRQL = Note: ======================================================================== */ NDIS_STATUS RT30xxReadRFRegister( IN PRTMP_ADAPTER pAd, IN UCHAR regID, IN PUCHAR pValue) { RF_CSR_CFG_STRUC rfcsr = { { 0 } }; UINT i=0, k=0; #ifdef RT3593 RF_CSR_CFG_EXT_STRUC RfCsrCfgExt = { { 0 } }; #endif // RT3593 // #ifdef RT3593 if (IS_RT3593(pAd)) { ASSERT((regID <= 63)); // R0~R63 for (i = 0; i < MAX_BUSY_COUNT; i++) { RTMP_IO_READ32(pAd, RF_CSR_CFG, &RfCsrCfgExt.word); if (RfCsrCfgExt.field.RF_CSR_KICK == BUSY) { continue; } RfCsrCfgExt.word = 0; RfCsrCfgExt.field.RF_CSR_WR = 0; RfCsrCfgExt.field.RF_CSR_KICK = 1; RfCsrCfgExt.field.TESTCSR_RFACC_REGNUM = regID; // R0~R63 RTMP_IO_WRITE32(pAd, RF_CSR_CFG, RfCsrCfgExt.word); for (k = 0; k < MAX_BUSY_COUNT; k++) { RTMP_IO_READ32(pAd, RF_CSR_CFG, &RfCsrCfgExt.word); if (RfCsrCfgExt.field.RF_CSR_KICK == IDLE) { break; } } if ((RfCsrCfgExt.field.RF_CSR_KICK == IDLE) && (RfCsrCfgExt.field.TESTCSR_RFACC_REGNUM == regID)) { *pValue = (UCHAR)(RfCsrCfgExt.field.RF_CSR_DATA); break; } } if (RfCsrCfgExt.field.RF_CSR_KICK == BUSY) { DBGPRINT_ERR(("RF read R%d = 0x%X fail, i[%d], k[%d]\n", regID, (UINT32)RfCsrCfgExt.word, i, k)); return STATUS_UNSUCCESSFUL; } } else #endif // RT3593 // { ASSERT((regID <= 31)); // R0~R31 for (i=0; i<MAX_BUSY_COUNT; i++) { RTMP_IO_READ32(pAd, RF_CSR_CFG, &rfcsr.word); if (rfcsr.field.RF_CSR_KICK == BUSY) { continue; } rfcsr.word = 0; rfcsr.field.RF_CSR_WR = 0; rfcsr.field.RF_CSR_KICK = 1; rfcsr.field.TESTCSR_RFACC_REGNUM = regID; RTMP_IO_WRITE32(pAd, RF_CSR_CFG, rfcsr.word); for (k=0; k<MAX_BUSY_COUNT; k++) { RTMP_IO_READ32(pAd, RF_CSR_CFG, &rfcsr.word); if (rfcsr.field.RF_CSR_KICK == IDLE) break; } if ((rfcsr.field.RF_CSR_KICK == IDLE) && (rfcsr.field.TESTCSR_RFACC_REGNUM == regID)) { *pValue = (UCHAR)(rfcsr.field.RF_CSR_DATA); break; } } if (rfcsr.field.RF_CSR_KICK == BUSY) { DBGPRINT_ERR(("RF read R%d=0x%X fail, i[%d], k[%d]\n", regID, rfcsr.word,i,k)); return STATUS_UNSUCCESSFUL; } } return STATUS_SUCCESS; }
VOID RTMPInitPCIeLinkCtrlValue( IN PRTMP_ADAPTER pAd) { INT pos; USHORT reg16, data2, PCIePowerSaveLevel, Configuration; UINT32 MacValue; BOOLEAN bFindIntel = FALSE; POS_COOKIE pObj; pObj = (POS_COOKIE) pAd->OS_Cookie; if (!OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_ADVANCE_POWER_SAVE_PCIE_DEVICE)) { DBGPRINT(RT_DEBUG_TRACE, ("Not PCIe device.\n")); return; } DBGPRINT(RT_DEBUG_TRACE, ("%s.===>\n", __FUNCTION__)); // Init EEPROM, and save settings if (!(IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd) || IS_RT3593(pAd))) { RT28xx_EEPROM_READ16(pAd, 0x22, PCIePowerSaveLevel); pAd->PCIePowerSaveLevel = PCIePowerSaveLevel & 0xff; pAd->LnkCtrlBitMask = 0; if ((PCIePowerSaveLevel&0xff) == 0xff) { OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_ADVANCE_POWER_SAVE_PCIE_DEVICE); DBGPRINT(RT_DEBUG_TRACE, ("====> PCIePowerSaveLevel = 0x%x.\n", PCIePowerSaveLevel)); return; } else { PCIePowerSaveLevel &= 0x3; RT28xx_EEPROM_READ16(pAd, 0x24, data2); if( !(((data2&0xff00) == 0x9200) && ((data2&0x80) !=0)) ) { if (PCIePowerSaveLevel > 1 ) PCIePowerSaveLevel = 1; } DBGPRINT(RT_DEBUG_TRACE, ("====> Write 0x83 = 0x%x.\n", PCIePowerSaveLevel)); AsicSendCommandToMcu(pAd, TRUE, 0x83, 0xff, (UCHAR)PCIePowerSaveLevel, 0x00); RT28xx_EEPROM_READ16(pAd, 0x22, PCIePowerSaveLevel); PCIePowerSaveLevel &= 0xff; PCIePowerSaveLevel = PCIePowerSaveLevel >> 6; switch(PCIePowerSaveLevel) { case 0: // Only support L0 pAd->LnkCtrlBitMask = 0; break; case 1: // Only enable L0s pAd->LnkCtrlBitMask = 1; break; case 2: // enable L1, L0s pAd->LnkCtrlBitMask = 3; break; case 3: // sync with host clk and enable L1, L0s pAd->LnkCtrlBitMask = 0x103; break; } RT28xx_EEPROM_READ16(pAd, 0x24, data2); if ((PCIePowerSaveLevel&0xff) != 0xff) { PCIePowerSaveLevel &= 0x3; if( !(((data2&0xff00) == 0x9200) && ((data2&0x80) !=0)) ) { if (PCIePowerSaveLevel > 1 ) PCIePowerSaveLevel = 1; } DBGPRINT(RT_DEBUG_TRACE, ("====> rt28xx Write 0x83 Command = 0x%x.\n", PCIePowerSaveLevel)); printk("\n\n\n%s:%d\n",__FUNCTION__,__LINE__); AsicSendCommandToMcu(pAd, TRUE, 0x83, 0xff, (UCHAR)PCIePowerSaveLevel, 0x00); } DBGPRINT(RT_DEBUG_TRACE, ("====> LnkCtrlBitMask = 0x%x.\n", pAd->LnkCtrlBitMask)); } }
/* ========================================================================== Description: Load RF normal operation-mode setup ========================================================================== */ VOID RT30xxLoadRFNormalModeSetup( IN PRTMP_ADAPTER pAd) { UCHAR RFValue, bbpreg = 0; #ifdef RT3593 if (IS_RT3593(pAd)) { // improve power consumption RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R138, &bbpreg); if (pAd->Antenna.field.TxPath == 1) { // turn off tx DAC_1 & DAC_2 bbpreg = (bbpreg | 0x60); } else if (pAd->Antenna.field.TxPath == 2) { // turn off tx DAC_2 bbpreg = (bbpreg | 0x40); } if (pAd->Antenna.field.RxPath == 1) { // turn off rx ADC_1 & ADC_2 bbpreg &= (~0x6); } else if (pAd->Antenna.field.RxPath == 2) { // turn off rx ADC_2 bbpreg &= (~0x4); } RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R138, bbpreg); } else #endif // RT3593 // { // improve power consumption RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R138, &bbpreg); if (pAd->Antenna.field.TxPath == 1) { // turn off tx DAC_1 bbpreg = (bbpreg | 0x20); } if (pAd->Antenna.field.RxPath == 1) { // turn off tx ADC_1 bbpreg &= (~0x2); } RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R138, bbpreg); } // RX0_PD & TX0_PD, RF R1 register Bit 2 & Bit 3 to 0 and RF_BLOCK_en,RX1_PD & TX1_PD, Bit0, Bit 4 & Bit5 to 1 RT30xxReadRFRegister(pAd, RF_R01, &RFValue); RFValue = (RFValue & (~0x0C)) | 0x31; RT30xxWriteRFRegister(pAd, RF_R01, RFValue); // TX_LO2_en, RF R15 register Bit 3 to 0 RT30xxReadRFRegister(pAd, RF_R15, &RFValue); RFValue &= (~0x08); RT30xxWriteRFRegister(pAd, RF_R15, RFValue); // TX_LO1_en, RF R17 register Bit 3 to 0 RT30xxReadRFRegister(pAd, RF_R17, &RFValue); RFValue &= (~0x08); // to fix rx long range issue if (((pAd->MACVersion & 0xffff) >= 0x0211) && (pAd->NicConfig2.field.ExternalLNAForG == 0)) { RFValue |= 0x20; } // set RF_R17_bit[2:0] equal to EEPROM setting at 0x48h if (pAd->TxMixerGain24G >= 2) { RFValue &= (~0x7); // clean bit [2:0] RFValue |= pAd->TxMixerGain24G; } RT30xxWriteRFRegister(pAd, RF_R17, RFValue); // RX_LO1_en, RF R20 register Bit 3 to 0 RT30xxReadRFRegister(pAd, RF_R20, &RFValue); RFValue &= (~0x08); RT30xxWriteRFRegister(pAd, RF_R20, RFValue); // RX_LO2_en, RF R21 register Bit 3 to 0 RT30xxReadRFRegister(pAd, RF_R21, &RFValue); RFValue &= (~0x08); RT30xxWriteRFRegister(pAd, RF_R21, RFValue); }
/* ========================================================================== Description: Load RF sleep-mode setup ========================================================================== */ VOID RT30xxLoadRFSleepModeSetup( IN PRTMP_ADAPTER pAd) { UCHAR RFValue; UINT32 MACValue; if(!IS_RT3572(pAd)) { #ifdef RT3593 if (IS_RT3593(pAd)) { UCHAR rfreg; RT30xxReadRFRegister(pAd, RF_R01, &rfreg); rfreg = ((rfreg & ~0x01) | 0x00); // vco_en RT30xxWriteRFRegister(pAd, RF_R01, rfreg); RT30xxReadRFRegister(pAd, RF_R06, &rfreg); rfreg &= (~0x40); // vco_ic (VCO bias current control, 00: off) RT30xxWriteRFRegister(pAd, RF_R06, rfreg); RT30xxReadRFRegister(pAd, RF_R22, &rfreg); rfreg = ((rfreg & ~0xE0) | 0x00); // cp_ic (reference current control, 000: 0.25 mA) RT30xxWriteRFRegister(pAd, RF_R22, rfreg); RT30xxReadRFRegister(pAd, RF_R46, &rfreg); rfreg &= (~0x20); // rx_ctb_en RT30xxWriteRFRegister(pAd, RF_R46, rfreg); RT30xxReadRFRegister(pAd, RF_R20, &rfreg); rfreg |= 0xEE; // ldo_pll_vc and ldo_rf_vc (111: -0.15) RT30xxWriteRFRegister(pAd, RF_R20, rfreg); } else #endif // RT3593 // { // RF_BLOCK_en. RF R1 register Bit 0 to 0 RT30xxReadRFRegister(pAd, RF_R01, &RFValue); RFValue &= (~0x01); RT30xxWriteRFRegister(pAd, RF_R01, RFValue); // VCO_IC, RF R7 register Bit 4 & Bit 5 to 0 RT30xxReadRFRegister(pAd, RF_R07, &RFValue); RFValue &= (~0x30); RT30xxWriteRFRegister(pAd, RF_R07, RFValue); // Idoh, RF R9 register Bit 1, Bit 2 & Bit 3 to 0 RT30xxReadRFRegister(pAd, RF_R09, &RFValue); RFValue &= (~0x0E); RT30xxWriteRFRegister(pAd, RF_R09, RFValue); // RX_CTB_en, RF R21 register Bit 7 to 0 RT30xxReadRFRegister(pAd, RF_R21, &RFValue); RFValue &= (~0x80); RT30xxWriteRFRegister(pAd, RF_R21, RFValue); } } // Don't touch LDO_CFG0 for 3090F & 3593, possibly the board is single power scheme if (IS_RT3090(pAd) || // IS_RT3090 including RT309x and RT3071/72 IS_RT3572(pAd) || (IS_RT3070(pAd) && ((pAd->MACVersion & 0xffff) < 0x0201))) { if (!IS_RT3572(pAd)) { RT30xxReadRFRegister(pAd, RF_R27, &RFValue); RFValue |= 0x77; RT30xxWriteRFRegister(pAd, RF_R27, RFValue); } RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue); MACValue |= 0x1D000000; RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue); } }
RTMP_BUILD_DRV_OPS_FUNCTION_BODY #endif /* OS_ABL_FUNC_SUPPORT */ #endif /* LINUX */ int rt28xx_init( IN VOID *pAdSrc, IN PSTRING pDefaultMac, IN PSTRING pHostName) { PRTMP_ADAPTER pAd = (PRTMP_ADAPTER)pAdSrc; UINT index; UCHAR TmpPhy; NDIS_STATUS Status; if (pAd == NULL) return FALSE; #ifdef RT3290 DBGPRINT(RT_DEBUG_OFF, ("MACVersion=0x%x\n", pAd->MACVersion)); if (IS_RT3290(pAd)) { UINT32 MacRegValue; OSCCTL_STRUC osCtrl = {.word = 0}; CMB_CTRL_STRUC cmbCtrl = {.word = 0}; WLAN_FUN_CTRL_STRUC WlanFunCtrl = {.word = 0}; RTMPEnableWlan(pAd, TRUE, TRUE); // // Too much time for reading efuse(enter/exit L1), and our device will hang up // Disable L1 // RTMP_IO_READ32(pAd, WLAN_FUN_CTRL, &WlanFunCtrl.word); if (WlanFunCtrl.field.WLAN_EN == TRUE) { WlanFunCtrl.field.PCIE_APP0_CLK_REQ = TRUE; RTMP_IO_WRITE32(pAd, WLAN_FUN_CTRL, WlanFunCtrl.word); } //Enable ROSC_EN first then CAL_REQ RTMP_IO_READ32(pAd, OSCCTL, &osCtrl.word); osCtrl.field.ROSC_EN = TRUE; //HW force RTMP_IO_WRITE32(pAd, OSCCTL, osCtrl.word); osCtrl.field.ROSC_EN = TRUE; //HW force osCtrl.field.CAL_REQ = TRUE; osCtrl.field.REF_CYCLE = 0x27; RTMP_IO_WRITE32(pAd, OSCCTL, osCtrl.word); RTMP_IO_READ32(pAd, CMB_CTRL, &cmbCtrl.word); pAd->CmbCtrl.word = cmbCtrl.word; // Overwrite default Coex Parameter RTMP_IO_READ32(pAd, COEXCFG0, &MacRegValue); MacRegValue &= ~(0xFF000000); MacRegValue |= 0x5E000000; RTMP_IO_WRITE32(pAd, COEXCFG0, MacRegValue); } if (IS_RT3290LE(pAd)) { PLL_CTRL_STRUC PllCtrl; RTMP_IO_READ32(pAd, PLL_CTRL, &PllCtrl.word); PllCtrl.field.VCO_FIXED_CURRENT_CONTROL = 0x1; RTMP_IO_WRITE32(pAd, PLL_CTRL, PllCtrl.word); } #endif /* RT3290 */ #ifdef CONFIG_STA_SUPPORT #ifdef PCIE_PS_SUPPORT IF_DEV_CONFIG_OPMODE_ON_STA(pAd) { /* If dirver doesn't wake up firmware here,*/ /* NICLoadFirmware will hang forever when interface is up again.*/ if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE) && OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_ADVANCE_POWER_SAVE_PCIE_DEVICE)) { AUTO_WAKEUP_STRUC AutoWakeupCfg; AsicForceWakeup(pAd, TRUE); AutoWakeupCfg.word = 0; RTMP_IO_WRITE32(pAd, AUTO_WAKEUP_CFG, AutoWakeupCfg.word); OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_DOZE); } } #endif /* PCIE_PS_SUPPORT */ #endif /* CONFIG_STA_SUPPORT */ /* reset Adapter flags*/ RTMP_CLEAR_FLAGS(pAd); /* Init BssTab & ChannelInfo tabbles for auto channel select.*/ #ifdef DOT11_N_SUPPORT /* Allocate BA Reordering memory*/ if (ba_reordering_resource_init(pAd, MAX_REORDERING_MPDU_NUM) != TRUE) goto err1; #endif /* DOT11_N_SUPPORT */ /* Make sure MAC gets ready.*/ index = 0; if (WaitForAsicReady(pAd) != TRUE) goto err1; DBGPRINT(RT_DEBUG_TRACE, ("MAC[Ver:Rev=0x%08x]\n", pAd->MACVersion)); if (MAX_LEN_OF_MAC_TABLE > MAX_AVAILABLE_CLIENT_WCID(pAd)) { DBGPRINT(RT_DEBUG_ERROR, ("MAX_LEN_OF_MAC_TABLE can not be larger than MAX_AVAILABLE_CLIENT_WCID!!!!\n")); goto err1; } #ifdef RTMP_MAC_PCI #if defined(RT3090) || defined(RT3592) || defined(RT3390) || defined(RT3593) || defined(RT5390) || defined(RT5392) || defined(RT5592) /*Iverson patch PCIE L1 issue to make sure that driver can be read,write ,BBP and RF register at pcie L.1 level */ if ((IS_RT3090(pAd) || IS_RT3572(pAd) ||IS_RT3390(pAd) || IS_RT3593(pAd) || IS_RT5390(pAd) || IS_RT5392(pAd) || IS_RT5592(pAd)) &&pAd->infType==RTMP_DEV_INF_PCIE) { UINT32 MacValue = 0; RTMP_IO_READ32(pAd, AUX_CTRL, &MacValue); MacValue |= 0x402; RTMP_IO_WRITE32(pAd, AUX_CTRL, MacValue); DBGPRINT(RT_DEBUG_TRACE, ("AUX_CTRL = 0x%x\n", MacValue)); } #endif /* To fix driver disable/enable hang issue when radio off*/ RTMP_IO_WRITE32(pAd, PWR_PIN_CFG, 0x2); #endif /* RTMP_MAC_PCI */ /* Disable DMA*/ RT28XXDMADisable(pAd); /* Load 8051 firmware*/ Status = NICLoadFirmware(pAd); if (Status != NDIS_STATUS_SUCCESS) { DBGPRINT_ERR(("NICLoadFirmware failed, Status[=0x%08x]\n", Status)); goto err1; } NICLoadRateSwitchingParams(pAd); /* Disable interrupts here which is as soon as possible*/ /* This statement should never be true. We might consider to remove it later*/ #ifdef RTMP_MAC_PCI if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_ACTIVE)) { RTMP_ASIC_INTERRUPT_DISABLE(pAd); } #endif /* RTMP_MAC_PCI */ #ifdef RESOURCE_PRE_ALLOC Status = RTMPInitTxRxRingMemory(pAd); #else Status = RTMPAllocTxRxRingMemory(pAd); #endif /* RESOURCE_PRE_ALLOC */ if (Status != NDIS_STATUS_SUCCESS) { DBGPRINT_ERR(("RTMPAllocTxRxMemory failed, Status[=0x%08x]\n", Status)); goto err2; } RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_IN_USE); /* initialize MLME*/ Status = RtmpMgmtTaskInit(pAd); if (Status != NDIS_STATUS_SUCCESS) goto err3; Status = MlmeInit(pAd); if (Status != NDIS_STATUS_SUCCESS) { DBGPRINT_ERR(("MlmeInit failed, Status[=0x%08x]\n", Status)); goto err4; } #ifdef RMTP_RBUS_SUPPORT #ifdef VIDEO_TURBINE_SUPPORT VideoConfigInit(pAd); #endif /* VIDEO_TURBINE_SUPPORT */ #endif /* RMTP_RBUS_SUPPORT */ /* Initialize pAd->StaCfg, pAd->ApCfg, pAd->CommonCfg to manufacture default*/ UserCfgInit(pAd); Status = RtmpNetTaskInit(pAd); if (Status != NDIS_STATUS_SUCCESS) goto err5; /* COPY_MAC_ADDR(pAd->ApCfg.MBSSID[apidx].Bssid, netif->hwaddr);*/ /* pAd->bForcePrintTX = TRUE;*/ CfgInitHook(pAd); #ifdef BLOCK_NET_IF initblockQueueTab(pAd); #endif /* BLOCK_NET_IF */ Status = MeasureReqTabInit(pAd); if (Status != NDIS_STATUS_SUCCESS) { DBGPRINT_ERR(("MeasureReqTabInit failed, Status[=0x%08x]\n",Status)); goto err6; } Status = TpcReqTabInit(pAd); if (Status != NDIS_STATUS_SUCCESS) { DBGPRINT_ERR(("TpcReqTabInit failed, Status[=0x%08x]\n",Status)); goto err6; } /* Init the hardware, we need to init asic before read registry, otherwise mac register will be reset*/ Status = NICInitializeAdapter(pAd, TRUE); if (Status != NDIS_STATUS_SUCCESS) { DBGPRINT_ERR(("NICInitializeAdapter failed, Status[=0x%08x]\n", Status)); if (Status != NDIS_STATUS_SUCCESS) goto err6; } /* Read parameters from Config File */ /* unknown, it will be updated in NICReadEEPROMParameters */ pAd->RfIcType = RFIC_UNKNOWN; Status = RTMPReadParametersHook(pAd); #ifdef CONFIG_STA_SUPPORT #ifdef CREDENTIAL_STORE RecoverConnectInfo(pAd); #endif /* CREDENTIAL_STORE */ #endif /* CONFIG_STA_SUPPORT */ DBGPRINT(RT_DEBUG_OFF, ("1. Phy Mode = %d\n", pAd->CommonCfg.PhyMode)); if (Status != NDIS_STATUS_SUCCESS) { DBGPRINT_ERR(("RTMPReadParametersHook failed, Status[=0x%08x]\n",Status)); goto err6; } #ifdef DOT11_N_SUPPORT /*Init Ba Capability parameters.*/ /* RT28XX_BA_INIT(pAd);*/ pAd->CommonCfg.DesiredHtPhy.MpduDensity = (UCHAR)pAd->CommonCfg.BACapability.field.MpduDensity; pAd->CommonCfg.DesiredHtPhy.AmsduEnable = (USHORT)pAd->CommonCfg.BACapability.field.AmsduEnable; pAd->CommonCfg.DesiredHtPhy.AmsduSize = (USHORT)pAd->CommonCfg.BACapability.field.AmsduSize; pAd->CommonCfg.DesiredHtPhy.MimoPs = (USHORT)pAd->CommonCfg.BACapability.field.MMPSmode; /* UPdata to HT IE*/ pAd->CommonCfg.HtCapability.HtCapInfo.MimoPs = (USHORT)pAd->CommonCfg.BACapability.field.MMPSmode; pAd->CommonCfg.HtCapability.HtCapInfo.AMsduSize = (USHORT)pAd->CommonCfg.BACapability.field.AmsduSize; pAd->CommonCfg.HtCapability.HtCapParm.MpduDensity = (UCHAR)pAd->CommonCfg.BACapability.field.MpduDensity; #endif /* DOT11_N_SUPPORT */ /* after reading Registry, we now know if in AP mode or STA mode*/ /* Load 8051 firmware; crash when FW image not existent*/ /* Status = NICLoadFirmware(pAd);*/ /* if (Status != NDIS_STATUS_SUCCESS)*/ /* break;*/ DBGPRINT(RT_DEBUG_OFF, ("2. Phy Mode = %d\n", pAd->CommonCfg.PhyMode)); /* We should read EEPROM for all cases. rt2860b*/ NICReadEEPROMParameters(pAd, (PSTRING)pDefaultMac); #ifdef CONFIG_STA_SUPPORT #endif /* CONFIG_STA_SUPPORT */ DBGPRINT(RT_DEBUG_OFF, ("3. Phy Mode = %d\n", pAd->CommonCfg.PhyMode)); #ifdef LED_CONTROL_SUPPORT /* Send LED Setting to MCU */ RTMPInitLEDMode(pAd); #endif /* LED_CONTROL_SUPPORT */ NICInitAsicFromEEPROM(pAd); /* rt2860b */ #ifdef RTMP_FREQ_CALIBRATION_SUPPORT #ifdef CONFIG_STA_SUPPORT /* Initialize the frequency calibration*/ if (pAd->chipCap.FreqCalibrationSupport) FrequencyCalibration(pAd); #endif /* CONFIG_STA_SUPPORT */ #endif /* RTMP_FREQ_CALIBRATION_SUPPORT */ #ifdef RTMP_INTERNAL_TX_ALC /* Initialize the desired TSSI table*/ RTMP_CHIP_ASIC_TSSI_TABLE_INIT(pAd); #endif /* RTMP_INTERNAL_TX_ALC */ #ifdef RTMP_TEMPERATURE_COMPENSATION /* Temperature compensation, initialize the lookup table */ DBGPRINT(RT_DEBUG_OFF, ("bAutoTxAgcG = %d\n", pAd->bAutoTxAgcG)); if (pAd->chipCap.bTempCompTxALC && pAd->bAutoTxAgcG) InitLookupTable(pAd); #endif /* RTMP_TEMPERATURE_COMPENSATION */ #ifdef RTMP_FREQ_CALIBRATION_SUPPORT #ifdef CONFIG_STA_SUPPORT if (pAd->chipCap.FreqCalibrationSupport) InitFrequencyCalibration(pAd); #endif /* CONFIG_STA_SUPPORT */ #endif /* RTMP_FREQ_CALIBRATION_SUPPORT */ /* Set PHY to appropriate mode*/ TmpPhy = pAd->CommonCfg.PhyMode; pAd->CommonCfg.PhyMode = 0xff; RTMPSetPhyMode(pAd, TmpPhy); #ifdef DOT11_N_SUPPORT SetCommonHT(pAd); #endif /* DOT11_N_SUPPORT */ /* No valid channels.*/ if (pAd->ChannelListNum == 0) { DBGPRINT(RT_DEBUG_ERROR, ("Wrong configuration. No valid channel found. Check \"ContryCode\" and \"ChannelGeography\" setting.\n")); goto err6; } #ifdef DOT11_N_SUPPORT DBGPRINT(RT_DEBUG_OFF, ("MCS Set = %02x %02x %02x %02x %02x\n", pAd->CommonCfg.HtCapability.MCSSet[0], pAd->CommonCfg.HtCapability.MCSSet[1], pAd->CommonCfg.HtCapability.MCSSet[2], pAd->CommonCfg.HtCapability.MCSSet[3], pAd->CommonCfg.HtCapability.MCSSet[4])); #endif /* DOT11_N_SUPPORT */ /* APInitialize(pAd);*/ #ifdef IKANOS_VX_1X0 VR_IKANOS_FP_Init(pAd->ApCfg.BssidNum, pAd->PermanentAddress); #endif /* IKANOS_VX_1X0 */ /* Some modules init must be called before APStartUp(). Or APStartUp() will make up beacon content and call other modules API to get some information to fill. */ #ifdef CONFIG_TSO_SUPPORT if (RTMP_TEST_MORE_FLAG(pAd, fRTMP_ADAPTER_TSO_SUPPORT)) RTMPTsoEnable(pAd); #endif /* CONFIG_TSO_SUPPORT */ if (pAd && (Status != NDIS_STATUS_SUCCESS)) { /* Undo everything if it failed*/ if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_IN_USE)) { /* NdisMDeregisterInterrupt(&pAd->Interrupt);*/ RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_IN_USE); } /* RTMPFreeAdapter(pAd); we will free it in disconnect()*/ } else if (pAd) { /* Microsoft HCT require driver send a disconnect event after driver initialization.*/ OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_MEDIA_STATE_CONNECTED); OPSTATUS_CLEAR_FLAG(pAd, fOP_AP_STATUS_MEDIA_STATE_CONNECTED); RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_MEDIA_STATE_CHANGE); DBGPRINT(RT_DEBUG_TRACE, ("NDIS_STATUS_MEDIA_DISCONNECT Event B!\n")); }/* end of else*/ /* Set up the Mac address*/ #ifdef CONFIG_STA_SUPPORT RtmpOSNetDevAddrSet(pAd->OpMode, pAd->net_dev, &pAd->CurrentAddress[0], (PUCHAR)(pAd->StaCfg.dev_name)); #endif /* CONFIG_STA_SUPPORT */ /* Various AP function init*/ #ifdef UAPSD_SUPPORT UAPSD_Init(pAd); #endif /* UAPSD_SUPPORT */ /* assign function pointers*/ #ifdef CONFIG_STA_SUPPORT IF_DEV_CONFIG_OPMODE_ON_STA(pAd) { #ifdef WPA_SUPPLICANT_SUPPORT #ifndef NATIVE_WPA_SUPPLICANT_SUPPORT /* send wireless event to wpa_supplicant for infroming interface up.*/ RtmpOSWrielessEventSend(pAd->net_dev, RT_WLAN_EVENT_CUSTOM, RT_INTERFACE_UP, NULL, NULL, 0); #endif /* NATIVE_WPA_SUPPLICANT_SUPPORT */ #endif /* WPA_SUPPLICANT_SUPPORT */ } #endif /* CONFIG_STA_SUPPORT */ /* auto-fall back settings */ #ifdef RANGE_EXTEND RTMP_IO_WRITE32(pAd, HT_FBK_CFG1, 0xedcba980); #endif // RANGE_EXTEND // #ifdef DOT11N_SS3_SUPPORT if (pAd->CommonCfg.TxStream >= 3) { RTMP_IO_WRITE32(pAd, TX_FBK_CFG_3S_0, 0x12111008); RTMP_IO_WRITE32(pAd, TX_FBK_CFG_3S_1, 0x16151413); } #endif /* DOT11N_SS3_SUPPORT */ #ifdef STREAM_MODE_SUPPORT RtmpStreamModeInit(pAd); #endif /* STREAM_MODE_SUPPORT */ #ifdef DOT11_N_SUPPORT #endif /* DOT11_N_SUPPORT */ #ifdef RT3290 if (IS_RT3290(pAd)) { WLAN_FUN_CTRL_STRUC WlanFunCtrl = {.word = 0}; RTMP_MAC_PWRSV_EN(pAd, TRUE, TRUE); // // Too much time for reading efuse(enter/exit L1), and our device will hang up // Enable L1 // RTMP_IO_READ32(pAd, WLAN_FUN_CTRL, &WlanFunCtrl.word); if (WlanFunCtrl.field.WLAN_EN == TRUE) { WlanFunCtrl.field.PCIE_APP0_CLK_REQ = FALSE; RTMP_IO_WRITE32(pAd, WLAN_FUN_CTRL, WlanFunCtrl.word); } } #endif /* RT3290 */ DBGPRINT_S(Status, ("<==== rt28xx_init, Status=%x\n", Status)); return TRUE; /*err7: APStop(pAd);*/ err6: #ifdef IGMP_SNOOP_SUPPORT MultiCastFilterTableReset(&pAd->pMulticastFilterTable); #endif /* IGMP_SNOOP_SUPPORT */ MeasureReqTabExit(pAd); TpcReqTabExit(pAd); err5: RtmpNetTaskExit(pAd); UserCfgExit(pAd); err4: MlmeHalt(pAd); RTMP_TimerListRelease(pAd); err3: RtmpMgmtTaskExit(pAd); #ifdef RTMP_TIMER_TASK_SUPPORT NdisFreeSpinLock(&pAd->TimerQLock); #endif /* RTMP_TIMER_TASK_SUPPORT */ err2: #ifdef RESOURCE_PRE_ALLOC RTMPResetTxRxRingMemory(pAd); #else RTMPFreeTxRxRingMemory(pAd); #endif /* RESOURCE_PRE_ALLOC */ err1: #ifdef RT3290 if (IS_RT3290(pAd)) RTMPEnableWlan(pAd, FALSE, FALSE); #endif /* RT3290 */ #ifdef DOT11_N_SUPPORT if(pAd->mpdu_blk_pool.mem) os_free_mem(pAd, pAd->mpdu_blk_pool.mem); /* free BA pool*/ #endif /* DOT11_N_SUPPORT */ /* shall not set priv to NULL here because the priv didn't been free yet.*/ /*net_dev->priv = 0;*/ #ifdef INF_AMAZON_SE err0: #endif /* INF_AMAZON_SE */ #ifdef ST err0: #endif /* ST */ DBGPRINT(RT_DEBUG_ERROR, ("!!! rt28xx Initialized fail !!!\n")); return FALSE; } VOID RTMPDrvOpen( IN VOID *pAdSrc) { PRTMP_ADAPTER pAd = (PRTMP_ADAPTER)pAdSrc; #ifdef CONFIG_STA_SUPPORT #endif /* CONFIG_STA_SUPPORT */ /* Enable Interrupt*/ RTMP_IRQ_ENABLE(pAd); /* Now Enable RxTx*/ RTMPEnableRxTx(pAd); RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_START_UP); { UINT32 reg = 0; RTMP_IO_READ32(pAd, 0x1300, ®); /* clear garbage interrupts*/ printk("0x1300 = %08x\n", reg); } { /* u32 reg;*/ /* UINT8 byte;*/ /* u16 tmp;*/ /* RTMP_IO_READ32(pAd, XIFS_TIME_CFG, ®);*/ /* tmp = 0x0805;*/ /* reg = (reg & 0xffff0000) | tmp;*/ /* RTMP_IO_WRITE32(pAd, XIFS_TIME_CFG, reg);*/ } #ifdef CONFIG_STA_SUPPORT #ifdef PCIE_PS_SUPPORT IF_DEV_CONFIG_OPMODE_ON_STA(pAd) RTMPInitPCIeLinkCtrlValue(pAd); #endif /* PCIE_PS_SUPPORT */ #endif /* CONFIG_STA_SUPPORT */ #ifdef CONFIG_STA_SUPPORT /* To reduce connection time, do auto reconnect here instead of waiting STAMlmePeriodicExec to do auto reconnect. */ if (pAd->OpMode == OPMODE_STA) MlmeAutoReconnectLastSSID(pAd); #endif /* CONFIG_STA_SUPPORT */ #ifdef CONFIG_STA_SUPPORT #endif /* CONFIG_STA_SUPPORT */ } VOID RTMPDrvClose( IN VOID *pAdSrc, IN VOID *net_dev) { PRTMP_ADAPTER pAd = (PRTMP_ADAPTER)pAdSrc; BOOLEAN Cancelled; UINT32 i = 0; Cancelled = FALSE; #ifdef CONFIG_STA_SUPPORT #ifdef CREDENTIAL_STORE if (pAd->IndicateMediaState == NdisMediaStateConnected) { StoreConnectInfo(pAd); } else { RTMP_SEM_LOCK(&pAd->StaCtIf.Lock); pAd->StaCtIf.Changeable = FALSE; RTMP_SEM_UNLOCK(&pAd->StaCtIf.Lock); } #endif /* CREDENTIAL_STORE */ #endif /* CONFIG_STA_SUPPORT */ #ifdef CONFIG_STA_SUPPORT IF_DEV_CONFIG_OPMODE_ON_STA(pAd) { #ifdef PCIE_PS_SUPPORT RTMPPCIeLinkCtrlValueRestore(pAd, RESTORE_CLOSE); #endif /* PCIE_PS_SUPPORT */ /* If dirver doesn't wake up firmware here,*/ /* NICLoadFirmware will hang forever when interface is up again.*/ if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE)) { AsicForceWakeup(pAd, TRUE); } #ifdef RTMP_MAC_PCI pAd->bPCIclkOff = FALSE; #endif /* RTMP_MAC_PCI */ } #endif /* CONFIG_STA_SUPPORT */ RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS); #ifdef EXT_BUILD_CHANNEL_LIST if (pAd->CommonCfg.pChDesp != NULL) os_free_mem(NULL, pAd->CommonCfg.pChDesp); pAd->CommonCfg.pChDesp = NULL; pAd->CommonCfg.DfsType = MAX_RD_REGION; pAd->CommonCfg.bCountryFlag = 0; #endif /* EXT_BUILD_CHANNEL_LIST */ #ifdef WDS_SUPPORT WdsDown(pAd); #endif /* WDS_SUPPORT */ for (i = 0 ; i < NUM_OF_TX_RING; i++) { while (pAd->DeQueueRunning[i] == TRUE) { DBGPRINT(RT_DEBUG_TRACE, ("Waiting for TxQueue[%d] done..........\n", i)); RTMPusecDelay(1000); } } /* Stop Mlme state machine*/ MlmeHalt(pAd); /* Close net tasklets*/ RtmpNetTaskExit(pAd); #ifdef CONFIG_STA_SUPPORT IF_DEV_CONFIG_OPMODE_ON_STA(pAd) { MacTableReset(pAd); #if defined(WOW_SUPPORT) && defined(RTMP_MAC_USB) && defined(WOW_IFDOWN_SUPPORT) if (pAd->WOW_Cfg.bEnable == TRUE) RT28xxUsbAsicWOWEnable(pAd); else #endif /* WOW_SUPPORT */ MlmeRadioOff(pAd); } #endif /* CONFIG_STA_SUPPORT */ MeasureReqTabExit(pAd); TpcReqTabExit(pAd); #ifdef LED_CONTROL_SUPPORT RTMPExitLEDMode(pAd); #endif // LED_CONTROL_SUPPORT /* Close kernel threads*/ RtmpMgmtTaskExit(pAd); #ifdef RTMP_MAC_PCI { if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_ACTIVE)) { RTMP_ASIC_INTERRUPT_DISABLE(pAd); } /* Receive packets to clear DMA index after disable interrupt. */ /*RTMPHandleRxDoneInterrupt(pAd);*/ /* put to radio off to save power when driver unload. After radiooff, can't write /read register. So need to finish all */ /* register access before Radio off.*/ #ifdef RTMP_PCI_SUPPORT if (pAd->infType == RTMP_DEV_INF_PCI || pAd->infType == RTMP_DEV_INF_PCIE) { BOOLEAN brc; brc=RT28xxPciAsicRadioOff(pAd, RTMP_HALT, 0); /*In solution 3 of 3090F, the bPCIclkOff will be set to TRUE after calling RT28xxPciAsicRadioOff*/ #ifdef PCIE_PS_SUPPORT pAd->bPCIclkOff = FALSE; #endif /* PCIE_PS_SUPPORT */ if (brc==FALSE) { DBGPRINT(RT_DEBUG_ERROR,("%s call RT28xxPciAsicRadioOff fail !!\n", __FUNCTION__)); } } #endif /* RTMP_PCI_SUPPORT */ } #endif /* RTMP_MAC_PCI */ /* Free IRQ*/ if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_IN_USE)) { #ifdef RTMP_MAC_PCI /* Deregister interrupt function*/ RTMP_OS_IRQ_RELEASE(pAd, net_dev); #endif /* RTMP_MAC_PCI */ RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_IN_USE); } /* Free Ring or USB buffers*/ #ifdef RESOURCE_PRE_ALLOC RTMPResetTxRxRingMemory(pAd); #else /* Free Ring or USB buffers*/ RTMPFreeTxRxRingMemory(pAd); #endif /* RESOURCE_PRE_ALLOC */ RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS); #ifdef DOT11_N_SUPPORT /* Free BA reorder resource*/ ba_reordering_resource_release(pAd); #endif /* DOT11_N_SUPPORT */ UserCfgExit(pAd); /* must after ba_reordering_resource_release */ #ifdef CONFIG_STA_SUPPORT #endif /* CONFIG_STA_SUPPORT */ RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_START_UP); /*+++Modify by woody to solve the bulk fail+++*/ #ifdef CONFIG_STA_SUPPORT IF_DEV_CONFIG_OPMODE_ON_STA(pAd) { } #endif /* CONFIG_STA_SUPPORT */ /* clear MAC table */ /* TODO: do not clear spin lock, such as fLastChangeAccordingMfbLock */ NdisZeroMemory(&pAd->MacTab, sizeof(MAC_TABLE)); /* release all timers */ RTMPusecDelay(2000); RTMP_TimerListRelease(pAd); #ifdef RTMP_TIMER_TASK_SUPPORT NdisFreeSpinLock(&pAd->TimerQLock); #endif /* RTMP_TIMER_TASK_SUPPORT */ } VOID RTMPInfClose( IN VOID *pAdSrc) { PRTMP_ADAPTER pAd = (PRTMP_ADAPTER)pAdSrc; #ifdef CONFIG_STA_SUPPORT IF_DEV_CONFIG_OPMODE_ON_STA(pAd) { #ifdef PROFILE_STORE WriteDatThread(pAd); RTMPusecDelay(1000); #endif /* PROFILE_STORE */ #ifdef QOS_DLS_SUPPORT /* send DLS-TEAR_DOWN message, */ if (pAd->CommonCfg.bDLSCapable) { UCHAR i; /* tear down local dls table entry*/ for (i=0; i<MAX_NUM_OF_INIT_DLS_ENTRY; i++) { if (pAd->StaCfg.DLSEntry[i].Valid && (pAd->StaCfg.DLSEntry[i].Status == DLS_FINISH)) { RTMPSendDLSTearDownFrame(pAd, pAd->StaCfg.DLSEntry[i].MacAddr); pAd->StaCfg.DLSEntry[i].Status = DLS_NONE; pAd->StaCfg.DLSEntry[i].Valid = FALSE; } } /* tear down peer dls table entry*/ for (i=MAX_NUM_OF_INIT_DLS_ENTRY; i<MAX_NUM_OF_DLS_ENTRY; i++) { if (pAd->StaCfg.DLSEntry[i].Valid && (pAd->StaCfg.DLSEntry[i].Status == DLS_FINISH)) { RTMPSendDLSTearDownFrame(pAd, pAd->StaCfg.DLSEntry[i].MacAddr); pAd->StaCfg.DLSEntry[i].Status = DLS_NONE; pAd->StaCfg.DLSEntry[i].Valid = FALSE; } } RTMP_MLME_HANDLER(pAd); } #endif /* QOS_DLS_SUPPORT */ if (INFRA_ON(pAd) && #if defined(WOW_SUPPORT) && defined(RTMP_MAC_USB) && defined(WOW_IFDOWN_SUPPORT) /* In WOW state, can't issue disassociation reqeust */ pAd->WOW_Cfg.bEnable == FALSE && #endif /* WOW_SUPPORT */ (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST))) { MLME_DISASSOC_REQ_STRUCT DisReq; MLME_QUEUE_ELEM *MsgElem;/* = (MLME_QUEUE_ELEM *) kmalloc(sizeof(MLME_QUEUE_ELEM), MEM_ALLOC_FLAG);*/ os_alloc_mem(NULL, (UCHAR **)&MsgElem, sizeof(MLME_QUEUE_ELEM)); if (MsgElem) { COPY_MAC_ADDR(DisReq.Addr, pAd->CommonCfg.Bssid); DisReq.Reason = REASON_DEAUTH_STA_LEAVING; MsgElem->Machine = ASSOC_STATE_MACHINE; MsgElem->MsgType = MT2_MLME_DISASSOC_REQ; MsgElem->MsgLen = sizeof(MLME_DISASSOC_REQ_STRUCT); NdisMoveMemory(MsgElem->Msg, &DisReq, sizeof(MLME_DISASSOC_REQ_STRUCT)); /* Prevent to connect AP again in STAMlmePeriodicExec*/ pAd->MlmeAux.AutoReconnectSsidLen= 32; NdisZeroMemory(pAd->MlmeAux.AutoReconnectSsid, pAd->MlmeAux.AutoReconnectSsidLen); pAd->Mlme.CntlMachine.CurrState = CNTL_WAIT_OID_DISASSOC; MlmeDisassocReqAction(pAd, MsgElem); /* kfree(MsgElem);*/ os_free_mem(NULL, MsgElem); } RTMPusecDelay(1000); } #ifdef WPA_SUPPLICANT_SUPPORT #ifndef NATIVE_WPA_SUPPLICANT_SUPPORT /* send wireless event to wpa_supplicant for infroming interface down.*/ RtmpOSWrielessEventSend(pAd->net_dev, RT_WLAN_EVENT_CUSTOM, RT_INTERFACE_DOWN, NULL, NULL, 0); #endif /* NATIVE_WPA_SUPPLICANT_SUPPORT */ if (pAd->StaCfg.pWpsProbeReqIe) { /* kfree(pAd->StaCfg.pWpsProbeReqIe);*/ os_free_mem(NULL, pAd->StaCfg.pWpsProbeReqIe); pAd->StaCfg.pWpsProbeReqIe = NULL; pAd->StaCfg.WpsProbeReqIeLen = 0; } if (pAd->StaCfg.pWpaAssocIe) { /* kfree(pAd->StaCfg.pWpaAssocIe);*/ os_free_mem(NULL, pAd->StaCfg.pWpaAssocIe); pAd->StaCfg.pWpaAssocIe = NULL; pAd->StaCfg.WpaAssocIeLen = 0; } #endif /* WPA_SUPPLICANT_SUPPORT */ } #endif /* CONFIG_STA_SUPPORT */ } PNET_DEV RtmpPhyNetDevMainCreate( IN VOID *pAdSrc) { PRTMP_ADAPTER pAd = (PRTMP_ADAPTER)pAdSrc; PNET_DEV pDevNew; UINT32 MC_RowID = 0, IoctlIF = 0; pAd = pAd; #ifdef MULTIPLE_CARD_SUPPORT MC_RowID = pAd->MC_RowID; #endif /* MULTIPLE_CARD_SUPPORT */ #ifdef HOSTAPD_SUPPORT IoctlIF = pAd->IoctlIF; #endif /* HOSTAPD_SUPPORT */ pDevNew = RtmpOSNetDevCreate((INT32)MC_RowID, (UINT32 *)&IoctlIF, INT_MAIN, 0, sizeof(PRTMP_ADAPTER), INF_MAIN_DEV_NAME); #ifdef HOSTAPD_SUPPORT pAd->IoctlIF = IoctlIF; #endif /* HOSTAPD_SUPPORT */ return pDevNew; }
VOID RT35xx_ChipBBPAdjust( IN RTMP_ADAPTER *pAd) { UINT32 Value; UCHAR byteValue = 0; #ifdef DOT11_N_SUPPORT if ((pAd->CommonCfg.HtCapability.HtCapInfo.ChannelWidth == BW_40) && (pAd->CommonCfg.RegTransmitSetting.field.EXTCHA == EXTCHA_ABOVE)) { pAd->CommonCfg.BBPCurrentBW = BW_40; pAd->CommonCfg.CentralChannel = pAd->CommonCfg.Channel + 2; /* TX : control channel at lower */ RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value); Value &= (~0x1); RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value); /* RX : control channel at lower */ RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &byteValue); byteValue &= (~0x20); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, byteValue); RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &byteValue); byteValue &= (~0x18); byteValue |= 0x10; RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, byteValue); if (pAd->CommonCfg.Channel > 14) { /* request by Gary 20070208 for middle and long range A Band*/ if (IS_RT3572(pAd) || IS_RT3593(pAd)) RT3572WriteBBPR66(pAd, 0x48); } else { /* request by Gary 20070208 for middle and long range G Band*/ if (IS_RT3572(pAd) || IS_RT3593(pAd)) RT3572WriteBBPR66(pAd, 0x38); } /* */ if (pAd->MACVersion == 0x28600100) { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x1A); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, 0x0A); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x16); } else { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x12); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, 0x0A); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x10); } DBGPRINT(RT_DEBUG_TRACE, ("ApStartUp : ExtAbove, ChannelWidth=%d, Channel=%d, ExtChanOffset=%d(%d) \n", pAd->CommonCfg.HtCapability.HtCapInfo.ChannelWidth, pAd->CommonCfg.Channel, pAd->CommonCfg.RegTransmitSetting.field.EXTCHA, pAd->CommonCfg.AddHTInfo.AddHtInfo.ExtChanOffset)); } else if ((pAd->CommonCfg.Channel > 2) && (pAd->CommonCfg.HtCapability.HtCapInfo.ChannelWidth == BW_40) && (pAd->CommonCfg.RegTransmitSetting.field.EXTCHA == EXTCHA_BELOW)) { pAd->CommonCfg.BBPCurrentBW = BW_40; if (pAd->CommonCfg.Channel == 14) pAd->CommonCfg.CentralChannel = pAd->CommonCfg.Channel - 1; else pAd->CommonCfg.CentralChannel = pAd->CommonCfg.Channel - 2; /* TX : control channel at upper */ RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value); Value |= (0x1); RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value); /* RX : control channel at upper */ RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &byteValue); byteValue |= (0x20); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, byteValue); RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &byteValue); byteValue &= (~0x18); byteValue |= 0x10; RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, byteValue); if (pAd->CommonCfg.Channel > 14) { /* request by Gary 20070208 for middle and long range A Band*/ if (IS_RT3572(pAd) || IS_RT3593(pAd)) RT3572WriteBBPR66(pAd, 0x48); } else { /* request by Gary 20070208 for middle and long range G band*/ if (IS_RT3572(pAd) || IS_RT3593(pAd)) RT3572WriteBBPR66(pAd, 0x38); } if (pAd->MACVersion == 0x28600100) { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x1A); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, 0x0A); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x16); } else { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x12); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, 0x0A); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x10); } DBGPRINT(RT_DEBUG_TRACE, ("ApStartUp : ExtBlow, ChannelWidth=%d, Channel=%d, ExtChanOffset=%d(%d) \n", pAd->CommonCfg.HtCapability.HtCapInfo.ChannelWidth, pAd->CommonCfg.Channel, pAd->CommonCfg.RegTransmitSetting.field.EXTCHA, pAd->CommonCfg.AddHTInfo.AddHtInfo.ExtChanOffset)); } else #endif /* DOT11_N_SUPPORT */ { pAd->CommonCfg.BBPCurrentBW = BW_20; pAd->CommonCfg.CentralChannel = pAd->CommonCfg.Channel; /* TX : control channel at lower */ RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value); Value &= (~0x1); RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value); RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &byteValue); byteValue &= (~0x18); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, byteValue); /* 20 MHz bandwidth*/ if (pAd->CommonCfg.Channel > 14) { /* request by Gary 20070208*/ if (IS_RT3572(pAd) || IS_RT3593(pAd)) RT3572WriteBBPR66(pAd, 0x40); } else { /* request by Gary 20070208*/ /*RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, 0x30);*/ /* request by Brian 20070306*/ if (IS_RT3572(pAd) || IS_RT3593(pAd)) RT3572WriteBBPR66(pAd, 0x38); } if (pAd->MACVersion == 0x28600100) { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x16); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, 0x08); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x11); } else { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x12); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, 0x0a); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x10); } #ifdef DOT11_N_SUPPORT DBGPRINT(RT_DEBUG_TRACE, ("ApStartUp : 20MHz, ChannelWidth=%d, Channel=%d, ExtChanOffset=%d(%d) \n", pAd->CommonCfg.HtCapability.HtCapInfo.ChannelWidth, pAd->CommonCfg.Channel, pAd->CommonCfg.RegTransmitSetting.field.EXTCHA, pAd->CommonCfg.AddHTInfo.AddHtInfo.ExtChanOffset)); #endif /* DOT11_N_SUPPORT */ } if (pAd->CommonCfg.Channel > 14) { /* request by Gary 20070208 for middle and long range A Band*/ RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, 0x1D); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, 0x1D); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, 0x1D); /*RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0x1D);*/ } else { /* request by Gary 20070208 for middle and long range G band*/ RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, 0x2D); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, 0x2D); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, 0x2D); /*RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0x2D);*/ } }
/* ======================================================================== Routine Description: Periodic evaluate antenna link status Arguments: pAd - Adapter pointer Return Value: None ======================================================================== */ VOID APAsicEvaluateRxAnt( IN PRTMP_ADAPTER pAd) { UCHAR BBPR3 = 0; ULONG TxTotalCnt; #ifdef RALINK_ATE if (ATE_ON(pAd)) return; #endif /* RALINK_ATE */ #ifdef CARRIER_DETECTION_SUPPORT if(pAd->CommonCfg.CarrierDetect.CD_State == CD_SILENCE) return; #endif /* CARRIER_DETECTION_SUPPORT */ #ifdef TXBF_SUPPORT /* TODO: we didn't do RxAnt evaluate for 3x3 chips */ if (IS_RT3883(pAd) || IS_RT2883(pAd) || IS_RT3593(pAd)) return; #endif /* TXBF_SUPPORT */ RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BBPR3); BBPR3 &= (~0x18); if(pAd->Antenna.field.RxPath == 3 #ifdef DOT11_N_SUPPORT #ifdef GREENAP_SUPPORT && pAd->ApCfg.bGreenAPActive == FALSE #endif /* GREENAP_SUPPORT */ #endif /* DOT11_N_SUPPORT */ ) { BBPR3 |= (0x10); } else if(pAd->Antenna.field.RxPath == 2 #ifdef DOT11_N_SUPPORT #ifdef GREENAP_SUPPORT && pAd->ApCfg.bGreenAPActive == FALSE #endif /* GREENAP_SUPPORT */ #endif /* DOT11_N_SUPPORT */ ) { BBPR3 |= (0x8); } else if(pAd->Antenna.field.RxPath == 1) { BBPR3 |= (0x0); } RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BBPR3); TxTotalCnt = pAd->RalinkCounters.OneSecTxNoRetryOkCount + pAd->RalinkCounters.OneSecTxRetryOkCount + pAd->RalinkCounters.OneSecTxFailCount; if (TxTotalCnt > 50) { RTMPSetTimer(&pAd->Mlme.RxAntEvalTimer, 20); pAd->Mlme.bLowThroughput = FALSE; } else { RTMPSetTimer(&pAd->Mlme.RxAntEvalTimer, 300); pAd->Mlme.bLowThroughput = TRUE; } }