t_stat ptp_wr (int32 data, int32 PA, int32 access); t_stat ptp_svc (UNIT *uptr); t_stat ptp_reset (DEVICE *dptr); t_stat ptp_attach (UNIT *uptr, char *ptr); t_stat ptp_detach (UNIT *uptr); /* PTR data structures ptr_dev PTR device descriptor ptr_unit PTR unit descriptor ptr_reg PTR register list */ DIB ptr_dib = { IOBA_PTR, IOLN_PTR, &ptr_rd, &ptr_wr, 1, IVCL (PTR), VEC_PTR, { NULL } }; UNIT ptr_unit = { UDATA (&ptr_svc, UNIT_SEQ+UNIT_ATTABLE+UNIT_ROABLE, 0), SERIAL_IN_WAIT }; REG ptr_reg[] = { { GRDATA (BUF, ptr_unit.buf, DEV_RDX, 8, 0) }, { GRDATA (CSR, ptr_csr, DEV_RDX, 16, 0) }, { FLDATA (INT, int_req, INT_V_PTR) }, { FLDATA (ERR, ptr_csr, CSR_V_ERR) }, { FLDATA (BUSY, ptr_csr, CSR_V_BUSY) }, { FLDATA (DONE, ptr_csr, CSR_V_DONE) }, { FLDATA (IE, ptr_csr, CSR_V_IE) },
int32 ts_updxs0 (int32 t); void ts_cmpendcmd (int32 s0, int32 s1); void ts_endcmd (int32 ssf, int32 xs0f, int32 msg); int32 ts_map_status (t_stat st); /* TS data structures ts_dev TS device descriptor ts_unit TS unit list ts_reg TS register list ts_mod TS modifier list */ DIB ts_dib = { IOBA_TS, IOLN_TS, &ts_rd, &ts_wr, 1, IVCL (TS), VEC_TS, { NULL } }; UNIT ts_unit = { UDATA (&ts_svc, UNIT_ATTABLE + UNIT_ROABLE + UNIT_DISABLE, 0) }; REG ts_reg[] = { { GRDATA (TSSR, tssr, DEV_RDX, 16, 0) }, { GRDATA (TSBA, tsba, DEV_RDX, 22, 0) }, { GRDATA (TSDBX, tsdbx, DEV_RDX, 8, 0) }, { GRDATA (CHDR, cmdhdr, DEV_RDX, 16, 0) }, { GRDATA (CADL, cmdadl, DEV_RDX, 16, 0) }, { GRDATA (CADH, cmdadh, DEV_RDX, 16, 0) }, { GRDATA (CLNT, cmdlnt, DEV_RDX, 16, 0) }, { GRDATA (MHDR, msghdr, DEV_RDX, 16, 0) }, { GRDATA (MRFC, msgrfc, DEV_RDX, 16, 0) }, { GRDATA (MXS0, msgxs0, DEV_RDX, 16, 0) },
t_stat clk_svc (UNIT *uptr); int32 clk_inta (void); t_stat clk_reset (DEVICE *dptr); t_stat clk_set_freq (UNIT *uptr, int32 val, char *cptr, void *desc); t_stat clk_show_freq (FILE *st, UNIT *uptr, int32 val, void *desc); /* TTI data structures tti_dev TTI device descriptor tti_unit TTI unit descriptor tti_reg TTI register list */ DIB tti_dib = { IOBA_TTI, IOLN_TTI, &tti_rd, &tti_wr, 1, IVCL (TTI), VEC_TTI, { NULL } }; UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE, 0), SERIAL_IN_WAIT }; REG tti_reg[] = { { HRDATAD (BUF, tti_unit.buf, 8, "last data item processed") }, { HRDATAD (CSR, tti_csr, 16, "control/status register") }, { FLDATAD (INT, IREQ (TTI), INT_V_TTI, "interrupt pending flag") }, { FLDATAD (DONE, tti_csr, CSR_V_DONE, "device done flag (CSR<7>)") }, { FLDATAD (ERR, tti_csr, CSR_V_ERR, "device error flag (CSR<15>)") }, { FLDATAD (IE, tti_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") }, { DRDATAD (POS, tti_unit.pos, T_ADDR_W, "number of characters input"), PV_LEFT }, { DRDATAD (TIME, tti_unit.wait, 24, "input polling interval"), PV_LEFT }, { NULL } };
const char *ptp_description (DEVICE *dptr); t_stat ptp_attach (UNIT *uptr, CONST char *ptr); t_stat ptp_detach (UNIT *uptr); /* PTR data structures ptr_dev PTR device descriptor ptr_unit PTR unit descriptor ptr_reg PTR register list */ #define IOLN_PTR 004 DIB ptr_dib = { IOBA_AUTO, IOLN_PTR, &ptr_rd, &ptr_wr, 1, IVCL (PTR), VEC_AUTO, { NULL } }; UNIT ptr_unit = { UDATA (&ptr_svc, UNIT_SEQ+UNIT_ATTABLE+UNIT_ROABLE, 0), SERIAL_IN_WAIT }; extern DEVICE ptr_dev; REG ptr_reg[] = { { GRDATAD (BUF, ptr_unit.buf, DEV_RDX, 8, 0, "last data item processed") }, { GRDATAD (CSR, ptr_csr, DEV_RDX, 16, 0, "control/status register") }, { FLDATAD (INT, int_req, INT_V_PTR, "interrupt pending flag") }, { FLDATAD (ERR, ptr_csr, CSR_V_ERR, "error flag (CSR<15>)") }, { FLDATAD (BUSY, ptr_csr, CSR_V_BUSY, "busy flag (CSR<11>)") }, { FLDATAD (DONE, ptr_csr, CSR_V_DONE, "device done flag (CSR<7>)") },
t_stat ts_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr); char *ts_description (DEVICE *dptr); /* TS data structures ts_dev TS device descriptor ts_unit TS unit list ts_reg TS register list ts_mod TS modifier list */ #define IOLN_TS 004 DIB ts_dib = { IOBA_AUTO, IOLN_TS, &ts_rd, &ts_wr, 1, IVCL (TS), VEC_AUTO, { NULL } }; UNIT ts_unit = { UDATA (&ts_svc, UNIT_ATTABLE + UNIT_ROABLE + UNIT_DISABLE, 0) }; REG ts_reg[] = { { GRDATAD (TSSR, tssr, DEV_RDX, 16, 0, "status register") }, { GRDATAD (TSBA, tsba, DEV_RDX, 22, 0, "bus address register") }, { GRDATAD (TSDBX, tsdbx, DEV_RDX, 8, 0, "data buffer extension register") }, { GRDATAD (CHDR, cmdhdr, DEV_RDX, 16, 0, "command packet header") }, { GRDATAD (CADL, cmdadl, DEV_RDX, 16, 0, "command packet low address or count") }, { GRDATAD (CADH, cmdadh, DEV_RDX, 16, 0, "command packet high address") }, { GRDATAD (CLNT, cmdlnt, DEV_RDX, 16, 0, "command packet length") }, { GRDATAD (MHDR, msghdr, DEV_RDX, 16, 0, "message packet header") }, { GRDATAD (MRFC, msgrfc, DEV_RDX, 16, 0, "message packet residual frame count") }, { GRDATAD (MXS0, msgxs0, DEV_RDX, 16, 0, "message packet extended status 0") },
t_stat lpt_wr(int32 data, int32 PA, int32 access); t_stat lpt_svc(UNIT * uptr); t_stat lpt_reset(DEVICE * dptr); t_stat lpt_attach(UNIT * uptr, char *ptr); t_stat lpt_detach(UNIT * uptr); /* LPT data structures lpt_dev LPT device descriptor lpt_unit LPT unit descriptor lpt_reg LPT register list */ DIB lpt_dib = { IOBA_LPT, IOLN_LPT, &lpt_rd, &lpt_wr, 1, IVCL(LPT), VEC_LPT, {NULL} }; UNIT lpt_unit = { UDATA(&lpt_svc, UNIT_SEQ + UNIT_ATTABLE + UNIT_TEXT, 0), SERIAL_OUT_WAIT }; REG lpt_reg[] = { {GRDATA(BUF, lpt_unit.buf, DEV_RDX, 8, 0)}, {GRDATA(CSR, lpt_csr, DEV_RDX, 16, 0)}, {FLDATA(INT, IREQ(LPT), INT_V_LPT)}, {FLDATA(ERR, lpt_csr, CSR_V_ERR)}, {FLDATA(DONE, lpt_csr, CSR_V_DONE)}, {FLDATA(IE, lpt_csr, CSR_V_IE)}, {DRDATA(POS, lpt_unit.pos, T_ADDR_W), PV_LEFT}, {DRDATA(TIME, lpt_unit.wait, 24), PV_LEFT},
t_stat clk_reset (DEVICE *dptr); t_stat clk_attach (UNIT *uptr, char *cptr); t_stat clk_detach (UNIT *uptr); t_stat todr_resync (void); extern int32 sysd_hlt_enb (void); extern int32 fault_PC; /* TTI data structures tti_dev TTI device descriptor tti_unit TTI unit descriptor tti_reg TTI register list */ DIB tti_dib = { 0, 0, NULL, NULL, 1, IVCL (TTI), SCB_TTI, { NULL } }; UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), 0 }; REG tti_reg[] = { { HRDATA (BUF, tti_unit.buf, 16) }, { HRDATA (CSR, tti_csr, 16) }, { FLDATA (INT, int_req[IPL_TTI], INT_V_TTI) }, { FLDATA (DONE, tti_csr, CSR_V_DONE) }, { FLDATA (IE, tti_csr, CSR_V_IE) }, { DRDATA (POS, tti_unit.pos, T_ADDR_W), PV_LEFT }, { DRDATA (TIME, tti_unit.wait, 24), PV_LEFT }, { NULL } }; MTAB tti_mod[] = {
int32 dli_iack (void); void dlo_clr_int (int32 ln); void dlo_set_int (int32 ln); int32 dlo_iack (void); void dlx_reset_ln (int32 ln); /* DLI data structures dli_dev DLI device descriptor dli_unit DLI unit descriptor dli_reg DLI register list */ DIB dli_dib = { IOBA_DL, IOLN_DL, &dlx_rd, &dlx_wr, 2, IVCL (DLI), VEC_DLI, { &dli_iack, &dlo_iack } }; UNIT dli_unit = { UDATA (&dli_svc, 0, 0), KBD_POLL_WAIT }; REG dli_reg[] = { { BRDATA (BUF, dli_buf, DEV_RDX, 16, DLX_LINES) }, { BRDATA (CSR, dli_csr, DEV_RDX, 16, DLX_LINES) }, { GRDATA (IREQ, dli_ireq[DLI_RCI], DEV_RDX, DLX_LINES, 0) }, { GRDATA (DSI, dli_ireq[DLI_DSI], DEV_RDX, DLX_LINES, 0) }, { DRDATA (LINES, dlx_desc.lines, 6), REG_HRO }, { GRDATA (DEVADDR, dli_dib.ba, DEV_RDX, 32, 0), REG_HRO }, { GRDATA (DEVIOLN, dli_dib.lnt, DEV_RDX, 32, 0), REG_HRO }, { GRDATA (DEVVEC, dli_dib.vec, DEV_RDX, 16, 0), REG_HRO }, { NULL } };
void dz_set_txint(int32 dz); t_stat dz_setnl(UNIT * uptr, int32 val, char *cptr, void *desc); t_stat dz_set_log(UNIT * uptr, int32 val, char *cptr, void *desc); t_stat dz_set_nolog(UNIT * uptr, int32 val, char *cptr, void *desc); t_stat dz_show_log(FILE * st, UNIT * uptr, int32 val, void *desc); /* DZ data structures dz_dev DZ device descriptor dz_unit DZ unit list dz_reg DZ register list */ DIB dz_dib = { IOBA_DZ, IOLN_DZ * DZ_MUXES, &dz_rd, &dz_wr, 2, IVCL(DZRX), VEC_DZRX, {&dz_rxinta, &dz_txinta} }; UNIT dz_unit = { UDATA(&dz_svc, UNIT_IDLE | UNIT_ATTABLE | DZ_8B_DFLT, 0) }; REG dz_reg[] = { {BRDATA(CSR, dz_csr, DEV_RDX, 16, DZ_MUXES)}, {BRDATA(RBUF, dz_rbuf, DEV_RDX, 16, DZ_MUXES)}, {BRDATA(LPR, dz_lpr, DEV_RDX, 16, DZ_MUXES)}, {BRDATA(TCR, dz_tcr, DEV_RDX, 16, DZ_MUXES)}, {BRDATA(MSR, dz_msr, DEV_RDX, 16, DZ_MUXES)}, {BRDATA(TDR, dz_tdr, DEV_RDX, 16, DZ_MUXES)}, {BRDATA(SAENB, dz_sae, DEV_RDX, 1, DZ_MUXES)}, {GRDATA(RXINT, dz_rxi, DEV_RDX, DZ_MUXES, 0)}, {GRDATA(TXINT, dz_txi, DEV_RDX, DZ_MUXES, 0)}, {FLDATA(MDMCTL, dz_mctl, 0)},
t_stat ng_rd(int32 *data, int32 PA, int32 access); t_stat ng_wr(int32 data, int32 PA, int32 access); t_stat ng_svc(UNIT *uptr); t_stat ng_reset(DEVICE *dptr); t_stat ng_boot(int32 unit, DEVICE *dptr); t_stat ng_set_type(UNIT *uptr, int32 val, CONST char *cptr, void *desc); t_stat ng_show_type(FILE *st, UNIT *uptr, int32 val, CONST void *desc); t_stat ng_set_scale(UNIT *uptr, int32 val, CONST char *cptr, void *desc); t_stat ng_show_scale(FILE *st, UNIT *uptr, int32 val, CONST void *desc); t_stat ng_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr); const char *ng_description (DEVICE *dptr); #define IOLN_NG 4 DIB ng_dib = { IOBA_AUTO, IOLN_NG, &ng_rd, &ng_wr, 4, IVCL(NG), VEC_AUTO, {NULL}, IOLN_NG }; UNIT ng_unit = { UDATA (&ng_svc, 0, 0), NG_DELAY }; REG ng_reg[] = { { DRDATAD (CYCLE, ng_unit.wait, 24, "NG cycle"), REG_NZ + PV_LEFT }, { GRDATAD(TYPE, ng_type, 16, 16, 0, "Hardware type"), REG_FIT}, { GRDATAD(SCALE, ng_scale, 16, 16, 0, "Hardware type"), REG_FIT}, { NULL } }; MTAB ng_mod[] = { { MTAB_XTD|MTAB_VDV|MTAB_VALR, 0, "TYPE", "TYPE={DAZZLE|LOGO}",
t_stat rx_svc(UNIT * uptr); t_stat rx_reset(DEVICE * dptr); t_stat rx_boot(int32 unitno, DEVICE * dptr); void rx_done(int32 esr_flags, int32 new_ecode); /* RX11 data structures rx_dev RX device descriptor rx_unit RX unit list rx_reg RX register list rx_mod RX modifier list */ DIB rx_dib = { IOBA_RX, IOLN_RX, &rx_rd, &rx_wr, 1, IVCL(RX), VEC_RX, {NULL} }; UNIT rx_unit[] = { {UDATA(&rx_svc, UNIT_FIX + UNIT_ATTABLE + UNIT_BUFABLE + UNIT_MUSTBUF, RX_SIZE)}, {UDATA(&rx_svc, UNIT_FIX + UNIT_ATTABLE + UNIT_BUFABLE + UNIT_MUSTBUF, RX_SIZE)} }; REG rx_reg[] = { {ORDATA(RXCS, rx_csr, 16)}, {ORDATA(RXDB, rx_dbr, 8)}, {ORDATA(RXES, rx_esr, 8)}, {ORDATA(RXERR, rx_ecode, 8)}, {ORDATA(RXTA, rx_track, 8)},
int32 dci_iack (void); void dco_clr_int (int32 ln); void dco_set_int (int32 ln); int32 dco_iack (void); void dcx_reset_ln (int32 ln); /* DCI data structures dci_dev DCI device descriptor dci_unit DCI unit descriptor dci_reg DCI register list */ DIB dci_dib = { IOBA_DC, IOLN_DC, &dcx_rd, &dcx_wr, 2, IVCL (DCI), VEC_DCI, { &dci_iack, &dco_iack } }; UNIT dci_unit = { UDATA (&dci_svc, 0, 0), KBD_POLL_WAIT }; REG dci_reg[] = { { BRDATA (BUF, dci_buf, DEV_RDX, 8, DCX_LINES) }, { BRDATA (CSR, dci_csr, DEV_RDX, 16, DCX_LINES) }, { GRDATA (IREQ, dci_ireq, DEV_RDX, DCX_LINES, 0) }, { DRDATA (LINES, dcx_desc.lines, 6), REG_HRO }, { GRDATA (DEVADDR, dci_dib.ba, DEV_RDX, 32, 0), REG_HRO }, { GRDATA (DEVIOLN, dci_dib.lnt, DEV_RDX, 32, 0), REG_HRO }, { GRDATA (DEVVEC, dci_dib.vec, DEV_RDX, 16, 0), REG_HRO }, { NULL } };
t_stat rx_boot (int32 unitno, DEVICE *dptr); void rx_done (int32 esr_flags, int32 new_ecode); /* RX11 data structures rx_dev RX device descriptor rx_unit RX unit list rx_reg RX register list rx_mod RX modifier list */ #define IOLN_RX 004 DIB rx_dib = { IOBA_AUTO, IOLN_RX, &rx_rd, &rx_wr, 1, IVCL (RX), VEC_AUTO, { NULL }, IOLN_RX, }; UNIT rx_unit[] = { { UDATA (&rx_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+UNIT_MUSTBUF, RX_SIZE) }, { UDATA (&rx_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+UNIT_MUSTBUF, RX_SIZE) } }; REG rx_reg[] = { { ORDATA (RXCS, rx_csr, 16) }, { ORDATA (RXDB, rx_dbr, 8) }, { ORDATA (RXES, rx_esr, 8) }, { ORDATA (RXERR, rx_ecode, 8) }, { ORDATA (RXTA, rx_track, 8) },
int32 dlo_iack (void); void dlx_reset_ln (int32 ln); const char *dlx_description (DEVICE *dptr); /* DLI data structures dli_dev DLI device descriptor dli_unit DLI unit descriptor dli_reg DLI register list */ #define IOLN_DL 010 DIB dli_dib = { IOBA_AUTO, IOLN_DL * DLX_LINES, &dlx_rd, &dlx_wr, 2, IVCL (DLI), VEC_AUTO, { &dli_iack, &dlo_iack }, IOLN_DL, }; UNIT dli_unit = { UDATA (&dli_svc, 0, 0), TMLN_SPD_9600_BPS }; REG dli_reg[] = { { BRDATA (BUF, dli_buf, DEV_RDX, 16, DLX_LINES) }, { BRDATA (CSR, dli_csr, DEV_RDX, 16, DLX_LINES) }, { DRDATAD (TIME, dli_unit.wait, 24, "input polling interval"), PV_LEFT }, { GRDATA (IREQ, dli_ireq[DLI_RCI], DEV_RDX, DLX_LINES, 0) }, { GRDATA (DSI, dli_ireq[DLI_DSI], DEV_RDX, DLX_LINES, 0) }, { DRDATA (LINES, dlx_desc.lines, 6), REG_HRO }, { GRDATA (DEVADDR, dli_dib.ba, DEV_RDX, 32, 0), REG_HRO }, { GRDATA (DEVIOLN, dli_dib.lnt, DEV_RDX, 32, 0), REG_HRO }, { GRDATA (DEVVEC, dli_dib.vec, DEV_RDX, 16, 0), REG_HRO }, { NULL }
t_stat pclk_wr (int32 data, int32 PA, int32 access); t_stat pclk_svc (UNIT *uptr); t_stat pclk_reset (DEVICE *dptr); t_stat pclk_set_line (UNIT *uptr, int32 val, char *cptr, void *desc); void pclk_tick (void); /* PCLK data structures pclk_dev PCLK device descriptor pclk_unit PCLK unit descriptor pclk_reg PCLK register list */ DIB pclk_dib = { IOBA_PCLK, IOLN_PCLK, &pclk_rd, &pclk_wr, 1, IVCL (PCLK), VEC_PCLK, { NULL } }; UNIT pclk_unit = { UDATA (&pclk_svc, UNIT_IDLE, 0) }; REG pclk_reg[] = { { ORDATA (CSR, pclk_csr, 16) }, { ORDATA (CSB, pclk_csb, 16) }, { ORDATA (CNT, pclk_ctr, 16) }, { FLDATA (INT, IREQ (PCLK), INT_V_PCLK) }, { FLDATA (OVFL, pclk_csr, CSR_V_ERR) }, { FLDATA (DONE, pclk_csr, CSR_V_DONE) }, { FLDATA (IE, pclk_csr, CSR_V_IE) }, { FLDATA (UPDN, pclk_csr, CSR_V_UPDN) }, { FLDATA (MODE, pclk_csr, CSR_V_MODE) }, { FLDATA (RUN, pclk_csr, CSR_V_GO) },
t_stat vt_set_vspace(UNIT *uptr, int32 val, char *cptr, void *desc); t_stat vt_show_vspace(FILE *st, UNIT *uptr, int32 val, void *desc); t_stat vt_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr); const char *vt_description (DEVICE *dptr); /* VT11/VS60 data structures vt_dev VT11 device descriptor vt_unit VT11 unit descriptor vt_reg VT11 register list vt_mod VT11 modifier list */ #define IOLN_VT11 010 /* VT11 */ #define IOLN_VS60 040 /* VS60 */ DIB vt_dib = { IOBA_AUTO, IOLN_VT11, &vt_rd, &vt_wr, 4, IVCL(VTST), VEC_AUTO, {NULL} }; /* (VT11 uses only the first 3 interrupt vectors) */ UNIT vt_unit = { UDATA (&vt_svc, UNIT_SEQ, 0), VT11_DELAY}; REG vt_reg[] = { { GRDATA (DEVADDR, vt_dib.ba, DEV_RDX, 32, 0), REG_HRO }, { GRDATA (DEVVEC, vt_dib.vec, DEV_RDX, 16, 0), REG_HRO }, { NULL } }; MTAB vt_mod[] = { { MTAB_XTD|MTAB_VDV|MTAB_VALR, 0, "CRT", "CRT={VR14|VR17|VR48}", &vt_set_crt, &vt_show_crt, NULL, "CRT Type" }, { MTAB_XTD|MTAB_VDV|MTAB_VALR, 0, "SCALE", "SCALE={1|2|4|8}", &vt_set_scale, &vt_show_scale, NULL, "Pixel Scale Factor" },
t_stat ry_boot (int32 unitno, DEVICE *dptr); void ry_done (int esr_flags, int new_ecode); t_stat ry_set_size (UNIT *uptr, int32 val, char *cptr, void *desc); t_stat ry_attach (UNIT *uptr, char *cptr); /* RY11 data structures ry_dev RY device descriptor ry_unit RY unit list ry_reg RY register list ry_mod RY modifier list */ DIB ry_dib = { IOBA_RY, IOLN_RY, &ry_rd, &ry_wr, 1, IVCL (RY), VEC_RY, { NULL } }; UNIT ry_unit[] = { { UDATA (&ry_svc, UNIT_DEN+UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+UNIT_MUSTBUF, RY_SIZE) }, { UDATA (&ry_svc, UNIT_DEN+UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+UNIT_MUSTBUF, RY_SIZE) } }; REG ry_reg[] = { { GRDATA (RYCS, ry_csr, DEV_RDX, 16, 0) }, { GRDATA (RYBA, ry_ba, DEV_RDX, 16, 0) }, { GRDATA (RYWC, ry_wc, DEV_RDX, 8, 0) }, { GRDATA (RYDB, ry_dbr, DEV_RDX, 16, 0) }, { GRDATA (RYES, ry_esr, DEV_RDX, 12, 0) },
void dcx_reset_ln (int32 ln); t_stat dcx_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr); const char *dcx_description (DEVICE *dptr); /* DCI data structures dci_dev DCI device descriptor dci_unit DCI unit descriptor dci_reg DCI register list */ #define IOLN_DC 010 DIB dci_dib = { IOBA_AUTO, IOLN_DC * DCX_LINES, &dcx_rd, &dcx_wr, 2, IVCL (DCI), VEC_AUTO, { &dci_iack, &dco_iack }, IOLN_DC, }; UNIT dci_unit = { UDATA (&dci_svc, 0, 0), TMLN_SPD_9600_BPS }; REG dci_reg[] = { { BRDATAD (BUF, dci_buf, DEV_RDX, 8, DCX_LINES, "input control/stats register") }, { BRDATAD (CSR, dci_csr, DEV_RDX, 16, DCX_LINES, "input buffer") }, { GRDATAD (IREQ, dci_ireq, DEV_RDX, DCX_LINES, 0, "interrupt requests") }, { DRDATAD (TIME, dci_unit.wait, 24, "input polling interval"), PV_LEFT }, { DRDATA (LINES, dcx_desc.lines, 6), REG_HRO }, { GRDATA (DEVADDR, dci_dib.ba, DEV_RDX, 32, 0), REG_HRO }, { GRDATA (DEVIOLN, dci_dib.lnt, DEV_RDX, 32, 0), REG_HRO }, { GRDATA (DEVVEC, dci_dib.vec, DEV_RDX, 16, 0), REG_HRO }, { NULL } };