/****************************************************************************** * Shift data bits in from the EEPROM * * hw - Struct containing variables accessed by shared code *****************************************************************************/ static u16 ixgb_shift_in_bits(struct ixgb_hw *hw) { u32 eecd_reg; u32 i; u16 data; /* In order to read a register from the EEPROM, we need to shift 16 bits * in from the EEPROM. Bits are "shifted in" by raising the clock input to * the EEPROM (setting the SK bit), and then reading the value of the "DO" * bit. During this "shifting in" process the "DI" bit should always be * clear.. */ eecd_reg = IXGB_READ_REG(hw, EECD); eecd_reg &= ~(IXGB_EECD_DO | IXGB_EECD_DI); data = 0; for (i = 0; i < 16; i++) { data = data << 1; ixgb_raise_clock(hw, &eecd_reg); eecd_reg = IXGB_READ_REG(hw, EECD); eecd_reg &= ~(IXGB_EECD_DI); if (eecd_reg & IXGB_EECD_DO) data |= 1; ixgb_lower_clock(hw, &eecd_reg); } return data; }
/****************************************************************************** * Reset the transmit and receive units; mask and clear all interrupts. * * hw - Struct containing variables accessed by shared code *****************************************************************************/ bool ixgb_adapter_stop(struct ixgb_hw *hw) { u32 ctrl_reg; u32 icr_reg; ENTER(); /* If we are stopped or resetting exit gracefully and wait to be * started again before accessing the hardware. */ if (hw->adapter_stopped) { pr_debug("Exiting because the adapter is already stopped!!!\n"); return false; } /* Set the Adapter Stopped flag so other driver functions stop * touching the Hardware. */ hw->adapter_stopped = true; /* Clear interrupt mask to stop board from generating interrupts */ pr_debug("Masking off all interrupts\n"); IXGB_WRITE_REG(hw, IMC, 0xFFFFFFFF); /* Disable the Transmit and Receive units. Then delay to allow * any pending transactions to complete before we hit the MAC with * the global reset. */ IXGB_WRITE_REG(hw, RCTL, IXGB_READ_REG(hw, RCTL) & ~IXGB_RCTL_RXEN); IXGB_WRITE_REG(hw, TCTL, IXGB_READ_REG(hw, TCTL) & ~IXGB_TCTL_TXEN); IXGB_WRITE_FLUSH(hw); msleep(IXGB_DELAY_BEFORE_RESET); /* Issue a global reset to the MAC. This will reset the chip's * transmit, receive, DMA, and link units. It will not effect * the current PCI configuration. The global reset bit is self- * clearing, and should clear within a microsecond. */ pr_debug("Issuing a global reset to MAC\n"); ctrl_reg = ixgb_mac_reset(hw); /* Clear interrupt mask to stop board from generating interrupts */ pr_debug("Masking off all interrupts\n"); IXGB_WRITE_REG(hw, IMC, 0xffffffff); /* Clear any pending interrupt events. */ icr_reg = IXGB_READ_REG(hw, ICR); return ctrl_reg & IXGB_CTRL0_RST; }
/****************************************************************************** * Waits for the EEPROM to finish the current command. * * hw - Struct containing variables accessed by shared code * * The command is done when the EEPROM's data out pin goes high. * * Returns: * true: EEPROM data pin is high before timeout. * false: Time expired. *****************************************************************************/ static bool ixgb_wait_eeprom_command(struct ixgb_hw *hw) { u32 eecd_reg; u32 i; /* Toggle the CS line. This in effect tells to EEPROM to actually execute * the command in question. */ ixgb_standby_eeprom(hw); /* Now read DO repeatedly until is high (equal to '1'). The EEPROM will * signal that the command has been completed by raising the DO signal. * If DO does not go high in 10 milliseconds, then error out. */ for (i = 0; i < 200; i++) { eecd_reg = IXGB_READ_REG(hw, EECD); if (eecd_reg & IXGB_EECD_DO) return true; udelay(50); } ASSERT(0); return false; }
/****************************************************************************** * Returns EEPROM to a "standby" state * * hw - Struct containing variables accessed by shared code *****************************************************************************/ static void ixgb_standby_eeprom(struct ixgb_hw *hw) { u32 eecd_reg; eecd_reg = IXGB_READ_REG(hw, EECD); /* Deselect EEPROM */ eecd_reg &= ~(IXGB_EECD_CS | IXGB_EECD_SK); IXGB_WRITE_REG(hw, EECD, eecd_reg); IXGB_WRITE_FLUSH(hw); udelay(50); /* Clock high */ eecd_reg |= IXGB_EECD_SK; IXGB_WRITE_REG(hw, EECD, eecd_reg); IXGB_WRITE_FLUSH(hw); udelay(50); /* Select EEPROM */ eecd_reg |= IXGB_EECD_CS; IXGB_WRITE_REG(hw, EECD, eecd_reg); IXGB_WRITE_FLUSH(hw); udelay(50); /* Clock low */ eecd_reg &= ~IXGB_EECD_SK; IXGB_WRITE_REG(hw, EECD, eecd_reg); IXGB_WRITE_FLUSH(hw); udelay(50); }
/****************************************************************************** * Terminates a command by lowering the EEPROM's chip select pin * * hw - Struct containing variables accessed by shared code *****************************************************************************/ static void ixgb_cleanup_eeprom(struct ixgb_hw *hw) { u32 eecd_reg; eecd_reg = IXGB_READ_REG(hw, EECD); eecd_reg &= ~(IXGB_EECD_CS | IXGB_EECD_DI); IXGB_WRITE_REG(hw, EECD, eecd_reg); ixgb_clock_eeprom(hw); }
/****************************************************************************** * Prepares EEPROM for access * * hw - Struct containing variables accessed by shared code * * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This * function should be called before issuing a command to the EEPROM. *****************************************************************************/ static void ixgb_setup_eeprom(struct ixgb_hw *hw) { u32 eecd_reg; eecd_reg = IXGB_READ_REG(hw, EECD); /* Clear SK and DI */ eecd_reg &= ~(IXGB_EECD_SK | IXGB_EECD_DI); IXGB_WRITE_REG(hw, EECD, eecd_reg); /* Set CS */ eecd_reg |= IXGB_EECD_CS; IXGB_WRITE_REG(hw, EECD, eecd_reg); }
/****************************************************************************** * Raises then lowers the EEPROM's clock pin * * hw - Struct containing variables accessed by shared code *****************************************************************************/ static void ixgb_clock_eeprom(struct ixgb_hw *hw) { u32 eecd_reg; eecd_reg = IXGB_READ_REG(hw, EECD); /* Rising edge of clock */ eecd_reg |= IXGB_EECD_SK; IXGB_WRITE_REG(hw, EECD, eecd_reg); udelay(50); /* Falling edge of clock */ eecd_reg &= ~IXGB_EECD_SK; IXGB_WRITE_REG(hw, EECD, eecd_reg); udelay(50); }
static u32 ixgb_mac_reset(struct ixgb_hw *hw) { u32 ctrl_reg; ctrl_reg = IXGB_CTRL0_RST | IXGB_CTRL0_SDP3_DIR | /* All pins are Output=1 */ IXGB_CTRL0_SDP2_DIR | IXGB_CTRL0_SDP1_DIR | IXGB_CTRL0_SDP0_DIR | IXGB_CTRL0_SDP3 | /* Initial value 1101 */ IXGB_CTRL0_SDP2 | IXGB_CTRL0_SDP0; #ifdef HP_ZX1 /* Workaround for 82597EX reset errata */ IXGB_WRITE_REG_IO(hw, CTRL0, ctrl_reg); #else IXGB_WRITE_REG(hw, CTRL0, ctrl_reg); #endif /* Delay a few ms just to allow the reset to complete */ msleep(IXGB_DELAY_AFTER_RESET); ctrl_reg = IXGB_READ_REG(hw, CTRL0); #ifdef DBG /* Make sure the self-clearing global reset bit did self clear */ ASSERT(!(ctrl_reg & IXGB_CTRL0_RST)); #endif if (hw->subsystem_vendor_id == PCI_VENDOR_ID_SUN) { ctrl_reg = /* Enable interrupt from XFP and SerDes */ IXGB_CTRL1_GPI0_EN | IXGB_CTRL1_SDP6_DIR | IXGB_CTRL1_SDP7_DIR | IXGB_CTRL1_SDP6 | IXGB_CTRL1_SDP7; IXGB_WRITE_REG(hw, CTRL1, ctrl_reg); ixgb_optics_reset_bcm(hw); } if (hw->phy_type == ixgb_phy_type_txn17401) ixgb_optics_reset(hw); return ctrl_reg; }
/****************************************************************************** * Shift data bits out to the EEPROM. * * hw - Struct containing variables accessed by shared code * data - data to send to the EEPROM * count - number of bits to shift out *****************************************************************************/ static void ixgb_shift_out_bits(struct ixgb_hw *hw, u16 data, u16 count) { u32 eecd_reg; u32 mask; /* We need to shift "count" bits out to the EEPROM. So, value in the * "data" parameter will be shifted out to the EEPROM one bit at a time. * In order to do this, "data" must be broken down into bits. */ mask = 0x01 << (count - 1); eecd_reg = IXGB_READ_REG(hw, EECD); eecd_reg &= ~(IXGB_EECD_DO | IXGB_EECD_DI); do { /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", * and then raising and then lowering the clock (the SK bit controls * the clock input to the EEPROM). A "0" is shifted out to the EEPROM * by setting "DI" to "0" and then raising and then lowering the clock. */ eecd_reg &= ~IXGB_EECD_DI; if (data & mask) eecd_reg |= IXGB_EECD_DI; IXGB_WRITE_REG(hw, EECD, eecd_reg); IXGB_WRITE_FLUSH(hw); udelay(50); ixgb_raise_clock(hw, &eecd_reg); ixgb_lower_clock(hw, &eecd_reg); mask = mask >> 1; } while (mask); /* We leave the "DI" bit set to "0" when we leave this routine. */ eecd_reg &= ~IXGB_EECD_DI; IXGB_WRITE_REG(hw, EECD, eecd_reg); }
static void ixgb_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p) { struct ixgb_adapter *adapter = netdev_priv(netdev); struct ixgb_hw *hw = &adapter->hw; u32 *reg = p; u32 *reg_start = reg; u8 i; /* the 1 (one) below indicates an attempt at versioning, if the * interface in ethtool or the driver changes, this 1 should be * incremented */ regs->version = (1<<24) | hw->revision_id << 16 | hw->device_id; /* General Registers */ *reg++ = IXGB_READ_REG(hw, CTRL0); /* 0 */ *reg++ = IXGB_READ_REG(hw, CTRL1); /* 1 */ *reg++ = IXGB_READ_REG(hw, STATUS); /* 2 */ *reg++ = IXGB_READ_REG(hw, EECD); /* 3 */ *reg++ = IXGB_READ_REG(hw, MFS); /* 4 */ /* Interrupt */ *reg++ = IXGB_READ_REG(hw, ICR); /* 5 */ *reg++ = IXGB_READ_REG(hw, ICS); /* 6 */ *reg++ = IXGB_READ_REG(hw, IMS); /* 7 */ *reg++ = IXGB_READ_REG(hw, IMC); /* 8 */ /* Receive */ *reg++ = IXGB_READ_REG(hw, RCTL); /* 9 */ *reg++ = IXGB_READ_REG(hw, FCRTL); /* 10 */ *reg++ = IXGB_READ_REG(hw, FCRTH); /* 11 */ *reg++ = IXGB_READ_REG(hw, RDBAL); /* 12 */ *reg++ = IXGB_READ_REG(hw, RDBAH); /* 13 */ *reg++ = IXGB_READ_REG(hw, RDLEN); /* 14 */ *reg++ = IXGB_READ_REG(hw, RDH); /* 15 */ *reg++ = IXGB_READ_REG(hw, RDT); /* 16 */ *reg++ = IXGB_READ_REG(hw, RDTR); /* 17 */ *reg++ = IXGB_READ_REG(hw, RXDCTL); /* 18 */ *reg++ = IXGB_READ_REG(hw, RAIDC); /* 19 */ *reg++ = IXGB_READ_REG(hw, RXCSUM); /* 20 */ /* there are 16 RAR entries in hardware, we only use 3 */ for (i = 0; i < IXGB_ALL_RAR_ENTRIES; i++) { *reg++ = IXGB_READ_REG_ARRAY(hw, RAL, (i << 1)); /*21,...,51 */ *reg++ = IXGB_READ_REG_ARRAY(hw, RAH, (i << 1)); /*22,...,52 */ } /* Transmit */ *reg++ = IXGB_READ_REG(hw, TCTL); /* 53 */ *reg++ = IXGB_READ_REG(hw, TDBAL); /* 54 */ *reg++ = IXGB_READ_REG(hw, TDBAH); /* 55 */ *reg++ = IXGB_READ_REG(hw, TDLEN); /* 56 */ *reg++ = IXGB_READ_REG(hw, TDH); /* 57 */ *reg++ = IXGB_READ_REG(hw, TDT); /* 58 */ *reg++ = IXGB_READ_REG(hw, TIDV); /* 59 */ *reg++ = IXGB_READ_REG(hw, TXDCTL); /* 60 */ *reg++ = IXGB_READ_REG(hw, TSPMT); /* 61 */ *reg++ = IXGB_READ_REG(hw, PAP); /* 62 */ /* Physical */ *reg++ = IXGB_READ_REG(hw, PCSC1); /* 63 */ *reg++ = IXGB_READ_REG(hw, PCSC2); /* 64 */ *reg++ = IXGB_READ_REG(hw, PCSS1); /* 65 */ *reg++ = IXGB_READ_REG(hw, PCSS2); /* 66 */ *reg++ = IXGB_READ_REG(hw, XPCSS); /* 67 */ *reg++ = IXGB_READ_REG(hw, UCCR); /* 68 */ *reg++ = IXGB_READ_REG(hw, XPCSTC); /* 69 */ *reg++ = IXGB_READ_REG(hw, MACA); /* 70 */ *reg++ = IXGB_READ_REG(hw, APAE); /* 71 */ *reg++ = IXGB_READ_REG(hw, ARD); /* 72 */ *reg++ = IXGB_READ_REG(hw, AIS); /* 73 */ *reg++ = IXGB_READ_REG(hw, MSCA); /* 74 */ *reg++ = IXGB_READ_REG(hw, MSRWD); /* 75 */ /* Statistics */ *reg++ = IXGB_GET_STAT(adapter, tprl); /* 76 */ *reg++ = IXGB_GET_STAT(adapter, tprh); /* 77 */ *reg++ = IXGB_GET_STAT(adapter, gprcl); /* 78 */ *reg++ = IXGB_GET_STAT(adapter, gprch); /* 79 */ *reg++ = IXGB_GET_STAT(adapter, bprcl); /* 80 */ *reg++ = IXGB_GET_STAT(adapter, bprch); /* 81 */ *reg++ = IXGB_GET_STAT(adapter, mprcl); /* 82 */ *reg++ = IXGB_GET_STAT(adapter, mprch); /* 83 */ *reg++ = IXGB_GET_STAT(adapter, uprcl); /* 84 */ *reg++ = IXGB_GET_STAT(adapter, uprch); /* 85 */ *reg++ = IXGB_GET_STAT(adapter, vprcl); /* 86 */ *reg++ = IXGB_GET_STAT(adapter, vprch); /* 87 */ *reg++ = IXGB_GET_STAT(adapter, jprcl); /* 88 */ *reg++ = IXGB_GET_STAT(adapter, jprch); /* 89 */ *reg++ = IXGB_GET_STAT(adapter, gorcl); /* 90 */ *reg++ = IXGB_GET_STAT(adapter, gorch); /* 91 */ *reg++ = IXGB_GET_STAT(adapter, torl); /* 92 */ *reg++ = IXGB_GET_STAT(adapter, torh); /* 93 */ *reg++ = IXGB_GET_STAT(adapter, rnbc); /* 94 */ *reg++ = IXGB_GET_STAT(adapter, ruc); /* 95 */ *reg++ = IXGB_GET_STAT(adapter, roc); /* 96 */ *reg++ = IXGB_GET_STAT(adapter, rlec); /* 97 */ *reg++ = IXGB_GET_STAT(adapter, crcerrs); /* 98 */ *reg++ = IXGB_GET_STAT(adapter, icbc); /* 99 */ *reg++ = IXGB_GET_STAT(adapter, ecbc); /* 100 */ *reg++ = IXGB_GET_STAT(adapter, mpc); /* 101 */ *reg++ = IXGB_GET_STAT(adapter, tptl); /* 102 */ *reg++ = IXGB_GET_STAT(adapter, tpth); /* 103 */ *reg++ = IXGB_GET_STAT(adapter, gptcl); /* 104 */ *reg++ = IXGB_GET_STAT(adapter, gptch); /* 105 */ *reg++ = IXGB_GET_STAT(adapter, bptcl); /* 106 */ *reg++ = IXGB_GET_STAT(adapter, bptch); /* 107 */ *reg++ = IXGB_GET_STAT(adapter, mptcl); /* 108 */ *reg++ = IXGB_GET_STAT(adapter, mptch); /* 109 */ *reg++ = IXGB_GET_STAT(adapter, uptcl); /* 110 */ *reg++ = IXGB_GET_STAT(adapter, uptch); /* 111 */ *reg++ = IXGB_GET_STAT(adapter, vptcl); /* 112 */ *reg++ = IXGB_GET_STAT(adapter, vptch); /* 113 */ *reg++ = IXGB_GET_STAT(adapter, jptcl); /* 114 */ *reg++ = IXGB_GET_STAT(adapter, jptch); /* 115 */ *reg++ = IXGB_GET_STAT(adapter, gotcl); /* 116 */ *reg++ = IXGB_GET_STAT(adapter, gotch); /* 117 */ *reg++ = IXGB_GET_STAT(adapter, totl); /* 118 */ *reg++ = IXGB_GET_STAT(adapter, toth); /* 119 */ *reg++ = IXGB_GET_STAT(adapter, dc); /* 120 */ *reg++ = IXGB_GET_STAT(adapter, plt64c); /* 121 */ *reg++ = IXGB_GET_STAT(adapter, tsctc); /* 122 */ *reg++ = IXGB_GET_STAT(adapter, tsctfc); /* 123 */ *reg++ = IXGB_GET_STAT(adapter, ibic); /* 124 */ *reg++ = IXGB_GET_STAT(adapter, rfc); /* 125 */ *reg++ = IXGB_GET_STAT(adapter, lfc); /* 126 */ *reg++ = IXGB_GET_STAT(adapter, pfrc); /* 127 */ *reg++ = IXGB_GET_STAT(adapter, pftc); /* 128 */ *reg++ = IXGB_GET_STAT(adapter, mcfrc); /* 129 */ *reg++ = IXGB_GET_STAT(adapter, mcftc); /* 130 */ *reg++ = IXGB_GET_STAT(adapter, xonrxc); /* 131 */ *reg++ = IXGB_GET_STAT(adapter, xontxc); /* 132 */ *reg++ = IXGB_GET_STAT(adapter, xoffrxc); /* 133 */ *reg++ = IXGB_GET_STAT(adapter, xofftxc); /* 134 */ *reg++ = IXGB_GET_STAT(adapter, rjc); /* 135 */ regs->len = (reg - reg_start) * sizeof(u32); }
static void ixgb_ethtool_gregs(struct net_device *dev, struct ethtool_regs *regs, void *buf) { struct ixgb_adapter *adapter = dev->priv; struct ixgb_hw *hw = &adapter->hw; uint32_t *reg = buf; uint32_t *reg_start = reg; uint8_t i; regs->version = (adapter->hw.device_id << 16) | adapter->hw.subsystem_id; /* General Registers */ *reg++ = IXGB_READ_REG(hw, CTRL0); /* 0 */ *reg++ = IXGB_READ_REG(hw, CTRL1); /* 1 */ *reg++ = IXGB_READ_REG(hw, STATUS); /* 2 */ *reg++ = IXGB_READ_REG(hw, EECD); /* 3 */ *reg++ = IXGB_READ_REG(hw, MFS); /* 4 */ /* Interrupt */ *reg++ = IXGB_READ_REG(hw, ICR); /* 5 */ *reg++ = IXGB_READ_REG(hw, ICS); /* 6 */ *reg++ = IXGB_READ_REG(hw, IMS); /* 7 */ *reg++ = IXGB_READ_REG(hw, IMC); /* 8 */ /* Receive */ *reg++ = IXGB_READ_REG(hw, RCTL); /* 9 */ *reg++ = IXGB_READ_REG(hw, FCRTL); /* 10 */ *reg++ = IXGB_READ_REG(hw, FCRTH); /* 11 */ *reg++ = IXGB_READ_REG(hw, RDBAL); /* 12 */ *reg++ = IXGB_READ_REG(hw, RDBAH); /* 13 */ *reg++ = IXGB_READ_REG(hw, RDLEN); /* 14 */ *reg++ = IXGB_READ_REG(hw, RDH); /* 15 */ *reg++ = IXGB_READ_REG(hw, RDT); /* 16 */ *reg++ = IXGB_READ_REG(hw, RDTR); /* 17 */ *reg++ = IXGB_READ_REG(hw, RXDCTL); /* 18 */ *reg++ = IXGB_READ_REG(hw, RAIDC); /* 19 */ *reg++ = IXGB_READ_REG(hw, RXCSUM); /* 20 */ for (i = 0; i < IXGB_RAR_ENTRIES; i++) { *reg++ = IXGB_READ_REG_ARRAY(hw, RAL, (i << 1)); /*21,...,51 */ *reg++ = IXGB_READ_REG_ARRAY(hw, RAH, (i << 1)); /*22,...,52 */ } /* Transmit */ *reg++ = IXGB_READ_REG(hw, TCTL); /* 53 */ *reg++ = IXGB_READ_REG(hw, TDBAL); /* 54 */ *reg++ = IXGB_READ_REG(hw, TDBAH); /* 55 */ *reg++ = IXGB_READ_REG(hw, TDLEN); /* 56 */ *reg++ = IXGB_READ_REG(hw, TDH); /* 57 */ *reg++ = IXGB_READ_REG(hw, TDT); /* 58 */ *reg++ = IXGB_READ_REG(hw, TIDV); /* 59 */ *reg++ = IXGB_READ_REG(hw, TXDCTL); /* 60 */ *reg++ = IXGB_READ_REG(hw, TSPMT); /* 61 */ *reg++ = IXGB_READ_REG(hw, PAP); /* 62 */ /* Physical */ *reg++ = IXGB_READ_REG(hw, PCSC1); /* 63 */ *reg++ = IXGB_READ_REG(hw, PCSC2); /* 64 */ *reg++ = IXGB_READ_REG(hw, PCSS1); /* 65 */ *reg++ = IXGB_READ_REG(hw, PCSS2); /* 66 */ *reg++ = IXGB_READ_REG(hw, XPCSS); /* 67 */ *reg++ = IXGB_READ_REG(hw, UCCR); /* 68 */ *reg++ = IXGB_READ_REG(hw, XPCSTC); /* 69 */ *reg++ = IXGB_READ_REG(hw, MACA); /* 70 */ *reg++ = IXGB_READ_REG(hw, APAE); /* 71 */ *reg++ = IXGB_READ_REG(hw, ARD); /* 72 */ *reg++ = IXGB_READ_REG(hw, AIS); /* 73 */ *reg++ = IXGB_READ_REG(hw, MSCA); /* 74 */ *reg++ = IXGB_READ_REG(hw, MSRWD); /* 75 */ /* Statistics */ *reg++ = IXGB_GET_STAT(adapter, tprl); /* 76 */ *reg++ = IXGB_GET_STAT(adapter, tprh); /* 77 */ *reg++ = IXGB_GET_STAT(adapter, gprcl); /* 78 */ *reg++ = IXGB_GET_STAT(adapter, gprch); /* 79 */ *reg++ = IXGB_GET_STAT(adapter, bprcl); /* 80 */ *reg++ = IXGB_GET_STAT(adapter, bprch); /* 81 */ *reg++ = IXGB_GET_STAT(adapter, mprcl); /* 82 */ *reg++ = IXGB_GET_STAT(adapter, mprch); /* 83 */ *reg++ = IXGB_GET_STAT(adapter, uprcl); /* 84 */ *reg++ = IXGB_GET_STAT(adapter, uprch); /* 85 */ *reg++ = IXGB_GET_STAT(adapter, vprcl); /* 86 */ *reg++ = IXGB_GET_STAT(adapter, vprch); /* 87 */ *reg++ = IXGB_GET_STAT(adapter, jprcl); /* 88 */ *reg++ = IXGB_GET_STAT(adapter, jprch); /* 89 */ *reg++ = IXGB_GET_STAT(adapter, gorcl); /* 90 */ *reg++ = IXGB_GET_STAT(adapter, gorch); /* 91 */ *reg++ = IXGB_GET_STAT(adapter, torl); /* 92 */ *reg++ = IXGB_GET_STAT(adapter, torh); /* 93 */ *reg++ = IXGB_GET_STAT(adapter, rnbc); /* 94 */ *reg++ = IXGB_GET_STAT(adapter, ruc); /* 95 */ *reg++ = IXGB_GET_STAT(adapter, roc); /* 96 */ *reg++ = IXGB_GET_STAT(adapter, rlec); /* 97 */ *reg++ = IXGB_GET_STAT(adapter, crcerrs); /* 98 */ *reg++ = IXGB_GET_STAT(adapter, icbc); /* 99 */ *reg++ = IXGB_GET_STAT(adapter, ecbc); /* 100 */ *reg++ = IXGB_GET_STAT(adapter, mpc); /* 101 */ *reg++ = IXGB_GET_STAT(adapter, tptl); /* 102 */ *reg++ = IXGB_GET_STAT(adapter, tpth); /* 103 */ *reg++ = IXGB_GET_STAT(adapter, gptcl); /* 104 */ *reg++ = IXGB_GET_STAT(adapter, gptch); /* 105 */ *reg++ = IXGB_GET_STAT(adapter, bptcl); /* 106 */ *reg++ = IXGB_GET_STAT(adapter, bptch); /* 107 */ *reg++ = IXGB_GET_STAT(adapter, mptcl); /* 108 */ *reg++ = IXGB_GET_STAT(adapter, mptch); /* 109 */ *reg++ = IXGB_GET_STAT(adapter, uptcl); /* 110 */ *reg++ = IXGB_GET_STAT(adapter, uptch); /* 111 */ *reg++ = IXGB_GET_STAT(adapter, vptcl); /* 112 */ *reg++ = IXGB_GET_STAT(adapter, vptch); /* 113 */ *reg++ = IXGB_GET_STAT(adapter, jptcl); /* 114 */ *reg++ = IXGB_GET_STAT(adapter, jptch); /* 115 */ *reg++ = IXGB_GET_STAT(adapter, gotcl); /* 116 */ *reg++ = IXGB_GET_STAT(adapter, gotch); /* 117 */ *reg++ = IXGB_GET_STAT(adapter, totl); /* 118 */ *reg++ = IXGB_GET_STAT(adapter, toth); /* 119 */ *reg++ = IXGB_GET_STAT(adapter, dc); /* 120 */ *reg++ = IXGB_GET_STAT(adapter, plt64c); /* 121 */ *reg++ = IXGB_GET_STAT(adapter, tsctc); /* 122 */ *reg++ = IXGB_GET_STAT(adapter, tsctfc); /* 123 */ *reg++ = IXGB_GET_STAT(adapter, ibic); /* 124 */ *reg++ = IXGB_GET_STAT(adapter, rfc); /* 125 */ *reg++ = IXGB_GET_STAT(adapter, lfc); /* 126 */ *reg++ = IXGB_GET_STAT(adapter, pfrc); /* 127 */ *reg++ = IXGB_GET_STAT(adapter, pftc); /* 128 */ *reg++ = IXGB_GET_STAT(adapter, mcfrc); /* 129 */ *reg++ = IXGB_GET_STAT(adapter, mcftc); /* 130 */ *reg++ = IXGB_GET_STAT(adapter, xonrxc); /* 131 */ *reg++ = IXGB_GET_STAT(adapter, xontxc); /* 132 */ *reg++ = IXGB_GET_STAT(adapter, xoffrxc); /* 133 */ *reg++ = IXGB_GET_STAT(adapter, xofftxc); /* 134 */ *reg++ = IXGB_GET_STAT(adapter, rjc); /* 135 */ regs->len = (reg - reg_start) * sizeof(uint32_t); }