static void SetVGAHorizontalSync31kHzAtInterrupt(InterruptHandler *handler,int dier)
{
WaitForLastLineIfVGAEnabled();
TIM2->DIER=dier;
TIM2->CCER=TIM_CCER_CC4E|TIM_CCER_CC4P; // Channel 4 enabled, reversed polarity (active low).
// Enable HSync timer interrupt and set highest priority.
InstallInterruptHandler(TIM2_IRQn,handler);
EnableInterrupt(TIM2_IRQn);
SetInterruptPriority(TIM2_IRQn,0);
}
static void SetVGAHorizontalSync31kHzActiveHighAtInterrupt(InterruptHandler *handler,int dier)
{
WaitForLastLineIfVGAEnabled();
TIM2->DIER=dier; // Enable update interrupt.
TIM2->CCER=TIM_CCER_CC4E; // Channel 4 enabled, normal polarity (active high).
// Enable HSync timer interrupt and set highest priority.
InstallInterruptHandler(TIM2_IRQn,handler);
EnableInterrupt(TIM2_IRQn);
SetInterruptPriority(TIM2_IRQn,0);
}
static void InitializePixelDMA(int pixelclock)
{
// Configure timer 8 as the pixel clock.
TIM8->CR1=TIM_CR1_ARPE;
TIM8->DIER=TIM_DIER_UDE; // Enable update DMA request.
TIM8->PSC=0; // Prescaler = 1
TIM8->ARR=pixelclock-1; // TODO: Should this be -1?
// DMA2 stream 1 channel 7 is triggered by timer 8.
// Stop it and configure interrupts.
DMA2_Stream1->CR&=~DMA_SxCR_EN;
InstallInterruptHandler(DMA2_Stream1_IRQn,DMACompleteHandler);
EnableInterrupt(DMA2_Stream1_IRQn);
SetInterruptPriority(DMA2_Stream1_IRQn,0);
}
void PlayAudioWithCallback(AudioCallbackFunction *callback,void *context)
{
StopAudioDMA();
InstallInterruptHandler(DMA1_Stream7_IRQn,DMACompleteHandler);
EnableInterrupt(DMA1_Stream7_IRQn);
SetInterruptPriority(DMA1_Stream7_IRQn,4);
SPI3->CR2|=SPI_CR2_TXDMAEN; // Enable I2S TX DMA request.
CallbackFunction=callback;
CallbackContext=context;
BufferNumber=0;
if(CallbackFunction) CallbackFunction(CallbackContext,BufferNumber);
}
static void InitializePixelDMA(int pixelclock,int pixelsperrow)
{
// Configure timer 8 as the pixel clock.
TIM8->CR1=TIM_CR1_ARPE;
TIM8->DIER=TIM_DIER_UDE; // Enable update DMA request.
TIM8->PSC=0; // Prescaler = 1.
TIM8->ARR=pixelclock-1;
TIM8->SMCR=(5*TIM_SMCR_SMS_0)|(1*TIM_SMCR_TS_0); // Only run TIM8 when TIM2 trigger-out is high.
// DMA2 stream 1 channel 7 is triggered by timer 8.
// Stop it and configure interrupts.
DMA2_Stream1->CR&=~DMA_SxCR_EN;
InstallInterruptHandler(DMA2_Stream1_IRQn,DMACompleteHandler);
EnableInterrupt(DMA2_Stream1_IRQn);
SetInterruptPriority(DMA2_Stream1_IRQn,0);
VGAPixelsPerRow=pixelsperrow;
}
void InitializeVGAHorizontalSync31kHz(InterruptHandler *handler)
{
// Configure timer 9 as the HSYNC timer.
TIM9->CR1=TIM_CR1_ARPE;
TIM9->DIER=TIM_DIER_UIE|TIM_DIER_CC1IE|TIM_DIER_CC2IE; // Enable update, compare 1 and 2 interrupts.
TIM9->CCMR1=0;
TIM9->CCER=0;
TIM9->PSC=0; // Prescaler = 1
TIM9->ARR=5337; // 168 MHz / 31.4686 kHz = 5338.65504
TIM9->CCR1=633; // 168 MHz * 3.77 microseconds = 633.36 - sync pulse end
TIM9->CCR2=950; // 168 MHz * (3.77 + 1.89) microseconds = 950.88 - back porch end
// Enable HSYNC timer interrupt and set highest priority.
InstallInterruptHandler(TIM1_BRK_TIM9_IRQn,handler);
EnableInterrupt(TIM1_BRK_TIM9_IRQn);
SetInterruptPriority(TIM1_BRK_TIM9_IRQn,0);
// Enable HSYNC timer.
TIM9->CR1|=TIM_CR1_CEN;
}
HDI_STATUS HDIInit (ULONG *self_test_result_p)
{
HDI_STATUS status = OK;
USHORT num_args = 1;
#ifdef COMPILE_FOR_CORE
static const char ver[] = "1.0.6 @"__DATE__ "";
#else
static const char ver[] = "1.0.6 @"__DATE__ "";
#endif /* COMPILE_FOR_CORE */
#ifdef COMPILE_FOR_CORE
#ifdef DEBUG
const char RcsId[] = "@@MainDriver@[email protected]@GK6105S@DEBUG@"__DATE__ "@";
#else
const char RcsId[] = "@@MainDriver@[email protected]@GK6105S@PRODUCT@"__DATE__ "@";
#endif /* DEBUG */
#else /* COMPILE_FOR_CORE */
#ifdef DEBUG
const char RcsId[] = "@@FGDLDriver@[email protected]@GK6105S@DEBUG@"__DATE__ "@";
#else
const char RcsId[] = "@@FGDLDriver@[email protected]@GK6105S@PRODUCT@"__DATE__ "@";
#endif /* DEBUG */
#endif /* COMPILE_FOR_CORE */
#ifdef COMPILE_FOR_CORE
if ( CORESetDriverInfo((const USHORT)num_args, (const UBYTE *)ver) == NOT_OK )
{
status = NOT_OK;
}
#endif /* COMPILE_FOR_CORE */
//Added by anthony for GAPI init
GND_InitGAPI();
XD_UaInitUart(GD_UART_BAUD_RATE115200);
//GNH_ARC_set_IRQEnable(0xFFFFFFFF);
XD_CiDefaultChipInit ();
#ifdef ALLOW_DEBUG_OUTPUT_IN_DRIVERS // allow debug output in other modules (otherwise Link-Error!)
DebSetDebSystemMessageLevel(3); // NOTE: Set Debug Message Output Level -> enable all
if (&APP_PROG_START_MSG)
{
//GM_Printf(APP_PROG_START_MSG);
}
else
{
//GM_Printf(INIT_CLEAR_MSG);
//GM_Printf(STARS_MSG);
if ( (U32)&__PROGRAM_START == FGDL_START_ADDRESS) //GM_Printf(START_FGDL_MSG);
else if ((U32)&__PROGRAM_START == CORE_START_ADDRESS) //GM_Printf(START_MAIN_MSG);
else //GM_Printf(MINICORE_START_MSG);
//GM_Printf(STARS_MSG);
}
if (XD_CiMpegU32ShadowRegData[SHR32IDX_BANKSIZE]) // if detected only 64MBit
{
//GM_Printf((CSTR *)"\nSmartMPeg Chip-Init : Big-Memory");
}
else
{
//GM_Printf((CSTR *)"\nSmartMPeg Chip-Init : Small-Memory");
}
#endif /* ALLOW_DEBUG_OUTPUT_IN_DRIVERS */
if (!XD_CiMpegU32ShadowRegData[SHR32IDX_BANKSIZE]) // if detected only 64MBit
{
SYS_DEBUG_INFO(DEBL0_NSTR,(CSTR*)"x <STB-dones not have enough memory>",0,0,0);
while (1);
}
#ifdef COMPILE_FOR_CORE
SYS_DEBUG_INFO(DEBL2_NSTR, (CSTR*)"x OK, Init HDI-driver for CORE ...", 0,0,0);
#else
SYS_DEBUG_INFO(DEBL2_NSTR, (CSTR*)"x OK, Init HDI-driver for FGDL ...", 0,0,0);
#endif /* COMPILE_FOR_CORE */
/*
XD_SetColorSystem(GD_VENC_COLOR_SYSTEM_NTSC);
XD_SetDACs(GD_VENC_COMPOSITE_RGB);
*/
#ifdef COMPILE_FOR_CORE
//Set as hardware outputs
//XD_CiSetMpegSRegBits(SHR16IDX_GPIO_SELECT_LOW, BIT0 | BIT14);
//HDICA_2145_Init(); // Launches the CAHDI tasks and sets up HDI
#endif
GND_InitOsd(XD_OSD_PAL_OFFSETS); // init HDI-Osd-Driver
GND_InitHdiDemux();
#ifdef COMPILE_FOR_CORE
GND_InitStillLayer();
GND_InitIFrameDecode(IFRAME_MPEG_BUFFER, MAX_MPEG_IFRAME_DATA_SIZE, OSD_IFRAME_OSD_BUFFER);
//GND_InitLowSpeedData();
//GND_InitSectionFilterManager();//Nick add
#endif
#ifdef RELEASE_LIBS_FOR_INTEGRATION
#ifdef COMPILE_FOR_CORE
STT_EV_QUEUE = OSQCreate((void **)STT_QueueBuf, STT_QUEUE_SIZE);
OSAddTask((void (*)(void *))TestTask, TASK_TEST_PRIO, STACK_Test_Task, CPU_USE_STK_SIZE);
COREActivateProductionTest();
#else
COREWPActi vateCore (&flash_descp);
#endif /* COMPILE_FOR_CORE */
#else
#ifdef COMPILE_FOR_CORE
U8 Software_Version[]={"Main driver dummary test!"};
CORESetDriverInfo (1, (U8*)Software_Version);
#else /* COMPILE_FOR_CORE */
U8 Software_Version[]={"Fgdl driver dummary test!"};
#endif
#endif /* RELEASE_LIBS_FOR_INTEGRATION */
#ifdef COMPILE_FOR_CORE
#ifdef RELEASE_LIBS_FOR_INTEGRATION
//GH_TSD2_set_MuxSelect_MEM_EXCEP_EN(1);
//GM_Printf((CSTR*)"\n<Note: No MemExeption for loader !>");
#else
//GH_TSD2_set_MuxSelect_MEM_EXCEP_EN(0); // no Exeption for HDI-Test
//GM_Printf((CSTR*)"\n<Note: No MemExeption for MRS !>");
#endif
#endif
#ifdef COMPILE_FOR_FGDL
#ifndef RELEASE_LIBS_FOR_INTEGRATION
//GM_Printf((CSTR*)"\n<Note: No MemExeption for loader !>");
WR_MPEG_REG(REG_TSD2_MUXSELECT, 0x0000);
#endif
#endif
#ifdef ENABLE_DATA_CACHE
SYS_DEBUG_INFO(DEBL2_NSTR, (CSTR*)"***<CpuData-Cache Enabled>***", 0,0,0);
Cpu_EnableDataCache();
#endif
//Added by Anthony for keyboard
//GND_InitEddieUserIO();
//XD_UaInitUart(GD_UART_BAUD_RATE115200);
#ifdef COMPILE_FOR_FGDL
//GHA_WriteMpegReg(SHR16IDX_GPIO_SELECT_LOW,0x7c75);
#endif
#ifdef COMPILE_FOR_CORE
//GH_GPIO_set_MuxSelectLower(0x7c75);
#endif
GND_InitFrontEnd();
#ifdef COMPILE_FOR_FGDL
//GHA_WriteMpegReg(SHR16IDX_GPIO_SELECT_LOW,0x7c75);
#endif
#ifdef COMPILE_FOR_CORE
//GH_GPIO_set_MuxSelectLower(0x7c75);
#endif
FP_DRV_Initialise_New();
EEPROM_Init_New();
GND_InitVideo();
#ifdef COMPILE_FOR_CORE
GND_InitAudio();
#endif
//Nick add start
/*Add by Nick for NDS Kernel2 Hardware timer ISR Mark 2013 10 29*/
#ifdef COMPILE_FOR_CORE
/*Disable All ISR, OS will enable it when OSStart*/
GD_INT_OpenKernel2( );
_ASM("flag 0");
#endif
//Nick add end
//9/23/2004 6:29PM
#ifdef COMPILE_FOR_CORE
// Steven Yu: modify for MAIN xui20.c
HDIActivateAutoCommandIndicator(GFALSE); //add by maggie
CORESetRfFrontEndsXt(GFALSE,GTRUE,GFALSE,GFALSE,GFALSE);
InstallInterruptHandler(GD_INT_SLOW1_IRQ, (void *) ((U32)&OSTickISR));
#else
HDIActivateAutoCommandIndicator(GTRUE); //add by maggie
CORESetRfFrontEndsEx(CABLE, 0);
#endif
//_ASM("flag 6");
ARCAdjustIntVectTable();
// Add by Steven Yu: setmod20.scr initial operating mode is STANDBY_MODE.
HDISetOperatingMode (STANDBY_MODE);
{
U16 sectorCount;
U32 i;
GD_SFLASH_GetNumberOfSectors(gnd_sflash_handle, §orCount);
for(i=0;i<sectorCount;i++)
{
GD_SFLASH_Sector_Unlock(gnd_sflash_handle, i);
}
}
return (status);
}