void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) {
__IO uint32_t *dmy_ctr;
/* Wake-up Irq is not supported */
if (type != IRQ_WAKEUP) {
if (enable) {
dmy_ctr = CTR_MATCH[obj->ch];
if (type == IRQ_ERROR) {
/* EWIE interrupts is enable */
*dmy_ctr |= 0x00000200;
} else if (type == IRQ_OVERRUN) {
/* OLIE interrupts is enable */
*dmy_ctr |= 0x00002000;
} else if (type == IRQ_PASSIVE) {
/* EPIE interrupts is enable */
*dmy_ctr |= 0x00000400;
} else if (type == IRQ_ARB) {
/* ALIE interrupts is enable */
*dmy_ctr |= 0x00008000;
} else if (type == IRQ_BUS) {
/* BEIE interrupts is enable */
*dmy_ctr |= 0x00000100;
}
InterruptHandlerRegister(can_int_info[obj->ch][type].int_num, can_int_info[obj->ch][type].handler);
GIC_SetPriority(can_int_info[obj->ch][type].int_num, 5);
GIC_SetConfiguration(can_int_info[obj->ch][type].int_num, 1);
GIC_EnableIRQ(can_int_info[obj->ch][type].int_num);
} else {
GIC_DisableIRQ(can_int_info[obj->ch][type].int_num);
}
}
}
void start1msecInterrupt(void (*func)(void))
{
static bool started = false;
if (!started) {
CPG.STBCR5 &= ~CpgStbcr5Bit; // OsTimer power supply
OsTimer.OSTMnTT = 0b00000001; // Timer stop
msecCount = 0;
InterruptHandlerRegister(WrapAroundIrq, (IRQHandler)func);
GIC_SetPriority(WrapAroundIrq, 5);
GIC_EnableIRQ(WrapAroundIrq);
if (RZ_A1_IsClockMode0()) {
phy0ClockPeriod = CM0_RENESAS_RZ_A1_P0_CLK / 1000;
} else {
phy0ClockPeriod = CM1_RENESAS_RZ_A1_P0_CLK / 1000;
}
OsTimer.OSTMnCMP = phy0ClockPeriod - 1; // Interrupt generation timing
OsTimer.OSTMnCTL = 0b00000000; // Interval timer mode
// Interrupts disabled at count start
OsTimer.OSTMnTS = 0b00000001; // Count start
started = true;
}
}
void us_ticker_init(void) {
if (us_ticker_inited) return;
us_ticker_inited = 1;
/* set Counter Clock(us) */
if (false == RZ_A1_IsClockMode0()) {
count_clock = ((double)CM1_RENESAS_RZ_A1_P0_CLK / (double)US_TICKER_CLOCK_US_DEV);
} else {
count_clock = ((double)CM0_RENESAS_RZ_A1_P0_CLK / (double)US_TICKER_CLOCK_US_DEV);
}
/* Power Control for Peripherals */
CPGSTBCR5 &= ~(CPG_STBCR5_BIT_MSTP50); /* enable OSTM1 clock */
// timer settings
OSTM1TT = 0x01; /* Stop the counter and clears the OSTM1TE bit. */
OSTM1CTL = 0x02; /* Free running timer mode. Interrupt disabled when star counter */
OSTM1TS = 0x1; /* Start the counter and sets the OSTM0TE bit. */
// INTC settings
InterruptHandlerRegister(US_TICKER_TIMER_IRQn, (void (*)(uint32_t))us_ticker_interrupt);
GIC_SetPriority(US_TICKER_TIMER_IRQn, 5);
GIC_EnableIRQ(US_TICKER_TIMER_IRQn);
}
static void serial_irq_set_irq(IRQn_Type IRQn, IRQHandler handler, uint32_t enable)
{
if (enable) {
InterruptHandlerRegister(IRQn, (void (*)(uint32_t))handler);
GIC_SetPriority(IRQn, 5);
GIC_EnableIRQ(IRQn);
} else {
GIC_DisableIRQ(IRQn);
}
}
// Initialize alternative hardware timer as RTX kernel timer
// Return: IRQ number of the alternative hardware timer
int os_tick_init (void) {
#ifdef TARGET_RZ_A1H
CPGSTBCR5 &= ~(CPG_STBCR5_BIT_MSTP51); /* enable OSTM0 clock */
OSTM0TT = 0x1; /* Stop the counter and clears the OSTM0TE bit. */
OSTM0CTL = 0x1; /* Interval timer mode. Interrupt enabled */
OSTM0CMP = (uint32_t)(((double)CM0_RENESAS_RZ_A1_P0_CLK*(double)OS_TICK)/1E6);
OSTM0TS = 0x1; /* Start the counter and sets the OSTM0TE bit. */
InterruptHandlerRegister(IRQ_SGI0 , (IRQHandler)PendSV_Handler);
InterruptHandlerRegister(IRQ_OSTMI0TINT, (IRQHandler)OS_Tick_Handler);
return IRQ_OSTMI0TINT; /* Return IRQ number of timer (0..239) */
/* RTX will set and configure the interrupt */
#endif
}
static void i2c_irqs_set(i2c_t *obj, uint32_t enable)
{
int i;
const IRQn_Type *irqTable = irq_set_tbl[obj->i2c.i2c];
const IRQHandler *handlerTable = hander_set_tbl[obj->i2c.i2c];
for (i = 0; i < IRQ_NUM; ++i) {
if (enable) {
InterruptHandlerRegister(irqTable[i], handlerTable[i]);
GIC_SetPriority(irqTable[i], 5);
GIC_EnableIRQ(irqTable[i]);
} else {
GIC_DisableIRQ(irqTable[i]);
}
}
REG(IER.UINT8[0]) = enable ? 0x63 : 0x00;
}
static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) {
IRQn_Type IRQn;
IRQHandler handler;
IRQn = irq_set_tbl[obj->index][irq];
handler = hander_set_tbl[obj->index][irq];
if ((obj->index >= 0) && (obj->index <= 7)) {
if (enable) {
InterruptHandlerRegister(IRQn, (void (*)(uint32_t))handler);
GIC_SetPriority(IRQn, 5);
GIC_EnableIRQ(IRQn);
} else {
GIC_DisableIRQ(IRQn);
}
}
}
void lp_ticker_init(void)
{
GIC_DisableIRQ(LP_TICKER_TIMER_IRQn);
GIC_ClearPendingIRQ(LP_TICKER_TIMER_IRQn);
/* Power Control for Peripherals */
mtu2_init();
if (lp_ticker_inited) return;
lp_ticker_inited = 1;
MTU2TCR = MTU2_TCR_TPSC;
MTU2TSTR |= MTU2_TSTR_CST;
MTU2TIER |= MTU2_TIER_n_TGIEA;
// INTC settings
InterruptHandlerRegister(LP_TICKER_TIMER_IRQn, (void (*)(uint32_t))lp_ticker_irq_handler);
GIC_SetPriority(LP_TICKER_TIMER_IRQn, 5);
GIC_SetConfiguration(LP_TICKER_TIMER_IRQn, 3);
}
static void spi_irqs_set(spi_t *obj, uint32_t enable)
{
int i;
const IRQn_Type *irqTable = irq_set_tbl[obj->spi.index];
const IRQHandler *handlerTable = hander_set_tbl[obj->spi.index];
for (i = 0; i < IRQ_NUM; ++i) {
if (enable) {
InterruptHandlerRegister(irqTable[i], handlerTable[i]);
GIC_SetPriority(irqTable[i], 5);
GIC_EnableIRQ(irqTable[i]);
} else {
GIC_DisableIRQ(irqTable[i]);
}
}
if (enable) {
obj->spi.spi->SPCR |= (1 << 4) | (1 << 7);
} else {
obj->spi.spi->SPCR &= ~((1 << 4) | (1 << 7));
}
}
void us_ticker_init(void)
{
GIC_DisableIRQ(OSTMI1TINT_IRQn);
GIC_ClearPendingIRQ(OSTMI1TINT_IRQn);
/* Power Control for Peripherals */
CPGSTBCR5 &= ~(CPG_STBCR5_BIT_MSTP50); /* enable OSTM1 clock */
if (us_ticker_inited) return;
us_ticker_inited = 1;
// timer settings
OSTM1TT = 0x01; /* Stop the counter and clears the OSTM1TE bit. */
OSTM1CTL = 0x02; /* Free running timer mode. Interrupt disabled when star counter */
OSTM1TS = 0x1; /* Start the counter and sets the OSTM0TE bit. */
// INTC settings
InterruptHandlerRegister(OSTMI1TINT_IRQn, (void (*)(uint32_t))us_ticker_irq_handler);
GIC_SetPriority(OSTMI1TINT_IRQn, 5);
GIC_SetConfiguration(OSTMI1TINT_IRQn, 3);
}
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
InterruptHandlerRegister(IRQn, (IRQHandler)vector);
}
