VOID
MiscInitialization (
VOID
)
{
//
// Disable A20 Mask
//
IoOr8 (0x92, BIT1);
//
// Build the CPU hob with 36-bit addressing and 16-bits of IO space.
//
BuildCpuHob (36, 16);
//
// If PMREGMISC/PMIOSE is set, assume the ACPI PMBA has been configured (for
// example by Xen) and skip the setup here. This matches the logic in
// AcpiTimerLibConstructor ().
//
if ((PciRead8 (PCI_LIB_ADDRESS (0, 1, 3, 0x80)) & 0x01) == 0) {
//
// The PEI phase should be exited with fully accessibe PIIX4 IO space:
// 1. set PMBA
//
PciAndThenOr32 (
PCI_LIB_ADDRESS (0, 1, 3, 0x40),
(UINT32) ~0xFFC0,
PcdGet16 (PcdAcpiPmBaseAddress)
);
//
// 2. set PCICMD/IOSE
//
PciOr8 (
PCI_LIB_ADDRESS (0, 1, 3, PCI_COMMAND_OFFSET),
EFI_PCI_COMMAND_IO_SPACE
);
//
// 3. set PMREGMISC/PMIOSE
//
PciOr8 (PCI_LIB_ADDRESS (0, 1, 3, 0x80), 0x01);
}
}
VOID
MiscInitialization ()
{
//
// Disable A20 Mask
//
IoOr8 (0x92, BIT1);
//
// Build the CPU hob with 36-bit addressing and 16-bits of IO space.
//
BuildCpuHob (36, 16);
//
// Set the PM I/O base address to 0x400
//
PciAndThenOr32 (PCI_LIB_ADDRESS (0, 1, 3, 0x40), (UINT32) ~0xfc0, 0x400);
}
VOID
MiscInitialization (
VOID
)
{
UINTN PmCmd;
UINTN Pmba;
UINTN AcpiCtlReg;
UINT8 AcpiEnBit;
//
// Disable A20 Mask
//
IoOr8 (0x92, BIT1);
//
// Build the CPU HOB with guest RAM size dependent address width and 16-bits
// of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during
// S3 resume as well, so we build it unconditionally.)
//
BuildCpuHob (mPhysMemAddressWidth, 16);
//
// Determine platform type and save Host Bridge DID to PCD
//
switch (mHostBridgeDevId) {
case INTEL_82441_DEVICE_ID:
PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);
Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;
break;
case INTEL_Q35_MCH_DEVICE_ID:
PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);
Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);
AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;
break;
default:
DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
__FUNCTION__, mHostBridgeDevId));
ASSERT (FALSE);
return;
}
PcdSet16 (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);
//
// If the appropriate IOspace enable bit is set, assume the ACPI PMBA
// has been configured (e.g., by Xen) and skip the setup here.
// This matches the logic in AcpiTimerLibConstructor ().
//
if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {
//
// The PEI phase should be exited with fully accessibe ACPI PM IO space:
// 1. set PMBA
//
PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));
//
// 2. set PCICMD/IOSE
//
PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);
//
// 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)
//
PciOr8 (AcpiCtlReg, AcpiEnBit);
}
if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
//
// Set Root Complex Register Block BAR
//
PciWrite32 (
POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),
ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN
);
//
// Set PCI Express Register Range Base Address
//
PciExBarInitialization ();
}
}
