VOID
EFIAPI
PowerButtonCallback (
IN EFI_HANDLE DispatchHandle,
IN EFI_SMM_POWER_BUTTON_DISPATCH_CONTEXT *DispatchContext
)
{
//
// Check what the state to return to after AC Loss. If Last State, then
// set it to Off.
//
UINT16 data16;
if (mWakeOnRtcVariable) {
EnableS5WakeOnRtc();
}
if (mAcLossVariable == 1) {
SetAfterG3On (TRUE);
}
ClearP2PBusMaster();
//
// Program clock chip
//
S4S5ProgClock();
data16 = (UINT16)(IoRead16(mAcpiBaseAddr + R_PCH_ACPI_GPE0a_EN));
data16 &= B_PCH_ACPI_GPE0a_EN_PCI_EXP;
//
// Clear Sleep SMI Status
//
IoWrite16 (mAcpiBaseAddr + R_PCH_SMI_STS,
(UINT16)(IoRead16 (mAcpiBaseAddr + R_PCH_SMI_STS) | B_PCH_SMI_STS_ON_SLP_EN));
//
// Clear Sleep Type Enable
//
IoWrite16 (mAcpiBaseAddr + R_PCH_SMI_EN,
(UINT16)(IoRead16 (mAcpiBaseAddr + R_PCH_SMI_EN) & (~B_PCH_SMI_EN_ON_SLP_EN)));
//
// Clear Power Button Status
//
IoWrite16(mAcpiBaseAddr + R_PCH_ACPI_PM1_STS, B_PCH_ACPI_PM1_STS_PWRBTN);
//
// Shut it off now!
//
IoWrite16(mAcpiBaseAddr + R_PCH_ACPI_PM1_CNT, V_PCH_ACPI_PM1_CNT_S5);
IoWrite16(mAcpiBaseAddr + R_PCH_ACPI_PM1_CNT, B_PCH_ACPI_PM1_CNT_SLP_EN | V_PCH_ACPI_PM1_CNT_S5);
//
// Should not return
//
CpuDeadLoop();
}
BOOLEAN
GetSleepTypeAfterWakeup (
IN CONST EFI_PEI_SERVICES **PeiServices,
OUT UINT16 *SleepType
)
{
UINT16 Pm1Sts;
UINT16 Pm1Cnt;
UINT16 GenPmCon1;
//
// VLV BIOS Specification 0.6.2 - Section 18.4, "Power Failure Consideration"
//
// When the SUS_PWR_FLR bit is set, it indicates the SUS well power is lost.
// This bit is in the SUS Well and defaults to 1’b1 based on RSMRST# assertion (not cleared by any type of reset).
// System BIOS should follow cold boot path if SUS_PWR_FLR (PBASE + 0x20[14]),
// GEN_RST_STS (PBASE + 0x20[9]) or PWRBTNOR_STS (ABASE + 0x00[11]) is set to 1’b1
// regardless of the value in the SLP_TYP (ABASE + 0x04[12:10]) field.
//
GenPmCon1 = MmioRead16 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1);
//
// Read the ACPI registers
//
Pm1Sts = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS);
Pm1Cnt = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT);
if ((GenPmCon1 & (B_PCH_PMC_GEN_PMCON_SUS_PWR_FLR | B_PCH_PMC_GEN_PMCON_GEN_RST_STS)) ||
(Pm1Sts & B_PCH_ACPI_PM1_STS_PRBTNOR)) {
//
// If power failure indicator, then don't attempt s3 resume.
// Clear PM1_CNT of S3 and set it to S5 as we just had a power failure, and memory has
// lost already. This is to make sure no one will use PM1_CNT to check for S3 after
// power failure.
//
if ((Pm1Cnt & B_PCH_ACPI_PM1_CNT_SLP_TYP) == V_PCH_ACPI_PM1_CNT_S3) {
Pm1Cnt = ((Pm1Cnt & ~B_PCH_ACPI_PM1_CNT_SLP_TYP) | V_PCH_ACPI_PM1_CNT_S5);
IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT, Pm1Cnt);
}
//
// Clear Wake Status (WAK_STS)
//
}
//
// Get sleep type if a wake event occurred and there is no power failure
//
if ((Pm1Cnt & B_PCH_ACPI_PM1_CNT_SLP_TYP) == V_PCH_ACPI_PM1_CNT_S3) {
*SleepType = Pm1Cnt & B_PCH_ACPI_PM1_CNT_SLP_TYP;
return TRUE;
} else if ((Pm1Cnt & B_PCH_ACPI_PM1_CNT_SLP_TYP) == V_PCH_ACPI_PM1_CNT_S4) {
*SleepType = Pm1Cnt & B_PCH_ACPI_PM1_CNT_SLP_TYP;
return TRUE;
}
return FALSE;
}
/**
Reads I/O registers.
@param[in] PeiServices An indirect pointer to the PEI Services Table
published by the PEI Foundation.
@param[in] This Pointer to local data for the interface.
@param[in] Width The width of the access. Enumerated in bytes.
@param[in] Address The physical address of the access.
@param[in] Count The number of accesses to perform.
@param[out] Buffer A pointer to the buffer of data.
@retval EFI_SUCCESS The function completed successfully.
@retval EFI_INVALID_PARAMETER Width is invalid for this EFI system.
@retval EFI_INVALID_PARAMETER Buffer is NULL.
@retval EFI_UNSUPPORTED The address range specified by Address, Width,
and Count is not valid for this EFI system.
**/
EFI_STATUS
EFIAPI
CpuIoServiceRead (
IN CONST EFI_PEI_SERVICES **PeiServices,
IN CONST EFI_PEI_CPU_IO_PPI *This,
IN EFI_PEI_CPU_IO_PPI_WIDTH Width,
IN UINT64 Address,
IN UINTN Count,
OUT VOID *Buffer
)
{
EFI_STATUS Status;
UINT8 InStride;
UINT8 OutStride;
EFI_PEI_CPU_IO_PPI_WIDTH OperationWidth;
BOOLEAN Aligned;
UINT8 *Uint8Buffer;
Status = CpuIoCheckParameter (FALSE, Width, Address, Count, Buffer);
if (EFI_ERROR (Status)) {
return Status;
}
//
// Select loop based on the width of the transfer
//
InStride = mInStride[Width];
OutStride = mOutStride[Width];
OperationWidth = (EFI_PEI_CPU_IO_PPI_WIDTH) (Width & 0x03);
Aligned = (BOOLEAN)(((UINTN)Buffer & (mInStride[OperationWidth] - 1)) == 0x00);
for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
if (OperationWidth == EfiPeiCpuIoWidthUint8) {
*Uint8Buffer = IoRead8 ((UINTN)Address);
} else if (OperationWidth == EfiPeiCpuIoWidthUint16) {
if (Aligned) {
*((UINT16 *)Uint8Buffer) = IoRead16 ((UINTN)Address);
} else {
WriteUnaligned16 ((UINT16 *)Uint8Buffer, IoRead16 ((UINTN)Address));
}
} else if (OperationWidth == EfiPeiCpuIoWidthUint32) {
if (Aligned) {
*((UINT32 *)Uint8Buffer) = IoRead32 ((UINTN)Address);
} else {
WriteUnaligned32 ((UINT32 *)Uint8Buffer, IoRead32 ((UINTN)Address));
}
}
}
return EFI_SUCCESS;
}
VOID
CapsuleReset (
IN UINTN CapsuleDataPtr
)
/*++
Routine Description:
If need be, do any special reset required for capsules. For this
implementation where we're called from the ResetSystem () api,
just set our capsule variable and return to let the caller
do a soft reset.
Arguments:
CapsuleDataPtr - pointer to the capsule block descriptors
Returns:
Nothing.
--*/
{
UINT32 Eflags;
UINT16 PmCntl;
UINT16 AcpiPm1CntBase;
//
// This implementation assumes that we're using a variable
// to indicate capsule updates.
//
gST->RuntimeServices->SetVariable (
EFI_CAPSULE_VARIABLE_NAME,
&gEfiCapsuleVendorGuid,
EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_BOOTSERVICE_ACCESS,
sizeof (UINTN),
(VOID *) &CapsuleDataPtr
);
// Get sleep state right now.
ReadPMIO (FCH_PMIOA_REG62, AccWidthUint16, (VOID*)&AcpiPm1CntBase);
PmCntl = ((IoRead16 (AcpiPm1CntBase) & ~(SLP_EN | SLP_TYPE)) | SUS_S3);
Eflags = EfiGetEflags ();
if ((Eflags & 0x200)) {
EfiDisableInterrupt ();
}
EfiDisableCache ();
// Transform system into S3 sleep state
IoWrite16 (AcpiPm1CntBase, PmCntl);
PmCntl |= SLP_EN;
IoWrite16 (AcpiPm1CntBase, PmCntl);
if ((Eflags & 0x200)) {
EfiEnableInterrupt ();
}
//
// Should not return
//
EFI_DEADLOOP ();
}
/**
Read from IO space
Argv[0] - "ioread"[.#] # is optional width 1, 2, or 4. Default 1
Argv[1] - Hex IO address
ior.4 0x3f8 ;Do a 32-bit IO Read from 0x3f8
ior 0x3f8 ;Do a 8-bit IO Read from 0x3f8
@param Argc Number of command arguments in Argv
@param Argv Array of strings that represent the parsed command line.
Argv[0] is the command name
@return EFI_SUCCESS
**/
EFI_STATUS
EblIoReadCmd (
IN UINTN Argc,
IN CHAR8 **Argv
)
{
UINTN Width;
UINTN Port;
UINTN Data;
if (Argc < 2) {
return EFI_INVALID_PARAMETER;
}
Port = AsciiStrHexToUintn (Argv[1]);
Width = WidthFromCommandName (Argv[0], 1);
if (Width == 1) {
Data = IoRead8 (Port);
} else if (Width == 2) {
Data = IoRead16 (Port);
} else if (Width == 4) {
Data = IoRead32 (Port);
} else {
return EFI_INVALID_PARAMETER;
}
AsciiPrint ("0x%04x = 0x%x", Port, Data);
return EFI_SUCCESS;
}
/**
Reads I/O registers.
The I/O operations are carried out exactly as requested. The caller is
responsible for any alignment and I/O width issues that the bus, device,
platform, or type of I/O might require.
@param[in] This The EFI_SMM_CPU_IO2_PROTOCOL instance.
@param[in] Width Signifies the width of the I/O operations.
@param[in] Address The base address of the I/O operations. The caller is
responsible for aligning the Address if required.
@param[in] Count The number of I/O operations to perform.
@param[out] Buffer For read operations, the destination buffer to store
the results. For write operations, the source buffer
from which to write data.
@retval EFI_SUCCESS The data was read from or written to the device.
@retval EFI_UNSUPPORTED The Address is not valid for this system.
@retval EFI_INVALID_PARAMETER Width or Count, or both, were invalid.
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
lack of resources
**/
EFI_STATUS
EFIAPI
CpuIoServiceRead (
IN CONST EFI_SMM_CPU_IO2_PROTOCOL *This,
IN EFI_SMM_IO_WIDTH Width,
IN UINT64 Address,
IN UINTN Count,
OUT VOID *Buffer
)
{
EFI_STATUS Status;
UINT8 Stride;
UINT8 *Uint8Buffer;
Status = CpuIoCheckParameter (FALSE, Width, Address, Count, Buffer);
if (EFI_ERROR (Status)) {
return Status;
}
//
// Select loop based on the width of the transfer
//
Stride = mStride[Width];
for (Uint8Buffer = Buffer; Count > 0; Address += Stride, Uint8Buffer += Stride, Count--) {
if (Width == SMM_IO_UINT8) {
*Uint8Buffer = IoRead8 ((UINTN)Address);
} else if (Width == SMM_IO_UINT16) {
*((UINT16 *)Uint8Buffer) = IoRead16 ((UINTN)Address);
} else if (Width == SMM_IO_UINT32) {
*((UINT32 *)Uint8Buffer) = IoRead32 ((UINTN)Address);
}
}
return EFI_SUCCESS;
}
EFI_STATUS
EFIAPI
GetWakeupEventAndSaveToHob (
IN CONST EFI_PEI_SERVICES **PeiServices
)
{
UINT16 Pm1Sts;
UINTN Gpe0Sts;
UINTN WakeEventData;
//
// Read the ACPI registers
//
Pm1Sts = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS);
Gpe0Sts = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_GPE0a_STS);
//
// Figure out the wake-up event
//
if ((Pm1Sts & B_PCH_ACPI_PM1_STS_PWRBTN) != 0) {
WakeEventData = SMBIOS_WAKEUP_TYPE_POWER_SWITCH;
} else if (((Pm1Sts & B_PCH_ACPI_PM1_STS_WAK) != 0)) {
WakeEventData = SMBIOS_WAKEUP_TYPE_PCI_PME;
} else if (Gpe0Sts != 0) {
WakeEventData = SMBIOS_WAKEUP_TYPE_OTHERS;
} else {
WakeEventData = SMBIOS_WAKEUP_TYPE_UNKNOWN;
}
DEBUG ((EFI_D_ERROR, "ACPI Wake Status Register: %04x\n", Pm1Sts));
DEBUG ((EFI_D_ERROR, "ACPI Wake Event Data: %02x\n", WakeEventData));
return EFI_SUCCESS;
}
BOOLEAN
GetSleepTypeAfterWakeup (
IN CONST EFI_PEI_SERVICES **PeiServices,
OUT UINT16 *SleepType
)
{
UINT16 Pm1Sts;
UINT16 Pm1Cnt;
UINT16 GenPmCon1;
GenPmCon1 = MmioRead16 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1);
//
// Read the ACPI registers
//
Pm1Sts = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS);
Pm1Cnt = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT);
if ((GenPmCon1 & (B_PCH_PMC_GEN_PMCON_SUS_PWR_FLR | B_PCH_PMC_GEN_PMCON_GEN_RST_STS)) ||
(Pm1Sts & B_PCH_ACPI_PM1_STS_PRBTNOR)) {
//
// If power failure indicator, then don't attempt s3 resume.
// Clear PM1_CNT of S3 and set it to S5 as we just had a power failure, and memory has
// lost already. This is to make sure no one will use PM1_CNT to check for S3 after
// power failure.
//
if ((Pm1Cnt & B_PCH_ACPI_PM1_CNT_SLP_TYP) == V_PCH_ACPI_PM1_CNT_S3) {
Pm1Cnt = ((Pm1Cnt & ~B_PCH_ACPI_PM1_CNT_SLP_TYP) | V_PCH_ACPI_PM1_CNT_S5);
IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT, Pm1Cnt);
}
//
// Clear Wake Status (WAK_STS)
//
IoWrite16 ((ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS), B_PCH_ACPI_PM1_STS_WAK);
}
//
// Get sleep type if a wake event occurred and there is no power failure
//
if ((Pm1Cnt & B_PCH_ACPI_PM1_CNT_SLP_TYP) == V_PCH_ACPI_PM1_CNT_S3) {
*SleepType = Pm1Cnt & B_PCH_ACPI_PM1_CNT_SLP_TYP;
return TRUE;
} else if ((Pm1Cnt & B_PCH_ACPI_PM1_CNT_SLP_TYP) == V_PCH_ACPI_PM1_CNT_S4){
*SleepType = Pm1Cnt & B_PCH_ACPI_PM1_CNT_SLP_TYP;
return TRUE;
}
return FALSE;
}
/**
16-bit I/O read operations.
@param[in] PeiServices An indirect pointer to the PEI Services Table published
by the PEI Foundation.
@param[in] This Pointer to local data for the interface.
@param[in] Address The physical address of the access.
@return A 16-bit value returned from the I/O space.
**/
UINT16
EFIAPI
CpuIoRead16 (
IN CONST EFI_PEI_SERVICES **PeiServices,
IN CONST EFI_PEI_CPU_IO_PPI *This,
IN UINT64 Address
)
{
return IoRead16 ((UINTN)Address);
}
EFI_STATUS
DisableAcpiCallback (
IN EFI_HANDLE DispatchHandle,
IN CONST VOID *DispatchContext,
IN OUT VOID *CommBuffer,
IN OUT UINTN *CommBufferSize
)
/*++
Routine Description:
SMI handler to disable ACPI mode
Dispatched on reads from APM port with value 0xA1
ACPI events are disabled and ACPI event status is cleared.
SCI mode is then disabled.
Clear all ACPI event status and disable all ACPI events
Disable PM sources except power button
Clear status bits
Disable GPE0 sources
Clear status bits
Disable GPE1 sources
Clear status bits
Disable SCI
Arguments:
DispatchHandle - EFI Handle
DispatchContext - Pointer to the EFI_SMM_SW_DISPATCH_CONTEXT
Returns:
Nothing
--*/
{
EFI_STATUS Status;
UINT16 Pm1Cnt;
Status = GetAllQncPmBase (gSmst);
ASSERT_EFI_ERROR (Status);
Pm1Cnt = IoRead16 (mAcpiSmm.QncPmBase + R_QNC_PM1BLK_PM1C);
//
// Disable SCI
//
Pm1Cnt &= ~B_QNC_PM1BLK_PM1C_SCIEN;
IoWrite16 (mAcpiSmm.QncPmBase + R_QNC_PM1BLK_PM1C, Pm1Cnt);
return EFI_SUCCESS;
}
/**
Reads I/O registers.
The I/O operations are carried out exactly as requested. The caller is responsible
for satisfying any alignment and I/O width restrictions that a PI System on a
platform might require. For example on some platforms, width requests of
EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
be handled by the driver.
If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
each of the Count operations that is performed.
If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
incremented for each of the Count operations that is performed. The read or
write operation is performed Count times on the same Address.
If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
incremented for each of the Count operations that is performed. The read or
write operation is performed Count times from the first element of Buffer.
@param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
@param[in] Width Signifies the width of the I/O or Memory operation.
@param[in] Address The base address of the I/O operation.
@param[in] Count The number of I/O operations to perform. The number of
bytes moved is Width size * Count, starting at Address.
@param[out] Buffer For read operations, the destination buffer to store the results.
For write operations, the source buffer from which to write data.
@retval EFI_SUCCESS The data was read from or written to the PI system.
@retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
@retval EFI_INVALID_PARAMETER Buffer is NULL.
@retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
@retval EFI_UNSUPPORTED The address range specified by Address, Width,
and Count is not valid for this PI system.
**/
EFI_STATUS
EFIAPI
CpuIoServiceRead (
IN EFI_CPU_IO2_PROTOCOL *This,
IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
IN UINT64 Address,
IN UINTN Count,
OUT VOID *Buffer
)
{
EFI_STATUS Status;
UINT8 InStride;
UINT8 OutStride;
EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
UINT8 *Uint8Buffer;
Status = CpuIoCheckParameter (FALSE, Width, Address, Count, Buffer);
if (EFI_ERROR (Status)) {
return Status;
}
//
// Select loop based on the width of the transfer
//
InStride = mInStride[Width];
OutStride = mOutStride[Width];
OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
if (OperationWidth == EfiCpuIoWidthUint8) {
*Uint8Buffer = IoRead8 ((UINTN)Address);
} else if (OperationWidth == EfiCpuIoWidthUint16) {
*((UINT16 *)Uint8Buffer) = IoRead16 ((UINTN)Address);
} else if (OperationWidth == EfiCpuIoWidthUint32) {
*((UINT32 *)Uint8Buffer) = IoRead32 ((UINTN)Address);
}
}
return EFI_SUCCESS;
}
VOID
EFIAPI
DisableAcpiCallback (
IN EFI_HANDLE DispatchHandle,
IN EFI_SMM_SW_DISPATCH_CONTEXT *DispatchContext
)
{
UINT16 Pm1Cnt;
IoWrite16(mAcpiBaseAddr + R_PCH_ACPI_PM1_STS, 0xffff);
IoWrite16(mAcpiBaseAddr + R_PCH_ACPI_PM1_EN, mPM1_SaveState16);
IoWrite32(mAcpiBaseAddr + R_PCH_ACPI_GPE0a_STS, 0xffffffff);
IoWrite32(mAcpiBaseAddr + R_PCH_ACPI_GPE0a_EN, mGPE_SaveState32);
//
// Disable SCI
//
Pm1Cnt = IoRead16(mAcpiBaseAddr + R_PCH_ACPI_PM1_CNT);
Pm1Cnt &= ~B_PCH_ACPI_PM1_CNT_SCI_EN;
IoWrite16(mAcpiBaseAddr + R_PCH_ACPI_PM1_CNT, Pm1Cnt);
}
/**
Reads I/O registers.
@param[in] PeiServices An indirect pointer to the PEI Services Table
published by the PEI Foundation.
@param[in] This Pointer to local data for the interface.
@param[in] Width The width of the access. Enumerated in bytes.
@param[in] Address The physical address of the access.
@param[in] Count The number of accesses to perform.
@param[out] Buffer A pointer to the buffer of data.
@retval EFI_SUCCESS The function completed successfully.
@retval EFI_INVALID_PARAMETER Width is invalid for this EFI system.
@retval EFI_INVALID_PARAMETER Buffer is NULL.
@retval EFI_UNSUPPORTED The address range specified by Address, Width,
and Count is not valid for this EFI system.
**/
EFI_STATUS
EFIAPI
CpuIoServiceRead (
IN CONST EFI_PEI_SERVICES **PeiServices,
IN CONST EFI_PEI_CPU_IO_PPI *This,
IN EFI_PEI_CPU_IO_PPI_WIDTH Width,
IN UINT64 Address,
IN UINTN Count,
OUT VOID *Buffer
)
{
EFI_STATUS Status;
UINT8 InStride;
UINT8 OutStride;
EFI_PEI_CPU_IO_PPI_WIDTH OperationWidth;
BOOLEAN Aligned;
UINT8 *Uint8Buffer;
Status = CpuIoCheckParameter (FALSE, Width, Address, Count, Buffer);
if (EFI_ERROR (Status)) {
return Status;
}
//
// Select loop based on the width of the transfer
//
InStride = mInStride[Width];
OutStride = mOutStride[Width];
OperationWidth = (EFI_PEI_CPU_IO_PPI_WIDTH) (Width & 0x03);
//
// Fifo operations supported for (mInStride[Width] == 0)
//
if (InStride == 0) {
switch (OperationWidth) {
case EfiPeiCpuIoWidthUint8:
IoReadFifo8 ((UINTN)Address, Count, Buffer);
return EFI_SUCCESS;
case EfiPeiCpuIoWidthUint16:
IoReadFifo16 ((UINTN)Address, Count, Buffer);
return EFI_SUCCESS;
case EfiPeiCpuIoWidthUint32:
IoReadFifo32 ((UINTN)Address, Count, Buffer);
return EFI_SUCCESS;
default:
//
// The CpuIoCheckParameter call above will ensure that this
// path is not taken.
//
ASSERT (FALSE);
break;
}
}
Aligned = (BOOLEAN)(((UINTN)Buffer & (mInStride[OperationWidth] - 1)) == 0x00);
for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
if (OperationWidth == EfiPeiCpuIoWidthUint8) {
*Uint8Buffer = IoRead8 ((UINTN)Address);
} else if (OperationWidth == EfiPeiCpuIoWidthUint16) {
if (Aligned) {
*((UINT16 *)Uint8Buffer) = IoRead16 ((UINTN)Address);
} else {
WriteUnaligned16 ((UINT16 *)Uint8Buffer, IoRead16 ((UINTN)Address));
}
} else if (OperationWidth == EfiPeiCpuIoWidthUint32) {
if (Aligned) {
*((UINT32 *)Uint8Buffer) = IoRead32 ((UINTN)Address);
} else {
WriteUnaligned32 ((UINT32 *)Uint8Buffer, IoRead32 ((UINTN)Address));
}
}
}
return EFI_SUCCESS;
}
VOID
EFIAPI
EnableAcpiCallback (
IN EFI_HANDLE DispatchHandle,
IN EFI_SMM_SW_DISPATCH_CONTEXT *DispatchContext
)
{
UINT32 SmiEn;
UINT16 Pm1Cnt;
UINT16 wordValue;
UINT32 RegData32;
//
// Disable SW SMI Timer
//
SmiEn = IoRead32(mAcpiBaseAddr + R_PCH_SMI_EN);
SmiEn &= ~B_PCH_SMI_STS_SWSMI_TMR;
IoWrite32(mAcpiBaseAddr + R_PCH_SMI_EN, SmiEn);
wordValue = IoRead16(mAcpiBaseAddr + R_PCH_ACPI_PM1_STS);
if(wordValue & B_PCH_ACPI_PM1_STS_WAK) {
IoWrite32((mAcpiBaseAddr + R_PCH_ACPI_GPE0a_EN), 0x0000);
IoWrite32((mAcpiBaseAddr + R_PCH_ACPI_GPE0a_STS), 0xffffffff);
}
else {
mPM1_SaveState16 = IoRead16(mAcpiBaseAddr + R_PCH_ACPI_PM1_EN);
//
// Disable PM sources except power button
//
// power button is enabled only for PCAT. Disabled it on Tablet platform
//
IoWrite16(mAcpiBaseAddr + R_PCH_ACPI_PM1_EN, B_PCH_ACPI_PM1_EN_PWRBTN);
IoWrite16(mAcpiBaseAddr + R_PCH_ACPI_PM1_STS, 0xffff);
mGPE_SaveState32 = IoRead16(mAcpiBaseAddr + R_PCH_ACPI_GPE0a_EN);
IoWrite32(mAcpiBaseAddr + R_PCH_ACPI_GPE0a_EN, 0x0000);
IoWrite32(mAcpiBaseAddr + R_PCH_ACPI_GPE0a_STS, 0xffffffff);
}
//
// Guarantee day-of-month alarm is invalid (ACPI 5.0 Section 4.8.2.4 "Real Time Clock Alarm")
// Clear Status D reg VM bit, Date of month Alarm to make Data in CMOS RAM is no longer Valid
//
IoWrite8 (PCAT_RTC_ADDRESS_REGISTER, RTC_ADDRESS_REGISTER_D);
IoWrite8 (PCAT_RTC_DATA_REGISTER, 0x0);
RegData32 = IoRead32(ACPI_BASE_ADDRESS + R_PCH_ALT_GP_SMI_EN);
RegData32 &= ~(BIT7);
IoWrite32((ACPI_BASE_ADDRESS + R_PCH_ALT_GP_SMI_EN), RegData32);
//
// Enable SCI
//
Pm1Cnt = IoRead16(mAcpiBaseAddr + R_PCH_ACPI_PM1_CNT);
Pm1Cnt |= B_PCH_ACPI_PM1_CNT_SCI_EN;
IoWrite16(mAcpiBaseAddr + R_PCH_ACPI_PM1_CNT, Pm1Cnt);
}
/**
Calling this function causes the system to enter a power state for capsule
update.
Reset update should not return, if it returns, it means the system does
not support capsule update.
**/
VOID
EFIAPI
EnterS3WithImmediateWake (
VOID
)
{
UINT8 Data8;
UINT16 Data16;
UINT32 Data32;
UINTN Eflags;
UINTN RegCr0;
EFI_TIME EfiTime;
UINT32 SmiEnSave;
Eflags = AsmReadEflags ();
if ( (Eflags & 0x200) ) {
DisableInterrupts ();
}
//
// Write all cache data to memory because processor will lost power
//
AsmWbinvd();
RegCr0 = AsmReadCr0();
AsmWriteCr0 (RegCr0 | 0x060000000);
SmiEnSave = QNCPortRead (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QNC_MSG_FSBIC_REG_HMISC);
QNCPortWrite (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QNC_MSG_FSBIC_REG_HMISC, (SmiEnSave & ~SMI_EN));
//
// Pogram RTC alarm for immediate WAKE
//
//
// Disable SMI sources
//
IoWrite16 (PcdGet16 (PcdGpe0blkIoBaseAddress) + R_QNC_GPE0BLK_SMIE, 0);
//
// Disable RTC alarm interrupt
//
IoWrite8 (PCAT_RTC_ADDRESS_REGISTER, RTC_ADDRESS_REGISTER_B);
Data8 = IoRead8 (PCAT_RTC_DATA_REGISTER);
IoWrite8 (PCAT_RTC_DATA_REGISTER, (Data8 & ~BIT5));
//
// Clear RTC alarm if already set
//
IoWrite8 (PCAT_RTC_ADDRESS_REGISTER, RTC_ADDRESS_REGISTER_C);
Data8 = IoRead8 (PCAT_RTC_DATA_REGISTER); // Read clears alarm status
//
// Disable all WAKE events
//
IoWrite16 (PcdGet16 (PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1E, B_QNC_PM1BLK_PM1E_PWAKED);
//
// Clear all WAKE status bits
//
IoWrite16 (PcdGet16 (PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1S, B_QNC_PM1BLK_PM1S_ALL);
//
// Avoid RTC rollover
//
do {
WaitForRTCUpdate();
IoWrite8 (PCAT_RTC_ADDRESS_REGISTER, RTC_ADDRESS_SECONDS);
EfiTime.Second = IoRead8 (PCAT_RTC_DATA_REGISTER);
} while (EfiTime.Second > PLATFORM_RTC_ROLLOVER_LIMIT);
//
// Read RTC time
//
IoWrite8 (PCAT_RTC_ADDRESS_REGISTER, RTC_ADDRESS_HOURS);
EfiTime.Hour = IoRead8 (PCAT_RTC_DATA_REGISTER);
IoWrite8 (PCAT_RTC_ADDRESS_REGISTER, RTC_ADDRESS_MINUTES);
EfiTime.Minute = IoRead8 (PCAT_RTC_DATA_REGISTER);
IoWrite8 (PCAT_RTC_ADDRESS_REGISTER, RTC_ADDRESS_SECONDS);
EfiTime.Second = IoRead8 (PCAT_RTC_DATA_REGISTER);
//
// Set RTC alarm
//
//
// Add PLATFORM_WAKE_SECONDS_BUFFER to current EfiTime.Second
// The maths is to allow for the fact we are adding to a BCD number and require the answer to be BCD (EfiTime.Second)
//
if ((BCD_BASE - (EfiTime.Second & 0x0F)) <= PLATFORM_WAKE_SECONDS_BUFFER) {
Data8 = (((EfiTime.Second & 0xF0) + 0x10) + (PLATFORM_WAKE_SECONDS_BUFFER - (BCD_BASE - (EfiTime.Second & 0x0F))));
} else {
Data8 = EfiTime.Second + PLATFORM_WAKE_SECONDS_BUFFER;
}
IoWrite8 (PCAT_RTC_ADDRESS_REGISTER, RTC_ADDRESS_HOURS_ALARM);
IoWrite8 (PCAT_RTC_DATA_REGISTER, EfiTime.Hour);
IoWrite8 (PCAT_RTC_ADDRESS_REGISTER, RTC_ADDRESS_MINUTES_ALARM);
IoWrite8 (PCAT_RTC_DATA_REGISTER, EfiTime.Minute);
IoWrite8 (PCAT_RTC_ADDRESS_REGISTER, RTC_ADDRESS_SECONDS_ALARM);
IoWrite8 (PCAT_RTC_DATA_REGISTER, Data8);
//
// Enable RTC alarm interrupt
//
IoWrite8 (PCAT_RTC_ADDRESS_REGISTER, RTC_ADDRESS_REGISTER_B);
Data8 = IoRead8 (PCAT_RTC_DATA_REGISTER);
IoWrite8 (PCAT_RTC_DATA_REGISTER, (Data8 | BIT5));
//
// Enable RTC alarm as WAKE event
//
Data16 = IoRead16 (PcdGet16 (PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1E);
IoWrite16 (PcdGet16 (PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1E, (Data16 | B_QNC_PM1BLK_PM1E_RTC));
//
// Enter S3
//
Data32 = IoRead32 (PcdGet16 (PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1C);
Data32 = (UINT32) ((Data32 & 0xffffc3fe) | V_S3 | B_QNC_PM1BLK_PM1C_SCIEN);
IoWrite32 (PcdGet16 (PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1C, Data32);
Data32 = Data32 | B_QNC_PM1BLK_PM1C_SLPEN;
IoWrite32 (PcdGet16 (PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1C, Data32);
//
// Enable Interrupt if it's enabled before
//
if ( (Eflags & 0x200) ) {
EnableInterrupts ();
}
}
VOID
EnableS5WakeOnRtc()
{
UINT8 CmosData;
UINTN i;
EFI_STATUS Status;
UINTN VarSize;
//
// make sure EFI_SMM_VARIABLE_PROTOCOL is available
//
if (!mSmmVariable) {
return;
}
VarSize = sizeof(SYSTEM_CONFIGURATION);
//
// read the variable into the buffer
//
Status = mSmmVariable->SmmGetVariable(
L"Setup",
&gEfiSetupVariableGuid,
NULL,
&VarSize,
&mSystemConfiguration
);
if (EFI_ERROR(Status) || VarSize != sizeof(SYSTEM_CONFIGURATION)) {
//The setup variable is corrupted
VarSize = sizeof(SYSTEM_CONFIGURATION);
Status = mSmmVariable->SmmGetVariable(
L"SetupRecovery",
&gEfiSetupVariableGuid,
NULL,
&VarSize,
&mSystemConfiguration
);
ASSERT_EFI_ERROR (Status);
}
if (!mSystemConfiguration.WakeOnRtcS5) {
return;
}
mWakeupDay = HexToBcd((UINT8)mSystemConfiguration.RTCWakeupDate);
mWakeupHour = HexToBcd((UINT8)mSystemConfiguration.RTCWakeupTimeHour);
mWakeupMinute = HexToBcd((UINT8)mSystemConfiguration.RTCWakeupTimeMinute);
mWakeupSecond = HexToBcd((UINT8)mSystemConfiguration.RTCWakeupTimeSecond);
//
// Check RTC alarm interrupt is enabled. If enabled, someone already
// grabbed RTC alarm. Just return.
//
IoWrite8(PCAT_RTC_ADDRESS_REGISTER, RTC_ADDRESS_REGISTER_B);
if(IoRead8(PCAT_RTC_DATA_REGISTER) & B_RTC_ALARM_INT_ENABLE){
return;
}
//
// Set Date
//
IoWrite8(PCAT_RTC_ADDRESS_REGISTER, RTC_ADDRESS_REGISTER_D);
CmosData = IoRead8(PCAT_RTC_DATA_REGISTER);
CmosData &= ~(B_RTC_DATE_ALARM_MASK);
CmosData |= mWakeupDay ;
for(i = 0 ; i < 0xffff ; i++){
IoWrite8(PCAT_RTC_DATA_REGISTER, CmosData);
SmmStall(1);
if(((CmosData = IoRead8(PCAT_RTC_DATA_REGISTER)) & B_RTC_DATE_ALARM_MASK)
== mWakeupDay){
break;
}
}
//
// Set Second
//
IoWrite8(PCAT_RTC_ADDRESS_REGISTER, RTC_ADDRESS_SECOND_ALARM);
for(i = 0 ; i < 0xffff ; i++){
IoWrite8(PCAT_RTC_DATA_REGISTER, mWakeupSecond);
SmmStall(1);
if(IoRead8(PCAT_RTC_DATA_REGISTER) == mWakeupSecond){
break;
}
}
//
// Set Minute
//
IoWrite8(PCAT_RTC_ADDRESS_REGISTER, RTC_ADDRESS_MINUTE_ALARM);
for(i = 0 ; i < 0xffff ; i++){
IoWrite8(PCAT_RTC_DATA_REGISTER, mWakeupMinute);
SmmStall(1);
if(IoRead8(PCAT_RTC_DATA_REGISTER) == mWakeupMinute){
break;
}
}
//
// Set Hour
//
IoWrite8(PCAT_RTC_ADDRESS_REGISTER, RTC_ADDRESS_HOUR_ALARM);
for(i = 0 ; i < 0xffff ; i++){
IoWrite8(PCAT_RTC_DATA_REGISTER, mWakeupHour);
SmmStall(1);
if(IoRead8(PCAT_RTC_DATA_REGISTER) == mWakeupHour){
break;
}
}
//
// Wait for UIP to arm RTC alarm
//
IoWrite8(PCAT_RTC_ADDRESS_REGISTER, RTC_ADDRESS_REGISTER_A);
while (IoRead8(PCAT_RTC_DATA_REGISTER) & 0x80);
//
// Read RTC register 0C to clear pending RTC interrupts
//
IoWrite8(PCAT_RTC_ADDRESS_REGISTER, RTC_ADDRESS_REGISTER_C);
IoRead8(PCAT_RTC_DATA_REGISTER);
//
// Enable RTC Alarm Interrupt
//
IoWrite8(PCAT_RTC_ADDRESS_REGISTER, RTC_ADDRESS_REGISTER_B);
IoWrite8(PCAT_RTC_DATA_REGISTER, IoRead8(PCAT_RTC_DATA_REGISTER) | B_RTC_ALARM_INT_ENABLE);
//
// Clear ICH RTC Status
//
IoWrite16(mAcpiBaseAddr + R_PCH_ACPI_PM1_STS, B_PCH_ACPI_PM1_STS_RTC);
//
// Enable ICH RTC event
//
IoWrite16(mAcpiBaseAddr + R_PCH_ACPI_PM1_EN,
(UINT16)(IoRead16(mAcpiBaseAddr + R_PCH_ACPI_PM1_EN) | B_PCH_ACPI_PM1_EN_RTC));
}
EFI_STATUS
SaveRuntimeScriptTable (
VOID
)
{
SMM_PCI_IO_ADDRESS PciAddress;
UINT32 Data32;
UINT16 Data16;
UINT8 Data8;
UINT8 Mask;
UINTN Index;
UINTN Offset;
UINT8 RegTable[] = {
//
//Bus , Dev, Func, DMI
//
0x00 , 0x00, 0x00,
//
//00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
//
0x00 , 0x08, 0x00, 0x00, 0x30, 0x00, 0x00, 0xa0,
//
//Bus , Dev, Func, LPC device
//
0x00 , 0x1F, 0x00,
//
//00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
//
0x00 , 0x08, 0x00, 0x07, 0x00, 0x00, 0x90, 0x00,
//
//Bus , Dev, Func, PCIE device
//
0x00 , 0x1C, 0x00,
//
//00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
//
0xC0 , 0x83, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00,
//
//Bus , Dev, Func, PCIE device
//
0x00 , 0x1C, 0x00,
//
//00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
//
0x03 , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
//
//Bus , Dev, Func, SATA device
//
0x00 , 0x13, 0x00,
//
//00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
//
0xf4 , 0xab, 0x27, 0x10, 0xf1, 0x1d, 0x00, 0x40,
//
//Bus , Dev, Func, EHCI device
//
0x00 , 0x1D, 0x00,
//
//00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
//
0x10 , 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
//
//Bus , Dev, Func, SMBUS device
//
0x00 , 0x1f, 0x03,
//
//00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
//
0x10 , 0x89, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
//
//Bus , Dev, Func, SMBUS device
//
0x00 , 0x1f, 0x03,
//
//00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
//
0x02 , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
//
//Bus , Dev, Func, VGA bus1
//
0x01 , 0x00, 0x00,
//
//00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
//
0x58 , 0x81, 0x18, 0x01, 0xb0, 0x00, 0x00, 0x00,
//
//Bus , Dev, Func, VGA bus1
//
0x01 , 0x00, 0x00,
//
//00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
//
0x02 , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
//
//Bus , Dev, Func, VGA bus1 function 1
//
0x01 , 0x00, 0x01,
//
//00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
//
0x51 , 0x80, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00,
//
//Bus , Dev, Func, VGA bus1 function 1
//
0x01 , 0x00, 0x01,
//
//00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
//
0x02 , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
//
//Bus , Dev, Func, IGD bus0 function 0
//
0x00 , 0x02, 0x00,
//
//00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
//
0x42 , 0x81, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00,
//
//Bus , Dev, Func, USB bus0 function 0
//
0x00 , 0x16, 0x00,
//
//00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
//
0x32 , 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
//
//Bus , Dev, Func, HD Audio bus0 function 0
//
0x00 , 0x1B, 0x00,
//
//00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
//
0x00 , 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
//
//0xFF indicates the end of the table
//
0xFF
};
//
// These registers have to set in byte order
//
UINT8 ExtReg[] = { 0x9E, 0x9D }; // SMRAM settings
//
// Save PCI-Host bridge settings (0, 0, 0). 0x90, 94 and 9c are changed by CSM
// and vital to S3 resume. That's why we put save code here
//
PciAddress.Bus = 0;
PciAddress.Device = 0;
PciAddress.Function = 0;
PciAddress.ExtendedRegister = 0;
for (Index = 0; Index < 2; Index++) {
//
// Read SRAM setting from Pci(0, 0, 0)
//
PciAddress.Register = ExtReg[Index];
Data8 = MmioRead8 (
MmPciAddress (0,
PciAddress.Bus,
PciAddress.Device,
PciAddress.Function,
PciAddress.Register
)
);
//
// Save latest settings to runtime script table
//
S3BootScriptSavePciCfgWrite(
S3BootScriptWidthUint8,
*(UINT64*)&PciAddress,
1,
&Data8
);
}
//
// Save PCI-Host bridge settings (0, 0, 0). 0x90, 94 and 9c are changed by CSM
// and vital to S3 resume. That's why we put save code here
//
Index = 0;
while (RegTable[Index] != 0xFF) {
PciAddress.Bus = RegTable[Index++];
PciAddress.Device = RegTable[Index++];
PciAddress.Function = RegTable[Index++];
PciAddress.Register = 0;
PciAddress.ExtendedRegister = 0;
Data16 = MmioRead16 (
MmPciAddress (0,
PciAddress.Bus,
PciAddress.Device,
PciAddress.Function,
PciAddress.Register
)
);
if (Data16 == 0xFFFF) {
Index+=8;
continue;
}
for (Offset = 0, Mask = 0x01; Offset < 256; Offset+=4, Mask<<=1) {
if (Mask == 0x00) {
Mask = 0x01;
}
if (RegTable[Index + Offset/32] & Mask ) {
PciAddress.Register = (UINT8)Offset;
Data32 = MmioRead32 (MmPciAddress (0, PciAddress.Bus, PciAddress.Device, PciAddress.Function, PciAddress.Register));
//
// Save latest settings to runtime script table
//
S3BootScriptSavePciCfgWrite (
S3BootScriptWidthUint32,
*(UINT64*)&PciAddress,
1,
&Data32
);
}
}
Index += 8;
}
//
// Save I/O ports to S3 script table
//
//
// Selftest KBC
//
Data8 = 0xAA;
S3BootScriptSaveIoWrite (
S3BootScriptWidthUint8,
0x64,
(UINTN)1,
&Data8
);
Data32 = IoRead32(mAcpiBaseAddr + R_PCH_SMI_EN);
S3BootScriptSaveIoWrite (
S3BootScriptWidthUint32,
(mAcpiBaseAddr + R_PCH_SMI_EN),
1,
&Data32
);
//
// Save B_ICH_TCO_CNT_LOCK so it will be done on S3 resume path.
//
Data16 = IoRead16(mAcpiBaseAddr + R_PCH_TCO_CNT);
S3BootScriptSaveIoWrite (
S3BootScriptWidthUint16,
mAcpiBaseAddr + R_PCH_TCO_CNT,
1,
&Data16
);
return EFI_SUCCESS;
}
// ------------------------------------------------------------------------------------------------
uint16 PciRead16(uint32 id, uint32 reg)
{
uint32 addr = 0x80000000 | id | (reg & 0xfc);
IoWrite32(PCI_CONFIG_ADDR, addr);
return IoRead16(PCI_CONFIG_DATA + (reg & 0x02));
}
/**
This function is IO instruction handler.
@param Index CPU index
**/
VOID
IoHandler (
IN UINT32 Index
)
{
VM_EXIT_QUALIFICATION Qualification;
UINT16 Port;
UINTN *DataPtr;
IO_WRITE_HANDLER_ITEM *IoWriteHandler;
IO_READ_HANDLER_ITEM *IoReadHandler;
UINT32 Action;
UINT32 Value;
UINTN LinearAddr;
Qualification.UintN = VmReadN (VMCS_N_RO_EXIT_QUALIFICATION_INDEX);
Port = (UINT16)Qualification.IoInstruction.PortNum;
DataPtr = (UINTN *)&mGuestContextCommon.GuestContextPerCpu[Index].Register.Rax;
if (Qualification.IoInstruction.Rep) {
UINT64 RcxMask;
RcxMask = 0xFFFFFFFFFFFFFFFFull;
if ((mGuestContextCommon.GuestContextPerCpu[Index].EFER & IA32_EFER_MSR_MLA) == 0) {
RcxMask = 0xFFFFFFFFull;
}
if ((mGuestContextCommon.GuestContextPerCpu[Index].Register.Rcx & RcxMask) == 0) {
// Skip
VmWriteN (VMCS_N_GUEST_RIP_INDEX, VmReadN(VMCS_N_GUEST_RIP_INDEX) + VmRead32(VMCS_32_RO_VMEXIT_INSTRUCTION_LENGTH_INDEX));
return ;
}
}
if (Port == 0xB2) {
DEBUG ((EFI_D_INFO, "(FRM) !!! SmiCmd(0xb2) - 0x%02x !!!\n", (UINT8)*DataPtr));
}
if ((mHostContextCommon.ResetIoPortBaseAddress != 0) && (Port == mHostContextCommon.ResetIoPortBaseAddress) && (Qualification.IoInstruction.Direction == 0)) {
IoResetHandler (Index, Port, (UINT8)*DataPtr);
} else if ((Port == mHostContextCommon.AcpiPmControlIoPortBaseAddress) && (Qualification.IoInstruction.Direction == 0)) {
IoAcpiHandler (Index, Port, (UINT32)*DataPtr);
}
if (Qualification.IoInstruction.String) {
LinearAddr = VmReadN (VMCS_N_RO_GUEST_LINEAR_ADDR_INDEX);
if (VmReadN (VMCS_N_GUEST_CR0_INDEX) & CR0_PG) {
DataPtr = (UINTN *)(UINTN)GuestVirtualToGuestPhysical (Index, LinearAddr);
} else {
DataPtr = (UINTN *)LinearAddr;
}
if (VmReadN (VMCS_N_GUEST_RFLAGS_INDEX) & RFLAGS_DF) {
if (Qualification.IoInstruction.Direction) {
mGuestContextCommon.GuestContextPerCpu[Index].Register.Rdi -= Qualification.IoInstruction.Size + 1;
} else {
mGuestContextCommon.GuestContextPerCpu[Index].Register.Rsi -= Qualification.IoInstruction.Size + 1;
}
} else {
if (Qualification.IoInstruction.Direction) {
mGuestContextCommon.GuestContextPerCpu[Index].Register.Rdi += Qualification.IoInstruction.Size + 1;
} else {
mGuestContextCommon.GuestContextPerCpu[Index].Register.Rsi += Qualification.IoInstruction.Size + 1;
}
}
}
if (Qualification.IoInstruction.Direction) { // IN
IoReadHandler = FindIoReadHandler (Port, Qualification.IoInstruction.Size + 1);
if (IoReadHandler != NULL) {
Action = IO_ACTION_NO_ACTION;
Value = 0;
IoReadHandler->Handler (IoReadHandler->Context, Port, &Value, &Action);
if (Action == IO_ACTION_NO_ACTION) {
switch (Qualification.IoInstruction.Size) {
case 0:
*(UINT8 *)DataPtr = (UINT8)Value;
goto Ret;
break;
case 1:
*(UINT16 *)DataPtr = (UINT16)Value;
goto Ret;
break;
case 3:
*(UINT32 *)DataPtr = Value;
goto Ret;
break;
default:
break;
}
goto Ret;
} else {
// Passthrough
}
}
switch (Qualification.IoInstruction.Size) {
case 0:
*(UINT8 *)DataPtr = IoRead8 (Port);
goto Ret;
break;
case 1:
*(UINT16 *)DataPtr = IoRead16 (Port);
goto Ret;
break;
case 3:
*(UINT32 *)DataPtr = IoRead32 (Port);
goto Ret;
break;
default:
break;
}
} else { // OUT
IoWriteHandler = FindIoWriteHandler (Port, Qualification.IoInstruction.Size + 1);
if (IoWriteHandler != NULL) {
Action = IO_ACTION_NO_ACTION;
Value = (UINT32)*DataPtr;
IoWriteHandler->Handler (IoWriteHandler->Context, Port, Value, &Action);
if (Action == IO_ACTION_NO_ACTION) {
goto Ret;
} else {
// Passthrough
}
}
switch (Qualification.IoInstruction.Size) {
case 0:
IoWrite8 (Port, (UINT8)*DataPtr);
goto Ret;
break;
case 1:
IoWrite16 (Port, (UINT16)*DataPtr);
goto Ret;
break;
case 3:
IoWrite32 (Port, (UINT32)*DataPtr);
goto Ret;
break;
default:
break;
}
}
DEBUG ((EFI_D_ERROR, "(FRM) !!!IoHandler!!!\n"));
DumpVmcsAllField ();
CpuDeadLoop ();
Ret:
if (Qualification.IoInstruction.Rep) {
// replay
mGuestContextCommon.GuestContextPerCpu[Index].Register.Rcx --;
return ;
}
VmWriteN (VMCS_N_GUEST_RIP_INDEX, VmReadN(VMCS_N_GUEST_RIP_INDEX) + VmRead32(VMCS_32_RO_VMEXIT_INSTRUCTION_LENGTH_INDEX));
return ;
}
EFI_STATUS
EFIAPI
InitializePlatformSmm (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
UINT8 Index;
EFI_HANDLE Handle;
EFI_SMM_POWER_BUTTON_DISPATCH_CONTEXT PowerButtonContext;
EFI_SMM_POWER_BUTTON_DISPATCH_PROTOCOL *PowerButtonDispatch;
EFI_SMM_ICHN_DISPATCH_CONTEXT IchnContext;
EFI_SMM_ICHN_DISPATCH_PROTOCOL *IchnDispatch;
EFI_SMM_SX_DISPATCH_PROTOCOL *SxDispatch;
EFI_SMM_SX_DISPATCH_CONTEXT EntryDispatchContext;
EFI_SMM_SW_DISPATCH_PROTOCOL *SwDispatch;
EFI_SMM_SW_DISPATCH_CONTEXT SwContext;
UINTN VarSize;
EFI_BOOT_MODE BootMode;
Handle = NULL;
//
// Locate the Global NVS Protocol.
//
Status = gBS->LocateProtocol (
&gEfiGlobalNvsAreaProtocolGuid,
NULL,
(void **)&mGlobalNvsAreaPtr
);
ASSERT_EFI_ERROR (Status);
//
// Get the ACPI Base Address
//
mAcpiBaseAddr = PchLpcPciCfg16( R_PCH_LPC_ACPI_BASE ) & B_PCH_LPC_ACPI_BASE_BAR;
VarSize = sizeof(SYSTEM_CONFIGURATION);
Status = SystemTable->RuntimeServices->GetVariable(
L"Setup",
&gEfiSetupVariableGuid,
NULL,
&VarSize,
&mSystemConfiguration
);
if (EFI_ERROR (Status) || VarSize != sizeof(SYSTEM_CONFIGURATION)) {
//The setup variable is corrupted
VarSize = sizeof(SYSTEM_CONFIGURATION);
Status = SystemTable->RuntimeServices->GetVariable(
L"SetupRecovery",
&gEfiSetupVariableGuid,
NULL,
&VarSize,
&mSystemConfiguration
);
ASSERT_EFI_ERROR (Status);
}
if (!EFI_ERROR(Status)) {
mAcLossVariable = mSystemConfiguration.StateAfterG3;
//
// If LAN is disabled, WOL function should be disabled too.
//
if (mSystemConfiguration.Lan == 0x01){
mWakeOnLanS5Variable = mSystemConfiguration.WakeOnLanS5;
} else {
mWakeOnLanS5Variable = FALSE;
}
mWakeOnRtcVariable = mSystemConfiguration.WakeOnRtcS5;
}
BootMode = GetBootModeHob ();
//
// Get the Power Button protocol
//
Status = gBS->LocateProtocol(
&gEfiSmmPowerButtonDispatchProtocolGuid,
NULL,
(void **)&PowerButtonDispatch
);
ASSERT_EFI_ERROR(Status);
if (BootMode != BOOT_ON_FLASH_UPDATE) {
//
// Register for the power button event
//
PowerButtonContext.Phase = PowerButtonEntry;
Status = PowerButtonDispatch->Register(
PowerButtonDispatch,
PowerButtonCallback,
&PowerButtonContext,
&Handle
);
ASSERT_EFI_ERROR(Status);
}
//
// Get the Sx dispatch protocol
//
Status = gBS->LocateProtocol (
&gEfiSmmSxDispatchProtocolGuid,
NULL,
(void **)&SxDispatch
);
ASSERT_EFI_ERROR(Status);
//
// Register entry phase call back function
//
EntryDispatchContext.Type = SxS3;
EntryDispatchContext.Phase = SxEntry;
Status = SxDispatch->Register (
SxDispatch,
(EFI_SMM_SX_DISPATCH)SxSleepEntryCallBack,
&EntryDispatchContext,
&Handle
);
EntryDispatchContext.Type = SxS4;
Status = SxDispatch->Register (
SxDispatch,
S4S5CallBack,
&EntryDispatchContext,
&Handle
);
ASSERT_EFI_ERROR(Status);
EntryDispatchContext.Type = SxS5;
Status = SxDispatch->Register (
SxDispatch,
S4S5CallBack,
&EntryDispatchContext,
&Handle
);
ASSERT_EFI_ERROR(Status);
Status = SxDispatch->Register (
SxDispatch,
S5SleepAcLossCallBack,
&EntryDispatchContext,
&Handle
);
ASSERT_EFI_ERROR(Status);
//
// Get the Sw dispatch protocol
//
Status = gBS->LocateProtocol (
&gEfiSmmSwDispatchProtocolGuid,
NULL,
(void **)&SwDispatch
);
ASSERT_EFI_ERROR(Status);
//
// Register ACPI enable handler
//
SwContext.SwSmiInputValue = ACPI_ENABLE;
Status = SwDispatch->Register (
SwDispatch,
EnableAcpiCallback,
&SwContext,
&Handle
);
ASSERT_EFI_ERROR(Status);
//
// Register ACPI disable handler
//
SwContext.SwSmiInputValue = ACPI_DISABLE;
Status = SwDispatch->Register (
SwDispatch,
DisableAcpiCallback,
&SwContext,
&Handle
);
ASSERT_EFI_ERROR(Status);
//
// Register for SmmReadyToBootCallback
//
SwContext.SwSmiInputValue = SMI_SET_SMMVARIABLE_PROTOCOL;
Status = SwDispatch->Register(
SwDispatch,
SmmReadyToBootCallback,
&SwContext,
&Handle
);
ASSERT_EFI_ERROR(Status);
//
// Get the ICHn protocol
//
Status = gBS->LocateProtocol(
&gEfiSmmIchnDispatchProtocolGuid,
NULL,
(void **)&IchnDispatch
);
ASSERT_EFI_ERROR(Status);
//
// Register for the events that may happen that we do not care.
// This is true for SMI related to TCO since TCO is enabled by BIOS WP
//
for (Index = 0; Index < sizeof(mTco1Sources)/sizeof(UINT8); Index++) {
IchnContext.Type = mTco1Sources[Index];
Status = IchnDispatch->Register(
IchnDispatch,
(EFI_SMM_ICHN_DISPATCH)DummyTco1Callback,
&IchnContext,
&Handle
);
ASSERT_EFI_ERROR( Status );
}
//
// Lock TCO_EN bit.
//
IoWrite16( mAcpiBaseAddr + R_PCH_TCO_CNT, IoRead16( mAcpiBaseAddr + R_PCH_TCO_CNT ) | B_PCH_TCO_CNT_LOCK );
//
// Set to power on from G3 dependent on WOL instead of AC Loss variable in order to support WOL from G3 feature.
//
//
// Set wake from G3 dependent on AC Loss variable and Wake On LAN variable.
// This is because no matter how, if WOL enabled or AC Loss variable not disabled, the board needs to wake from G3 to program the LAN WOL settings.
// This needs to be done after LAN enable/disable so that the PWR_FLR state clear not impacted the WOL from G3 feature.
//
if (mAcLossVariable != 0x00) {
SetAfterG3On (TRUE);
} else {
SetAfterG3On (FALSE);
}
return EFI_SUCCESS;
}
EFI_STATUS
EnableAcpiCallback (
IN EFI_HANDLE DispatchHandle,
IN CONST VOID *DispatchContext,
IN OUT VOID *CommBuffer,
IN OUT UINTN *CommBufferSize
)
/*++
Routine Description:
SMI handler to enable ACPI mode
Dispatched on reads from APM port with value 0xA0
Disables the SW SMI Timer.
ACPI events are disabled and ACPI event status is cleared.
SCI mode is then enabled.
Disable SW SMI Timer
Clear all ACPI event status and disable all ACPI events
Disable PM sources except power button
Clear status bits
Disable GPE0 sources
Clear status bits
Disable GPE1 sources
Clear status bits
Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)
Enable SCI
Arguments:
DispatchHandle - EFI Handle
DispatchContext - Pointer to the EFI_SMM_SW_DISPATCH_CONTEXT
Returns:
Nothing
--*/
{
EFI_STATUS Status;
UINT32 SmiEn;
UINT16 Pm1Cnt;
UINT8 Data8;
Status = GetAllQncPmBase (gSmst);
ASSERT_EFI_ERROR (Status);
SmiEn = IoRead32 (mAcpiSmm.QncGpe0Base + R_QNC_GPE0BLK_SMIE);
//
// Disable SW SMI Timer
//
SmiEn &= ~(B_QNC_GPE0BLK_SMIE_SWT);
IoWrite32 (mAcpiSmm.QncGpe0Base + R_QNC_GPE0BLK_SMIE, SmiEn);
//
// Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)
//
Data8 = RTC_ADDRESS_REGISTER_D;
IoWrite8 (R_IOPORT_CMOS_STANDARD_INDEX, Data8);
Data8 = 0x0;
IoWrite8 (R_IOPORT_CMOS_STANDARD_DATA, Data8);
//
// Enable SCI
//
Pm1Cnt = IoRead16 (mAcpiSmm.QncPmBase + R_QNC_PM1BLK_PM1C);
Pm1Cnt |= B_QNC_PM1BLK_PM1C_SCIEN;
IoWrite16 (mAcpiSmm.QncPmBase + R_QNC_PM1BLK_PM1C, Pm1Cnt);
//
// Do platform specific stuff for ACPI enable SMI
//
return EFI_SUCCESS;
}
/**
This function is IO instruction handler for SMM.
@param Index CPU index
**/
VOID
SmmIoHandler (
IN UINT32 Index
)
{
VM_EXIT_QUALIFICATION Qualification;
UINT16 Port;
UINTN *DataPtr;
UINTN LinearAddr;
X86_REGISTER *Reg;
STM_RSC_IO_DESC *IoDesc;
STM_RSC_PCI_CFG_DESC *PciCfgDesc;
UINT32 PciAddress;
STM_RSC_IO_DESC LocalIoDesc;
STM_RSC_PCI_CFG_DESC *LocalPciCfgDescPtr;
UINT8 LocalPciCfgDescBuf[STM_LOG_ENTRY_SIZE];
Reg = &mGuestContextCommonSmm.GuestContextPerCpu[Index].Register;
Qualification.UintN = VmReadN (VMCS_N_RO_EXIT_QUALIFICATION_INDEX);
if (Qualification.IoInstruction.Operand != 0) {
Port = (UINT16)Qualification.IoInstruction.PortNum;
} else {
Port = (UINT16)Reg->Rdx;
}
DataPtr = (UINTN *)&Reg->Rax;
//
// We need handle case that CF9 is protected, but CF8, CFC need to be pass-through.
// But DWORD CF8 programming will be caught here.
// So add check here. CF8 will be bypassed, because it does not in CF9 scope.
//
IoDesc = GetStmResourceIo (mHostContextCommon.MleProtectedResource.Base, Port);
if (IoDesc != NULL) {
DEBUG ((EFI_D_ERROR, "IO violation!\n"));
AddEventLogForResource (EvtHandledProtectionException, (STM_RSC *)IoDesc);
SmmExceptionHandler (Index);
CpuDeadLoop ();
}
IoDesc = GetStmResourceIo ((STM_RSC *)(UINTN)mGuestContextCommonSmm.BiosHwResourceRequirementsPtr, Port);
if (IoDesc == NULL) {
ZeroMem (&LocalIoDesc, sizeof(LocalIoDesc));
LocalIoDesc.Hdr.RscType = IO_RANGE;
LocalIoDesc.Hdr.Length = sizeof(LocalIoDesc);
LocalIoDesc.Base = Port;
LocalIoDesc.Length = (UINT16)(Qualification.IoInstruction.Size + 1);
AddEventLogForResource (EvtBiosAccessToUnclaimedResource, (STM_RSC *)&LocalIoDesc);
}
//
// Check PCI - 0xCF8, 0xCFC~0xCFF access
//
if (Port == 0xCF8) {
// Access PciAddress
//
// We need make sure PciAddress access and PciData access is atomic.
//
AcquireSpinLock (&mHostContextCommon.PciLock);
}
if ((Port >= 0xCFC) && (Port <= 0xCFF)) {
// Access PciData
//
// AcquireLock to prevent 0xCF8 access
//
AcquireSpinLock (&mHostContextCommon.PciLock);
PciAddress = IoRead32 (0xCF8);
PciCfgDesc = GetStmResourcePci (
mHostContextCommon.MleProtectedResource.Base,
BUS_FROM_CF8_ADDRESS(PciAddress),
DEVICE_FROM_CF8_ADDRESS(PciAddress),
FUNCTION_FROM_CF8_ADDRESS(PciAddress),
REGISTER_FROM_CF8_ADDRESS(PciAddress) + (Port & 0x3),
(Qualification.IoInstruction.Direction != 0) ? STM_RSC_PCI_CFG_R : STM_RSC_PCI_CFG_W
);
if (PciCfgDesc != NULL) {
DEBUG ((EFI_D_ERROR, "IO (PCI) violation!\n"));
AddEventLogForResource (EvtHandledProtectionException, (STM_RSC *)PciCfgDesc);
ReleaseSpinLock (&mHostContextCommon.PciLock);
SmmExceptionHandler (Index);
CpuDeadLoop ();
}
PciCfgDesc = GetStmResourcePci (
(STM_RSC *)(UINTN)mGuestContextCommonSmm.BiosHwResourceRequirementsPtr,
BUS_FROM_CF8_ADDRESS(PciAddress),
DEVICE_FROM_CF8_ADDRESS(PciAddress),
FUNCTION_FROM_CF8_ADDRESS(PciAddress),
REGISTER_FROM_CF8_ADDRESS(PciAddress) + (Port & 0x3),
(Qualification.IoInstruction.Direction != 0) ? STM_RSC_PCI_CFG_R : STM_RSC_PCI_CFG_W
);
if (PciCfgDesc == NULL) {
DEBUG((EFI_D_ERROR, "Add unclaimed PCI_RSC!\n"));
LocalPciCfgDescPtr = (STM_RSC_PCI_CFG_DESC *)LocalPciCfgDescBuf;
ZeroMem (LocalPciCfgDescBuf, sizeof(LocalPciCfgDescBuf));
LocalPciCfgDescPtr->Hdr.RscType = PCI_CFG_RANGE;
LocalPciCfgDescPtr->Hdr.Length = sizeof(STM_RSC_PCI_CFG_DESC); // BUGBUG: Just report this PCI device, it is hard to create PCI hierachy here.
LocalPciCfgDescPtr->RWAttributes = (Qualification.IoInstruction.Direction != 0) ? STM_RSC_PCI_CFG_R : STM_RSC_PCI_CFG_W;
LocalPciCfgDescPtr->Base = REGISTER_FROM_CF8_ADDRESS(PciAddress) + (Port & 0x3);
LocalPciCfgDescPtr->Length = (UINT16)(Qualification.IoInstruction.Size + 1);
LocalPciCfgDescPtr->OriginatingBusNumber = BUS_FROM_CF8_ADDRESS(PciAddress);
LocalPciCfgDescPtr->LastNodeIndex = 0;
LocalPciCfgDescPtr->PciDevicePath[0].Type = 1;
LocalPciCfgDescPtr->PciDevicePath[0].Subtype = 1;
LocalPciCfgDescPtr->PciDevicePath[0].Length = sizeof(STM_PCI_DEVICE_PATH_NODE);
LocalPciCfgDescPtr->PciDevicePath[0].PciFunction = FUNCTION_FROM_CF8_ADDRESS(PciAddress);
LocalPciCfgDescPtr->PciDevicePath[0].PciDevice = DEVICE_FROM_CF8_ADDRESS(PciAddress);
AddEventLogForResource (EvtBiosAccessToUnclaimedResource, (STM_RSC *)LocalPciCfgDescPtr);
}
}
if (Qualification.IoInstruction.Rep != 0) {
UINT64 RcxMask;
RcxMask = 0xFFFFFFFFFFFFFFFFull;
if ((mGuestContextCommonSmm.GuestContextPerCpu[Index].Efer & IA32_EFER_MSR_MLA) == 0) {
RcxMask = 0xFFFFFFFFull;
}
if ((Reg->Rcx & RcxMask) == 0) {
// Skip
if ((Port == 0xCF8) || ((Port >= 0xCFC) && (Port <= 0xCFF))) {
ReleaseSpinLock (&mHostContextCommon.PciLock);
}
VmWriteN (VMCS_N_GUEST_RIP_INDEX, VmReadN(VMCS_N_GUEST_RIP_INDEX) + VmRead32(VMCS_32_RO_VMEXIT_INSTRUCTION_LENGTH_INDEX));
return ;
}
}
if (Qualification.IoInstruction.String != 0) {
LinearAddr = VmReadN (VMCS_N_RO_GUEST_LINEAR_ADDR_INDEX);
if (VmReadN (VMCS_N_GUEST_CR0_INDEX) & CR0_PG) {
DataPtr = (UINTN *)(UINTN)GuestLinearToHostPhysical (Index, LinearAddr);
} else {
DataPtr = (UINTN *)LinearAddr;
}
if ((VmReadN (VMCS_N_GUEST_RFLAGS_INDEX) & RFLAGS_DF) != 0) {
if (Qualification.IoInstruction.Direction != 0) {
Reg->Rdi -= Qualification.IoInstruction.Size + 1;
} else {
Reg->Rsi -= Qualification.IoInstruction.Size + 1;
}
} else {
if (Qualification.IoInstruction.Direction != 0) {
Reg->Rdi += Qualification.IoInstruction.Size + 1;
} else {
Reg->Rsi += Qualification.IoInstruction.Size + 1;
}
}
}
if (Qualification.IoInstruction.Direction != 0) { // IN
switch (Qualification.IoInstruction.Size) {
case 0:
*(UINT8 *)DataPtr = IoRead8 (Port);
goto Ret;
break;
case 1:
*(UINT16 *)DataPtr = IoRead16 (Port);
goto Ret;
break;
case 3:
*(UINT32 *)DataPtr = IoRead32 (Port);
goto Ret;
break;
default:
break;
}
} else { // OUT
switch (Qualification.IoInstruction.Size) {
case 0:
IoWrite8 (Port, (UINT8)*DataPtr);
goto Ret;
break;
case 1:
IoWrite16 (Port, (UINT16)*DataPtr);
goto Ret;
break;
case 3:
IoWrite32 (Port, (UINT32)*DataPtr);
goto Ret;
break;
default:
break;
}
}
if ((Port == 0xCF8) || ((Port >= 0xCFC) && (Port <= 0xCFF))) {
ReleaseSpinLock (&mHostContextCommon.PciLock);
}
DEBUG ((EFI_D_INFO, "!!!IoHandler!!!\n"));
DumpVmcsAllField ();
CpuDeadLoop ();
Ret:
if ((Port == 0xCF8) || ((Port >= 0xCFC) && (Port <= 0xCFF))) {
ReleaseSpinLock (&mHostContextCommon.PciLock);
}
if (Qualification.IoInstruction.Rep != 0) {
// replay
Reg->Rcx --;
return ;
}
VmWriteN (VMCS_N_GUEST_RIP_INDEX, VmReadN(VMCS_N_GUEST_RIP_INDEX) + VmRead32(VMCS_32_RO_VMEXIT_INSTRUCTION_LENGTH_INDEX));
return ;
}
EFI_STATUS
EFIAPI
MemoryDiscoveredPpiNotifyCallback (
IN CONST EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
IN VOID *Ppi
)
{
EFI_STATUS Status;
EFI_BOOT_MODE BootMode;
EFI_CPUID_REGISTER FeatureInfo;
UINT8 CpuAddressWidth;
UINT16 Pm1Cnt;
EFI_PEI_HOB_POINTERS Hob;
EFI_PLATFORM_INFO_HOB *PlatformInfo;
UINT32 RootComplexBar;
UINT32 PmcBase;
UINT32 IoBase;
UINT32 IlbBase;
UINT32 SpiBase;
UINT32 MphyBase;
//
// Get Platform Info HOB
//
Hob.Raw = GetFirstGuidHob (&gEfiPlatformInfoGuid);
ASSERT (Hob.Raw != NULL);
PlatformInfo = GET_GUID_HOB_DATA(Hob.Raw);
Status = (*PeiServices)->GetBootMode (PeiServices, &BootMode);
//
// Check if user wants to turn off in PEI phase
//
if ((BootMode != BOOT_ON_S3_RESUME) && (BootMode != BOOT_ON_FLASH_UPDATE)) {
CheckPowerOffNow();
} else {
Pm1Cnt = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT);
Pm1Cnt &= ~B_PCH_ACPI_PM1_CNT_SLP_TYP;
IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT, Pm1Cnt);
}
#ifndef MINNOW2_FSP_BUILD
//
// Set PEI cache mode here
//
SetPeiCacheMode (PeiServices);
#endif
//
// Pulish memory tyoe info
//
PublishMemoryTypeInfo ();
//
// Work done if on a S3 resume
//
if (BootMode == BOOT_ON_S3_RESUME) {
//
//Program the side band packet register to send a sideband message to Punit
//To indicate that DRAM has been initialized and PUNIT FW base address in memory.
//
return EFI_SUCCESS;
}
RootComplexBar = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_RCBA ) & B_PCH_LPC_RCBA_BAR;
BuildResourceDescriptorHob (
EFI_RESOURCE_MEMORY_MAPPED_IO,
(EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
RootComplexBar,
0x1000
);
DEBUG ((EFI_D_INFO, "RootComplexBar : 0x%x\n", RootComplexBar));
PmcBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_PMC_BASE ) & B_PCH_LPC_PMC_BASE_BAR;
BuildResourceDescriptorHob (
EFI_RESOURCE_MEMORY_MAPPED_IO,
(EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
PmcBase,
0x1000
);
DEBUG ((EFI_D_INFO, "PmcBase : 0x%x\n", PmcBase));
IoBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_IO_BASE ) & B_PCH_LPC_IO_BASE_BAR;
BuildResourceDescriptorHob (
EFI_RESOURCE_MEMORY_MAPPED_IO,
(EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
IoBase,
0x4000
);
DEBUG ((EFI_D_INFO, "IoBase : 0x%x\n", IoBase));
IlbBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_ILB_BASE ) & B_PCH_LPC_ILB_BASE_BAR;
BuildResourceDescriptorHob (
EFI_RESOURCE_MEMORY_MAPPED_IO,
(EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
IlbBase,
0x1000
);
DEBUG ((EFI_D_INFO, "IlbBase : 0x%x\n", IlbBase));
SpiBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_SPI_BASE ) & B_PCH_LPC_SPI_BASE_BAR;
BuildResourceDescriptorHob (
EFI_RESOURCE_MEMORY_MAPPED_IO,
(EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
SpiBase,
0x1000
);
DEBUG ((EFI_D_INFO, "SpiBase : 0x%x\n", SpiBase));
MphyBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_MPHY_BASE ) & B_PCH_LPC_MPHY_BASE_BAR;
BuildResourceDescriptorHob (
EFI_RESOURCE_MEMORY_MAPPED_IO,
(EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
MphyBase,
0x100000
);
DEBUG ((EFI_D_INFO, "MphyBase : 0x%x\n", MphyBase));
//
// Local APIC
//
BuildResourceDescriptorHob (
EFI_RESOURCE_MEMORY_MAPPED_IO,
(EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
LOCAL_APIC_ADDRESS,
0x1000
);
DEBUG ((EFI_D_INFO, "LOCAL_APIC_ADDRESS : 0x%x\n", LOCAL_APIC_ADDRESS));
//
// IO APIC
//
BuildResourceDescriptorHob (
EFI_RESOURCE_MEMORY_MAPPED_IO,
(EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
IO_APIC_ADDRESS,
0x1000
);
DEBUG ((EFI_D_INFO, "IO_APIC_ADDRESS : 0x%x\n", IO_APIC_ADDRESS));
//
// Adding the PCIE Express area to the E820 memory table as type 2 memory.
//
BuildResourceDescriptorHob (
EFI_RESOURCE_MEMORY_MAPPED_IO,
(EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
PlatformInfo->PciData.PciExpressBase,
PlatformInfo->PciData.PciExpressSize
);
DEBUG ((EFI_D_INFO, "PciExpressBase : 0x%x\n", PlatformInfo->PciData.PciExpressBase));
//
// Adding the Flashpart to the E820 memory table as type 2 memory.
//
BuildResourceDescriptorHob (
EFI_RESOURCE_FIRMWARE_DEVICE,
(EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
FixedPcdGet32 (PcdFlashAreaBaseAddress),
FixedPcdGet32 (PcdFlashAreaSize)
);
DEBUG ((EFI_D_INFO, "FLASH_BASE_ADDRESS : 0x%x\n", FixedPcdGet32 (PcdFlashAreaBaseAddress)));
//
// Create a CPU hand-off information
//
CpuAddressWidth = 32;
AsmCpuid (EFI_CPUID_EXTENDED_FUNCTION, &FeatureInfo.RegEax, &FeatureInfo.RegEbx, &FeatureInfo.RegEcx, &FeatureInfo.RegEdx);
if (FeatureInfo.RegEax >= EFI_CPUID_VIRT_PHYS_ADDRESS_SIZE) {
AsmCpuid (EFI_CPUID_VIRT_PHYS_ADDRESS_SIZE, &FeatureInfo.RegEax, &FeatureInfo.RegEbx, &FeatureInfo.RegEcx, &FeatureInfo.RegEdx);
CpuAddressWidth = (UINT8) (FeatureInfo.RegEax & 0xFF);
}
BuildCpuHob(CpuAddressWidth, 16);
ASSERT_EFI_ERROR (Status);
return Status;
}