/**
* Should software C1e be enabled
*
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] StdHeader Config Handle for library, services.
*
* @retval TRUE SW C1e is supported.
* @retval FALSE SW C1e not supported.
*
*/
BOOLEAN
STATIC
IsSwC1eFeatureEnabled (
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
BOOLEAN IsEnabled;
AP_MAILBOXES ApMailboxes;
SW_C1E_FAMILY_SERVICES *SwFamilyServices;
ASSERT (PlatformConfig->C1eMode < MaxC1eMode);
IsEnabled = FALSE;
// Check whether software C1e is enabled only if hardware C1e is not supported or if the platform specifically
// uses C1eModeSoftwareDeprecated.
if ((PlatformConfig->C1eMode == C1eModeSoftwareDeprecated) ||
((PlatformConfig->C1eMode == C1eModeHardwareSoftwareDeprecated) && (!IsFeatureEnabled (HardwareC1e, PlatformConfig, StdHeader)))) {
ASSERT ((PlatformConfig->C1ePlatformData1 < 0x10000) && (PlatformConfig->C1ePlatformData1 != 0));
ASSERT (PlatformConfig->C1ePlatformData2 < 0x100);
if ((PlatformConfig->C1ePlatformData1 != 0) && (PlatformConfig->C1ePlatformData1 < 0xFFFE) && (PlatformConfig->C1ePlatformData2 < 0xFF)) {
if (!IsNonCoherentHt1 (StdHeader)) {
if (GetNumberOfProcessors (StdHeader) == 1) {
GetApMailbox (&ApMailboxes.ApMailInfo.Info, StdHeader);
if (ApMailboxes.ApMailInfo.Fields.ModuleType == 0) {
GetFeatureServicesOfCurrentCore (&SwC1eFamilyServiceTable, &SwFamilyServices, StdHeader);
if (SwFamilyServices != NULL) {
IsEnabled = SwFamilyServices->IsSwC1eSupported (SwFamilyServices, StdHeader);
}
}
}
}
}
}
return IsEnabled;
}
/**
* Update microcode patch in current processor for Family16h ML.
*
* This function acts as a wrapper for calling the LoadMicrocodePatch
* routine at AmdInitEarly.
*
* @param[in] FamilyServices The current Family Specific Services.
* @param[in] EarlyParams Service parameters.
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
F16MlLoadMicrocodePatchAtEarly (
IN CPU_SPECIFIC_SERVICES *FamilyServices,
IN AMD_CPU_EARLY_PARAMS *EarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
if (!IsFeatureEnabled (C6Cstate, &EarlyParams->PlatformConfig, StdHeader)) {
AGESA_TESTPOINT (TpProcCpuLoadUcode, StdHeader);
LoadMicrocodePatch (StdHeader);
}
}
/**
* Main entry point for the AMD_INIT_LATE function.
*
* This entry point is responsible for creating any desired ACPI tables, providing
* information for DMI, and to prepare the processors for the operating system
* bootstrap load process.
*
* @param[in,out] LateParams Required input parameters for the AMD_INIT_LATE
* entry point.
*
* @return Aggregated status across all internal AMD late calls invoked.
*
*/
AGESA_STATUS
AmdInitLate (
IN OUT AMD_LATE_PARAMS *LateParams
)
{
AGESA_STATUS AgesaStatus;
AGESA_STATUS AmdInitLateStatus;
IDS_HDT_CONSOLE (MAIN_FLOW, "AmdInitLate: Start\n\n");
AGESA_TESTPOINT (TpIfAmdInitLateEntry, &LateParams->StdHeader);
IDS_PERF_TIME_MEASURE (&LateParams->StdHeader);
ASSERT (LateParams != NULL);
AmdInitLateStatus = AGESA_SUCCESS;
IDS_OPTION_HOOK (IDS_INIT_LATE_BEFORE, LateParams, &LateParams->StdHeader);
IDS_HDT_CONSOLE (MAIN_FLOW, "CreatSystemTable: Start\n");
// _PSS, XPSS, _PCT, _PSD, _PPC, _CST, _CSD Tables
if ((LateParams->PlatformConfig.UserOptionPState) || (IsFeatureEnabled (IoCstate, &LateParams->PlatformConfig, &LateParams->StdHeader))) {
AgesaStatus = ((*(OptionPstateLateConfiguration.SsdtFeature)) (&LateParams->StdHeader, &LateParams->PlatformConfig, &LateParams->AcpiPState));
if (AgesaStatus > AmdInitLateStatus) {
AmdInitLateStatus = AgesaStatus;
}
}
// SRAT Table Generation
if (LateParams->PlatformConfig.UserOptionSrat) {
AgesaStatus = CreateAcpiSrat (&LateParams->StdHeader, &LateParams->AcpiSrat);
if (AgesaStatus > AmdInitLateStatus) {
AmdInitLateStatus = AgesaStatus;
}
}
// SLIT Table Generation
if (LateParams->PlatformConfig.UserOptionSlit) {
AgesaStatus = CreateAcpiSlit (&LateParams->StdHeader, &LateParams->PlatformConfig, &LateParams->AcpiSlit);
if (AgesaStatus > AmdInitLateStatus) {
AmdInitLateStatus = AgesaStatus;
}
}
// WHEA Table Generation
if (LateParams->PlatformConfig.UserOptionWhea) {
AgesaStatus = CreateAcpiWhea (&LateParams->StdHeader, &LateParams->AcpiWheaMce, &LateParams->AcpiWheaCmc);
if (AgesaStatus > AmdInitLateStatus) {
AmdInitLateStatus = AgesaStatus;
}
}
// DMI Table Generation
if (LateParams->PlatformConfig.UserOptionDmi) {
AgesaStatus = CreateDmiRecords (&LateParams->StdHeader, &LateParams->DmiTable);
if (AgesaStatus > AmdInitLateStatus) {
AmdInitLateStatus = AgesaStatus;
}
}
IDS_HDT_CONSOLE (MAIN_FLOW, "CreatSystemTable: End\n");
// Cpu Features
IDS_HDT_CONSOLE (MAIN_FLOW, "DispatchCpuFeatures: LateStart\n");
AgesaStatus = DispatchCpuFeatures (CPU_FEAT_INIT_LATE_END, &LateParams->PlatformConfig, &LateParams->StdHeader);
IDS_HDT_CONSOLE (MAIN_FLOW, "DispatchCpuFeatures: LateEnd\n");
if (AgesaStatus > AmdInitLateStatus) {
AmdInitLateStatus = AgesaStatus;
}
// It is the last function run by the AGESA CPU module and prepares the processor
// for the operating system bootstrap load process.
IDS_HDT_CONSOLE (MAIN_FLOW, "AmdCpuLate: Start\n");
AgesaStatus = AmdCpuLate (&LateParams->StdHeader);
IDS_HDT_CONSOLE (MAIN_FLOW, "AmdCpuLate: End\n");
if (AgesaStatus > AmdInitLateStatus) {
AmdInitLateStatus = AgesaStatus;
}
AgesaStatus = GnbInitAtLate (LateParams);
if (AgesaStatus > AmdInitLateStatus) {
AmdInitLateStatus = AgesaStatus;
}
IDS_OPTION_HOOK (IDS_INIT_LATE_AFTER, LateParams, &LateParams->StdHeader);
IDS_OPTION_HOOK (IDS_BEFORE_OS, LateParams, &LateParams->StdHeader);
IDS_PERF_TIME_MEASURE (&LateParams->StdHeader);
AGESA_TESTPOINT (TpIfAmdInitLateExit, &LateParams->StdHeader);
IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitLate: End\n\n");
AGESA_TESTPOINT (EndAgesaTps, &LateParams->StdHeader);
//End Debug Print Service
IDS_HDT_CONSOLE_EXIT (&LateParams->StdHeader);
return AmdInitLateStatus;
}
/**
*---------------------------------------------------------------------------------------
*
* AmdCpuCreateProcessorTables
*
* Description:
* Final CPU initialization before passing control to the OS through BDS
*
* Parameters:
* @param[in] *This
* @param[in] TableType
* @param[in, out] *BufferLength
* @param[in, out] **BufferPtr
*
* @retval AGESA_STATUS
*
*---------------------------------------------------------------------------------------
**/
EFI_STATUS
EFIAPI
AmdCpuCreateProcessorTables (
IN AMD_AGESA_DXE_PROTOCOL *This,
IN AMD_PROCESSOR_TABLE_TYPE TableType,
IN OUT UINTN *BufferLength,
IN OUT VOID **BufferPtr
)
{
EFI_STATUS Status;
AMD_LATE_PARAMS *LateParamsPtr;
AGESA_DXE_PRIVATE_DATA *AgesaDxePrivate;
Status = EFI_SUCCESS;
if (BufferPtr == NULL) {
return EFI_INVALID_PARAMETER;
}
AgesaDxePrivate = AGESA_DXE_PRIVATE_DATA_INSTANCE_FROM_THIS (This);
LateParamsPtr = mAgesaDxePrivate->LateParamsPtr;
switch (TableType) {
case UndefinedProcessorTableType:
Status = EFI_UNSUPPORTED;
break;
case AcpiPstateType:
if ((LateParamsPtr->PlatformConfig.UserOptionPState) ||
(IsFeatureEnabled (IoCstate, &LateParamsPtr->PlatformConfig, &LateParamsPtr->StdHeader))) {
if (*((UINT32 *) LateParamsPtr->AcpiPState) == 'TDSS') {
if (*BufferLength < *((UINT32 *) LateParamsPtr->AcpiPState + 1)) {
*BufferLength = *((UINT32 *) LateParamsPtr->AcpiPState + 1);
Status = EFI_BUFFER_TOO_SMALL;
} else if (*BufferPtr != NULL) {
gBS->CopyMem (
*BufferPtr,
LateParamsPtr->AcpiPState,
*((UINT32 *) LateParamsPtr->AcpiPState + 1)
);
}
}
} else {
Status = EFI_ACCESS_DENIED;
}
break;
case AcpiWheaHestCmcType:
if (LateParamsPtr->PlatformConfig.UserOptionWhea) {
if (*BufferLength < *((UINT16 *) LateParamsPtr->AcpiWheaCmc)) {
*BufferLength = *((UINT16 *) LateParamsPtr->AcpiWheaCmc);
Status = EFI_BUFFER_TOO_SMALL;
} else {
gBS->CopyMem (
*BufferPtr,
LateParamsPtr->AcpiWheaCmc,
*((UINT16 *) LateParamsPtr->AcpiWheaCmc)
);
}
} else {
Status = EFI_ACCESS_DENIED;
}
break;
case AcpiWheaHestMceType:
if (LateParamsPtr->PlatformConfig.UserOptionWhea) {
if (*BufferLength < *((UINT16 *) LateParamsPtr->AcpiWheaMce)) {
*BufferLength = *((UINT16 *) LateParamsPtr->AcpiWheaMce);
Status = EFI_BUFFER_TOO_SMALL;
} else {
gBS->CopyMem (
*BufferPtr,
LateParamsPtr->AcpiWheaMce,
*((UINT16 *)LateParamsPtr->AcpiWheaMce)
);
}
} else {
Status = EFI_ACCESS_DENIED;
}
break;
case DmiTableType:
if (LateParamsPtr->PlatformConfig.UserOptionDmi) {
if (*BufferLength < sizeof (DMI_INFO)) {
*BufferLength = sizeof (DMI_INFO);
Status = EFI_BUFFER_TOO_SMALL;
} else if (*BufferPtr != NULL) {
gBS->CopyMem (
*BufferPtr,
LateParamsPtr->DmiTable,
sizeof (DMI_INFO)
);
}
} else {
Status = EFI_ACCESS_DENIED;
}
break;
case AcpiAlibType:
if (LateParamsPtr->AcpiAlib != NULL) {
if (*((UINT32 *) LateParamsPtr->AcpiAlib) == 'TDSS') {
if (*BufferLength < *((UINT32 *) LateParamsPtr->AcpiAlib + 1)) {
*BufferLength = *((UINT32 *) LateParamsPtr->AcpiAlib + 1);
Status = EFI_BUFFER_TOO_SMALL;
} else if (*BufferPtr != NULL) {
gBS->CopyMem (
*BufferPtr,
LateParamsPtr->AcpiAlib,
*((UINT32 *) LateParamsPtr->AcpiAlib + 1)
);
}
}
} else {
Status = EFI_ACCESS_DENIED;
}
break;
case AcpiIvrsType:
if (LateParamsPtr->AcpiIvrs != NULL) {
if (*((UINT32 *) LateParamsPtr->AcpiIvrs) == 'SRVI') {
if (*BufferLength < *((UINT32 *) LateParamsPtr->AcpiIvrs + 1)) {
*BufferLength = *((UINT32 *) LateParamsPtr->AcpiIvrs + 1);
Status = EFI_BUFFER_TOO_SMALL;
} else if (*BufferPtr != NULL) {
gBS->CopyMem (
*BufferPtr,
LateParamsPtr->AcpiIvrs,
*((UINT32 *) LateParamsPtr->AcpiIvrs + 1)
);
}
}
} else {
Status = EFI_ACCESS_DENIED;
}
break;
case AcpiCratType:
if (LateParamsPtr->PlatformConfig.UserOptionCrat) {
if (*((UINT32 *) LateParamsPtr->AcpiCrat) == 'TARC') {
if (*BufferLength < *((UINT32 *) LateParamsPtr->AcpiCrat + 1)) {
*BufferLength = *((UINT32 *) LateParamsPtr->AcpiCrat + 1);
Status = EFI_BUFFER_TOO_SMALL;
} else if (*BufferPtr != NULL) {
gBS->CopyMem (
*BufferPtr,
LateParamsPtr->AcpiCrat,
*((UINT32 *) LateParamsPtr->AcpiCrat + 1)
);
}
}
} else {
Status = EFI_ACCESS_DENIED;
}
break;
case AcpiCditType:
if (LateParamsPtr->PlatformConfig.UserOptionCdit) {
if (*((UINT32 *) LateParamsPtr->AcpiCdit) == 'TIDC') {
if (*BufferLength < *((UINT32 *) LateParamsPtr->AcpiCdit + 1)) {
*BufferLength = *((UINT32 *) LateParamsPtr->AcpiCdit + 1);
Status = EFI_BUFFER_TOO_SMALL;
} else if (*BufferPtr != NULL) {
gBS->CopyMem (
*BufferPtr,
LateParamsPtr->AcpiCdit,
*((UINT32 *) LateParamsPtr->AcpiCdit + 1)
);
}
}
} else {
Status = EFI_ACCESS_DENIED;
}
break;
default:
Status = EFI_INVALID_PARAMETER;
}
return Status;
}
/**
*
* This function generates a complete SLIT table into a memory buffer.
* After completion, this table must be set by the system BIOS into its
* internal ACPI namespace, and linked into the RSDT/XSDT
*
* @param[in, out] StdHeader Standard Head Pointer
* @param[in] PlatformConfig Config handle for platform specific information
* @param[in, out] SlitPtr Point to Slit Struct including buffer address and length
*
* @retval UINT32 AGESA_STATUS
*/
AGESA_STATUS
GetAcpiSlitMain (
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN OUT VOID **SlitPtr
)
{
UINT8 MaxHops;
UINT8 SocketNum;
UINT8 i;
UINT8 j;
UINT8 *BufferPtr;
UINT8 *SocketTopologyDataPtr;
UINT8 *SocketTopologyPtr;
ACPI_TABLE_HEADER *CpuSlitHeaderStructPtr;
AGESA_STATUS Flag;
ALLOCATE_HEAP_PARAMS AllocStruct;
MaxHops = 0;
SocketTopologyPtr = NULL;
Flag = AGESA_ERROR;
// find out the pointer to the BufferHandle which contains
// Node Topology information
AcpiSlitHBufferFind (StdHeader, &SocketTopologyPtr);
if (SocketTopologyPtr == 0) {
return (Flag);
}
SocketNum = *SocketTopologyPtr;
IDS_HDT_CONSOLE (CPU_TRACE, " SLIT is created\n");
// create a buffer by calling IBV callout routine
AllocStruct.RequestedBufferSize = (SocketNum * SocketNum) + AMD_ACPI_SLIT_SOCKET_NUM_LENGTH + sizeof (ACPI_TABLE_HEADER);
AllocStruct.BufferHandle = AMD_ACPI_SLIT_BUFFER_HANDLE;
AllocStruct.Persist = HEAP_SYSTEM_MEM;
if (HeapAllocateBuffer (&AllocStruct, StdHeader) != AGESA_SUCCESS) {
return (Flag);
}
*SlitPtr = AllocStruct.BufferPtr;
//SLIT header
LibAmdMemCopy (*SlitPtr, (VOID *) &CpuSlitHdrStruct, (UINTN) (sizeof (ACPI_TABLE_HEADER)), StdHeader);
CpuSlitHeaderStructPtr = (ACPI_TABLE_HEADER *) *SlitPtr;
CpuSlitHeaderStructPtr->TableLength = (UINT32) AllocStruct.RequestedBufferSize;
BufferPtr = *SlitPtr;
Flag = AGESA_SUCCESS;
// SLIT body
// check if is PfMode (Prober Filer Mode)
if (!IsFeatureEnabled (HtAssist, PlatformConfig, StdHeader)) {
// probe filter is disabled
// get MaxHops
SocketTopologyDataPtr = SocketTopologyPtr + sizeof (SocketNum);
for (i = 0; i < SocketNum; i++) {
for (j = 0; j < SocketNum; j++) {
if (*SocketTopologyDataPtr > MaxHops) {
MaxHops = *SocketTopologyDataPtr;
}
SocketTopologyDataPtr++;
}
}
// the Max hop entries have a value of 13
// and all other entries have 10.
SocketTopologyDataPtr = SocketTopologyPtr + sizeof (SocketNum);
for (i = 0; i < SocketNum; i++) {
for (j = 0; j < SocketNum; j++) {
if (*SocketTopologyDataPtr++ == MaxHops) {
*(BufferPtr + sizeof (ACPI_TABLE_HEADER) +
AMD_ACPI_SLIT_SOCKET_NUM_LENGTH + (i * SocketNum) + j) = 13;
} else {
*(BufferPtr + sizeof (ACPI_TABLE_HEADER) +
AMD_ACPI_SLIT_SOCKET_NUM_LENGTH + (i * SocketNum) + j) = 10;
}
}
}
} else {
// probe filter is enabled
// formula : num_hops * 6 + 10
SocketTopologyDataPtr = SocketTopologyPtr + sizeof (SocketNum);
for (i = 0; i < SocketNum; i++) {
for (j = 0; j < SocketNum; j++) {
*(BufferPtr + sizeof (ACPI_TABLE_HEADER) +
AMD_ACPI_SLIT_SOCKET_NUM_LENGTH + (i * SocketNum) + j) =
((*SocketTopologyDataPtr++) * 6) + 10;
}
}
}
BufferPtr += sizeof (ACPI_TABLE_HEADER);
*((UINT64 *) BufferPtr) = (UINT64) SocketNum;
//Update SLIT header Checksum
ChecksumAcpiTable ((ACPI_TABLE_HEADER *) *SlitPtr, StdHeader);
return (Flag);
}
