void TWS_CKC_SetDDIBUS(int ddibusname, unsigned char mode)
{
#ifdef __TCC89XX_WINCE__
int retVal = -1;
stckcioctl pCKCIOCTL;
stckcinfo pCKCINFO;
unsigned long returnedbyte;
if((ddibusname < DDIPWDN_CIF) || (ddibusname >= DDIPWDN_STEPMAX))
{
printf("[TWS_CKC_SetDDIBUS] Invalid DDI BUS : %d\n", ddibusname);
return;
}
/* mode : 0(ddi bus disable), 1(ddi bus enable) */
pCKCIOCTL.ioctlcode = IOCTL_CKC_SET_DDIPWDN;
pCKCIOCTL.ddipdname = ddibusname;
pCKCIOCTL.mode = (mode>0)?1:0;
KernelIoControl(IOCTL_HAL_TCCCKC, &pCKCIOCTL, sizeof(stckcioctl), &pCKCINFO, sizeof(stckcinfo), &returnedbyte);
pCKCIOCTL.ioctlcode = IOCTL_CKC_GET_DDIPWDN;
KernelIoControl(IOCTL_HAL_TCCCKC, &pCKCIOCTL, sizeof(stckcioctl), &pCKCINFO, sizeof(stckcinfo), &returnedbyte);
if(pCKCINFO.retVal == 0) // Enable
printf("[TWS_CKC_SetDDIBUS]DDIBUS : %d - Enable\n", pCKCIOCTL.ddipdname);
else // Disable
printf("[TWS_CKC_SetDDIBUS]DDIBUS : %d - Disable\n", pCKCIOCTL.ddipdname);
#endif
}
void TWS_CKC_SetIOBUS(int iobusname, unsigned char mode)
{
#ifdef __TCC89XX_WINCE__
int retVal = -1;
stckcioctl pCKCIOCTL;
stckcinfo pCKCINFO;
unsigned long returnedbyte;
if((iobusname < RB_USB11H) || (iobusname >= RB_ALLPERIPERALS))
{
printf("[TWS_CKC_SetIOBUS] Invalid IO BUS : %d\n", iobusname);
return;
}
/* mode : 0(io bus disable), 1(io bus enable) */
pCKCIOCTL.ioctlcode = IOCTL_CKC_SET_PERIBUS;
pCKCIOCTL.prbname = iobusname;
pCKCIOCTL.mode = (mode>0)?1:0;
KernelIoControl(IOCTL_HAL_TCCCKC, &pCKCIOCTL, sizeof(stckcioctl), &pCKCINFO, sizeof(stckcinfo), &returnedbyte);
pCKCIOCTL.ioctlcode = IOCTL_CKC_GET_PERIBUS;
KernelIoControl(IOCTL_HAL_TCCCKC, &pCKCIOCTL, sizeof(stckcioctl), &pCKCINFO, sizeof(stckcinfo), &returnedbyte);
if(pCKCINFO.retVal == 0)
printf("[TWS_CKC_SetIOBUS]IOBUS: %d - Disable\n", pCKCIOCTL.prbname);
else
printf("[TWS_CKC_SetIOBUS]IOBUS: %d - Enable\n", pCKCIOCTL.prbname);
#endif
}
SD_API_STATUS
CSDHCBase::SetControllerPowerState(
CEDEVICE_POWER_STATE cpsNew
)
{
if (cpsNew != m_cpsCurrent) {
switch (cpsNew) {
case D0:
case D4:
KernelIoControl(IOCTL_HAL_DISABLE_WAKE, &m_dwSysIntr,
sizeof(m_dwSysIntr), NULL, 0, NULL);
break;
case D3:
KernelIoControl(IOCTL_HAL_ENABLE_WAKE, &m_dwSysIntr,
sizeof(m_dwSysIntr), NULL, 0, NULL);
break;
}
SetDevicePowerState(m_hBusAccess, cpsNew, NULL);
m_cpsCurrent = cpsNew;
}
return SD_API_STATUS_SUCCESS;
}
BOOL
DdsiTouchPanelEnable(VOID)
{
UINT32 Irq[3];
TSPMSG((_T("[TSP] ++DdsiTouchPanelEnable()\r\n")));
if (!g_bTSP_Initialized) // Map Virtual address and Interrupt at First time Only
{
if (!TSP_VirtualAlloc())
{
TSPERR((_T("[TSP:ERR] DdsiTouchPanelEnable() : TSP_VirtualAlloc() Failed\r\n")));
return FALSE;
}
// Initialize Critical Section
InitializeCriticalSection(&g_csTouchADC);
// Obtain SysIntr values from the OAL for the touch and touch timer interrupts.
Irq[0] = -1;
Irq[1] = OAL_INTR_FORCE_STATIC;
Irq[2] = IRQ_PENDN;
if (!KernelIoControl(IOCTL_HAL_REQUEST_SYSINTR, &Irq, sizeof(Irq), &gIntrTouch, sizeof(UINT32), NULL))
{
TSPERR((_T("[TSP:ERR] DdsiTouchPanelEnable() : IOCTL_HAL_REQUEST_SYSINTR Failed\r\n")));
gIntrTouch = SYSINTR_UNDEFINED;
return FALSE;
}
Irq[0] = -1;
Irq[1] = OAL_INTR_FORCE_STATIC;
Irq[2] = IRQ_TIMER3;
if (!KernelIoControl(IOCTL_HAL_REQUEST_SYSINTR, &Irq, sizeof(Irq), &gIntrTouchChanged, sizeof(UINT32), NULL))
{
TSPERR((_T("[TSP:ERR] DdsiTouchPanelEnable() : IOCTL_HAL_REQUEST_SYSINTR Failed\r\n")));
gIntrTouchChanged = SYSINTR_UNDEFINED;
return FALSE ;
}
TSPINF((_T("[TSP:INF] DdsiTouchPanelEnable() : gIntrTouch = %d\r\n"), gIntrTouch));
TSPINF((_T("[TSP:INF] DdsiTouchPanelEnable() : gIntrTouchChanged = %d\r\n"), gIntrTouchChanged));
g_bTSP_Initialized = TRUE;
}
TSP_PowerOn();
TSPMSG((_T("[TSP] --DdsiTouchPanelEnable()\r\n")));
return TRUE;
}
//------------------------------------------------------------------------------
//
// Function: AccessPMUReg
//
// This API calls KernelIoControl to access the PMU Register.
// This in turn calls the OEMIoControl routine.
// Note, the system is fully preemptible when this
// routine is called.
//
BOOL WINAPI AccessPMUReg(
PMUHandle handle,
enum PMURegAccessType Access,
unsigned long RegisterNumber,
unsigned long *pValue)
{
PMURegInfo PMURegBuffer;
unsigned long PMURegResults,
nOutBytes;
BOOL rtnvalue = FALSE;
if (handle == 0)
{
return FALSE;
}
PMURegBuffer.PMUReg = RegisterNumber;
switch (Access)
{
case READ:
PMURegBuffer.subcode = PMU_READ_REG;
rtnvalue =
KernelIoControl (IOCTL_PMU_CONFIG, (void *)&PMURegBuffer, sizeof(PMURegInfo),
&PMURegResults, sizeof(PMURegResults), &nOutBytes);
if (rtnvalue && (nOutBytes == sizeof(unsigned long)))
{
*pValue = PMURegResults;
}
else
{
rtnvalue = FALSE;
}
break;
case WRITE:
PMURegBuffer.subcode = PMU_WRITE_REG;
PMURegBuffer.PMUValue = *pValue;
rtnvalue =
KernelIoControl (IOCTL_PMU_CONFIG, (void *)&PMURegBuffer, sizeof(PMURegInfo),
&PMURegResults, sizeof(PMURegResults), &nOutBytes);
break;
default:
return FALSE;
break;
}
return rtnvalue;
}
static void
PWR_ReleaseResources(void)
{
PWRBTN_MSG((_T("[PWR] ++PWR_ReleaseResources()\r\n")));
if (g_pGPIOReg != NULL)
{
DrvLib_UnmapIoSpace((PVOID)g_pGPIOReg);
g_pGPIOReg = NULL;
}
if (g_dwSysIntrPowerBtn != SYSINTR_UNDEFINED)
{
InterruptDisable(g_dwSysIntrPowerBtn);
}
if (g_hEventPowerBtn != NULL)
{
CloseHandle(g_hEventPowerBtn);
}
if (g_dwSysIntrPowerBtn != SYSINTR_UNDEFINED)
{
KernelIoControl(IOCTL_HAL_RELEASE_SYSINTR, &g_dwSysIntrPowerBtn, sizeof(DWORD), NULL, 0, NULL);
}
if (g_dwSysIntrResetBtn != SYSINTR_UNDEFINED)
{
InterruptDisable(g_dwSysIntrResetBtn);
}
if (g_hEventResetBtn != NULL)
{
CloseHandle(g_hEventResetBtn);
}
if (g_dwSysIntrResetBtn != SYSINTR_UNDEFINED)
{
KernelIoControl(IOCTL_HAL_RELEASE_SYSINTR, &g_dwSysIntrResetBtn, sizeof(DWORD), NULL, 0, NULL);
}
g_pGPIOReg = NULL;
g_dwSysIntrPowerBtn = SYSINTR_UNDEFINED;
g_dwSysIntrResetBtn = SYSINTR_UNDEFINED;
g_hEventPowerBtn = NULL;
g_hEventResetBtn = NULL;
PWRBTN_MSG((_T("[PWR] --PWR_ReleaseResources()\r\n")));
}
//Example function for later use
unsigned long KGetProcInfo(unsigned char * InStructurePointer,
unsigned long InStructureLength, unsigned char * OutStructurePointer,
unsigned long OutStructureLength) {
Output("GetProcInfo(0x%x, %d, 0x%X, %d)\n", InStructurePointer,
InStructureLength, OutStructurePointer, OutStructureLength);
Output("sizeof(VOID_STRUCT) = %d, sizeof(PROCESSOR_INFO) = %d)\n",
sizeof(VOID_STRUCT), sizeof(PROCESSOR_INFO));
if (InStructurePointer && OutStructurePointer
&& sizeof(VOID_STRUCT) == InStructureLength
&& sizeof(PROCESSOR_INFO) == OutStructureLength) {
PROCESSOR_INFO * pinfo = (PROCESSOR_INFO *) OutStructurePointer;
// Try to lookup processor type.
DWORD rsize;
memset(&pinfo, sizeof(pinfo), 0);
int ret = KernelIoControl(IOCTL_PROCESSOR_INFORMATION, NULL, 0, &pinfo,
sizeof(pinfo), &rsize);
if (ret) {
Output("pinfo filled, GetProcInfo returns ERROR_SUCCESS\n");
return ERROR_SUCCESS;
}
Output("pinfo not filled, GetProcInfo returns ERROR_SUCCESS\n");
return ERROR;
}
return ERROR_INVALID_PARAMETER;
}
int TWS_CKC_GetBUS(int pckname,int *pckcfreq)
{
#ifdef __TCC89XX_WINCE__
int retVal = -1;
stckcioctl pCKCIOCTL;
stckcinfo pCKCINFO;
unsigned long returnedbyte;
pCKCIOCTL.ioctlcode = IOCTL_CKC_GET_CLOCKINFO;
KernelIoControl(IOCTL_HAL_TCCCKC, &pCKCIOCTL, sizeof(stckcioctl), &pCKCINFO, sizeof(stckcinfo), &returnedbyte);
printf("======================================\n");
printf("[TWS_CKC_GetBUS] PLL: %10d\n", pCKCINFO.currentsysfreq);
printf("[TWS_CKC_GetBUS] CPU: %10d\n",pCKCINFO.currentcpufreq);
printf("[TWS_CKC_GetBUS] MEM: %10d\n",pCKCINFO.currentbusfreq);
printf("======================================\n");
if(pckcfreq!=NULL)
{
*pckcfreq = pCKCINFO.currentbusfreq;
}
return pCKCINFO.currentbusfreq;
#else
return 0;
#endif
}
BOOL NLedBoardInit()
{
if (NLedCpuFamily == -1)
{
KernelIoControl(
IOCTL_HAL_GET_CPUFAMILY,
&NLedCpuFamily,
sizeof(DWORD),
&NLedCpuFamily,
sizeof(DWORD),
NULL
);
}
if( NLedCpuFamily != CPU_FAMILY_DM37XX)
{
if (RequestAndConfigurePadArray(LedPinMux))
{
return TRUE;
}
else
{
ERRORMSG(1,(TEXT("Unable to request PAD configuration for NLED driver\r\n")));
return FALSE;
}
}
return FALSE;
}
//-----------------------------------------------------------------------------
//
// Function: HalContextUpdateDirtyRegister
//
// update context save mask to indicate registers need to be saved before
// off
//
void
HalContextUpdateDirtyRegister(
UINT32 ffRegister
)
{
#if 1
#if (_WINCEOSVER<600)
BOOL bOldMode = SetKMode(TRUE);
#endif
static UINT32 *pKernelContextSaveMask = NULL;
if (pKernelContextSaveMask == NULL)
{
KernelIoControl(IOCTL_HAL_CONTEXTSAVE_GETBUFFER,
NULL,
0,
&pKernelContextSaveMask,
sizeof(UINT**),
0
);
}
*pKernelContextSaveMask |= ffRegister;
#if (_WINCEOSVER<600)
SetKMode(bOldMode);
#endif
#else
UNREFERENCED_PARAMETER(ffRegister);
#endif
}
void vm_sys_info_get_cpu_name(vm_char *cpu_name)
{
PROCESSOR_INFO pi;
Ipp32u dwBytesReturned;
Ipp32u dwSize = sizeof(PROCESSOR_INFO);
BOOL bResult;
/* check error(s) */
if (NULL == cpu_name)
return;
ZeroMemory(&pi, sizeof(PROCESSOR_INFO));
bResult = KernelIoControl(IOCTL_PROCESSOR_INFORMATION,
NULL,
0,
&pi,
sizeof(PROCESSOR_INFO),
&dwBytesReturned);
vm_string_sprintf(cpu_name,
VM_STRING("%s %s"),
pi.szProcessCore,
pi.szProcessorName);
} /* void vm_sys_info_get_cpu_name(vm_char *cpu_name) */
SD_API_STATUS
CSDHCBase::Stop()
{
// Mark for shutdown
m_fDriverShutdown = TRUE;
if (m_fInterruptInitialized) {
KernelIoControl(IOCTL_HAL_DISABLE_WAKE, &m_dwSysIntr, sizeof(m_dwSysIntr),
NULL, 0, NULL);
InterruptDisable(m_dwSysIntr);
}
// Clean up controller IST
if (m_htIST) {
// Wake up the IST
SetEvent(m_hevInterrupt);
WaitForSingleObject(m_htIST, INFINITE);
CloseHandle(m_htIST);
m_htIST = NULL;
}
// free controller interrupt event
if (m_hevInterrupt) {
CloseHandle(m_hevInterrupt);
m_hevInterrupt = NULL;
}
for (DWORD dwSlot = 0; dwSlot < m_cSlots; ++dwSlot) {
PCSDHCSlotBase pSlot = GetSlot(dwSlot);
pSlot->Stop();
}
return SD_API_STATUS_SUCCESS;
}
//------------------------------------------------------------------------------
//
// Function: HalSetBusDataByOffset
//
// This function write bus configuration data. It convert input parameters
// to new format and then it calls kernel to do rest.
//
ULONG HalSetBusDataByOffset(
BUS_DATA_TYPE busDataType, ULONG busNumber, ULONG slotNumber, VOID *pBuffer,
ULONG offset, ULONG length
) {
OAL_DDK_PARAMS params;
PCI_SLOT_NUMBER slot;
UINT32 outSize, rc = 0;
params.function = IOCTL_OAL_WRITEBUSDATA;
params.rc = 0;
switch (busDataType) {
case PCIConfiguration:
params.busData.devLoc.IfcType = PCIBus;
slot.u.AsULONG = slotNumber;
params.busData.devLoc.BusNumber = busNumber >> 8;
params.busData.devLoc.LogicalLoc = (busNumber & 0xFF) << 16;
params.busData.devLoc.LogicalLoc |= slot.u.bits.DeviceNumber << 8;
params.busData.devLoc.LogicalLoc |= slot.u.bits.FunctionNumber;
rc = TRUE;
break;
}
params.busData.offset = offset;
params.busData.length = length;
params.busData.pBuffer = pBuffer;
if (KernelIoControl(
IOCTL_HAL_DDK_CALL, ¶ms, sizeof(params), NULL, 0, &outSize
)) {
rc = params.rc;
}
return rc;
}
//------------------------------------------------------------------------------
//
// Function: GetCurrentCoreClockFrequency
//
// Returns the current core clock frequency (in KHz).
//
unsigned long WINAPI GetCurrentCoreClockFrequency(void)
{
PMUCCFInfo PMUCCFBuffer;
unsigned long CurFrequency,
nOutBytes;
BOOL rtnvalue = FALSE;
//
// This API calls KernelIoControl to access to get
// the current core clock frequency.
// This in turn calls the OEMIoControl routine.
// Note, the system is fully preemptible when this
// routine is called.
//
//
// Set the subcode for get ccf
//
PMUCCFBuffer.subcode = PMU_CCF_GETCURRENT;
rtnvalue =
KernelIoControl (IOCTL_PMU_CCF, (void *)&PMUCCFBuffer, sizeof(PMUCCFInfo),
&CurFrequency, sizeof(CurFrequency), &nOutBytes);
if (rtnvalue && (nOutBytes == sizeof(unsigned long)))
{
return CurFrequency;
}
else
{
return 0;
}
}
//------------------------------------------------------------------------------
//
// Function: GetOEMConfigData
//
// This API calls KernelIoControl to retrieve the OEM
// configuration data. This in turn calls the OEMIoControl routine.
// Note, the system is fully preemptible when this
// routine is called.
//
// Currently, the OEM configuration data retrieved consists
// of two items: the system interrupt ID assigned by the OEM,
// and the address to the VTune PMU driver globals area.
//
BOOL WINAPI GetOEMConfigData (
unsigned long *configArray,
unsigned long maxItems,
unsigned long *nOutItems)
{
OEMInfo OEMBuffer;
PMURegInfo PMURegBuffer;
unsigned long nOutBytes;
BOOL rtnvalue = FALSE;
PMURegBuffer.subcode = PMU_OEM_INFO;
rtnvalue =
KernelIoControl (IOCTL_PMU_CONFIG, (void *)&PMURegBuffer, sizeof(PMURegInfo),
&OEMBuffer, sizeof(OEMInfo), &nOutBytes);
if (rtnvalue && ((nOutBytes != sizeof(OEMInfo) ||
(nOutBytes > (maxItems*sizeof(unsigned long))))))
{
rtnvalue = FALSE;
*nOutItems = 0;
}
else
{
configArray[0] = OEMBuffer.sysintrID;
configArray[1] = OEMBuffer.PMUglobals;
*nOutItems = 2;
}
return rtnvalue;
}
void TWS_CKC_SetFBUS(int pckname,int pckcenable,int mode, int pckcfreq, int source)
{
#ifdef __TCC89XX_WINCE__
int retVal = -1;
stckcioctl pCKCIOCTL;
stckcinfo pCKCINFO;
unsigned long returnedbyte;
int ret;
pCKCIOCTL.ioctlcode = IOCTL_CKC_SET_CHANGEFBUS;
pCKCIOCTL.fbusname = pckname;
pCKCIOCTL.fbusfreq = pckcfreq;
ret = KernelIoControl(IOCTL_HAL_TCCCKC, &pCKCIOCTL, sizeof(stckcioctl), &pCKCINFO, sizeof(stckcinfo), &returnedbyte);
// check a frequency
printf("[TWS_CKC_SetFBUS] %d, %10d\n", pckname, TWS_CKC_GetFBUS(pckname));
// check a relative PMU status
switch(pckname)
{
case CLKCTRL3:
{
pCKCIOCTL.ioctlcode = IOCTL_CKC_GET_PMUPOWER;
pCKCIOCTL.pmuoffname = PMU_GRAPHICBUS;
KernelIoControl(IOCTL_HAL_TCCCKC, &pCKCIOCTL, sizeof(stckcioctl), &pCKCINFO, sizeof(stckcinfo), &returnedbyte);
if(pCKCINFO.state == 1) // 1 : Disable, 0: Enable
printf("[TWS_CKC_SetFBUS]PMU_GRAPHICBUS: Disable\n");
else
printf("[TWS_CKC_SetFBUS]PMU_GRAPHICBUS: Enable\n");
}
break;
case CLKCTRL5:
{
pCKCIOCTL.ioctlcode = IOCTL_CKC_GET_PMUPOWER;
pCKCIOCTL.pmuoffname = PMU_VIDEOBUS;
KernelIoControl(IOCTL_HAL_TCCCKC, &pCKCIOCTL, sizeof(stckcioctl), &pCKCINFO, sizeof(stckcinfo), &returnedbyte);
if(pCKCINFO.state == 1) // 1 : Disable, 0: Enable
printf("[TWS_CKC_SetFBUS]PMU_VIDEOBUS: Disable\n");
else
printf("[TWS_CKC_SetFBUS]PMU_VIDEOBUS: Enable\n");
}
break;
}
#endif
}
virtual BOOL Init()
{
PHYSICAL_ADDRESS ioPhysicalBase = {0,0};
ioPhysicalBase.LowPart = S3C6410_BASE_REG_PA_SYSCON;
ioPhysicalBase.HighPart = 0;
m_pSysconRegs = (S3C6410_SYSCON_REG *) MmMapIoSpace(ioPhysicalBase,sizeof(S3C6410_SYSCON_REG),FALSE);
if(m_pSysconRegs)
{
m_pSysconRegs->PCLK_GATE |= PCLK_UART0; // UART0
m_pSysconRegs->SCLK_GATE |= SCLK_UART; // UART0~3
}
else
{
return FALSE;
}
ioPhysicalBase.LowPart = S3C6410_BASE_REG_PA_GPIO;
ioPhysicalBase.HighPart = 0;
m_pIOPregs = (S3C6410_GPIO_REG *) MmMapIoSpace(ioPhysicalBase, sizeof(S3C6410_GPIO_REG),FALSE);
if (m_pIOPregs)
{
DDKISRINFO ddi;
if (GetIsrInfo(&ddi)== ERROR_SUCCESS &&
KernelIoControl(IOCTL_HAL_REQUEST_SYSINTR, &ddi.dwIrq, sizeof(UINT32), &ddi.dwSysintr, sizeof(UINT32), NULL))
{
RETAILMSG( FALSE, (TEXT("DEBUG: Serial0 SYSINTR : %d\r\n"), (PBYTE)&ddi.dwSysintr));
RegSetValueEx(DEVLOAD_SYSINTR_VALNAME,REG_DWORD,(PBYTE)&ddi.dwSysintr, sizeof(UINT32));
}
else
{
return FALSE;
}
m_pDTRPort = (volatile ULONG *)&(m_pIOPregs->GPNDAT);
m_pDSRPort = (volatile ULONG *)&(m_pIOPregs->GPNDAT);
m_dwDTRPortNum = DTR_PORT_NUMBER;
m_dwDSRPortNum = DSR_PORT_NUMBER;
// CTS0(GPA2), RTS0(GPA3), TXD0(GPA1), RXD0(GPA0)
m_pIOPregs->GPACON &= ~(0xf<<0 | 0xf<<4 | 0xf<<8 | 0xf<<12 ); ///< Clear Bit
m_pIOPregs->GPACON |= (0x2<<0 | 0x2<<4 | 0x2<<8 | 0x2<<12 ); ///< Select UART IP
m_pIOPregs->GPAPUD &= ~(0x3<<0 | 0x3<<2 | 0x3<<4 | 0x3<<6 ); ///< Pull-Up/Down Disable
// DTR0(GPN6), DSR0(GPN7)
// DTR and DSR are used for ActiveSync connection.
m_pIOPregs->GPNCON &= ~(0x3<<12); ///< DTR0 Clear Bit
m_pIOPregs->GPNCON |= (0x1<<12); ///< Output
m_pIOPregs->GPNPUD &= ~(0x3<<12); ///< Pull-Up/Down Disable
m_pIOPregs->GPNCON &= ~(0x3<<14); ///< DSR0 Clear Bit
m_pIOPregs->GPNCON |= (0x0<<14); ///< Input
m_pIOPregs->GPNPUD &= ~(0x3<<14); ///< Pull-Up/Down Disable
return CPdd6410Uart::Init();
}
return FALSE;
}
void OnWarmBoot()
{
BOOL status;
DWORD bytes_returned;
status = KernelIoControl( IOCTL_HAL_WARMBOOT, NULL, 0, NULL, 0, &bytes_returned );
//TODO: Add check to see that changes haven't been made since last "OnUpdate()" & alert if necessary
}
virtual BOOL Init()
{
PHYSICAL_ADDRESS ioPhysicalBase = {0,0};
ioPhysicalBase.LowPart = S3C6410_BASE_REG_PA_SYSCON;
ioPhysicalBase.HighPart = 0;
m_pSysconRegs = (S3C6410_SYSCON_REG *) MmMapIoSpace(ioPhysicalBase,sizeof(S3C6410_SYSCON_REG),FALSE);
if(m_pSysconRegs)
{
m_pSysconRegs->PCLK_GATE |= PCLK_UART1; // UART1
m_pSysconRegs->SCLK_GATE |= SCLK_UART; // UART0~3
}
else
{
return FALSE;
}
ioPhysicalBase.LowPart = S3C6410_BASE_REG_PA_GPIO;
ioPhysicalBase.HighPart = 0;
m_pIOPregs = (S3C6410_GPIO_REG *) MmMapIoSpace(ioPhysicalBase, sizeof(S3C6410_GPIO_REG),FALSE);
if (m_pIOPregs)
{
DDKISRINFO ddi;
if (GetIsrInfo(&ddi)== ERROR_SUCCESS &&
KernelIoControl(IOCTL_HAL_REQUEST_SYSINTR, &ddi.dwIrq, sizeof(UINT32), &ddi.dwSysintr, sizeof(UINT32), NULL))
{
RETAILMSG( FALSE, (TEXT("DEBUG: Serial1 SYSINTR : %d\r\n"), (PBYTE)&ddi.dwSysintr));
RegSetValueEx(DEVLOAD_SYSINTR_VALNAME,REG_DWORD,(PBYTE)&ddi.dwSysintr, sizeof(UINT32));
}
else
{
return FALSE;
}
#ifdef OMNIBOOK_VER
// TXD1(GPA5), RXD1(GPA4), (00)pull-up/down disabled
m_pIOPregs->GPACON = (m_pIOPregs->GPACON & ~(0xff<<16)) | (0x22<<16);
m_pIOPregs->GPAPUD = (m_pIOPregs->GPAPUD & ~(0xf<<8)) | (0x0<<8);
#else //!OMNIBOOK_VER
// TXD1(GPA5), RXD1(GPA4), RTS1(GPA7), CTS1(GPA6)
m_pIOPregs->GPACON &= ~(0xf<<16 | 0xf<<20 | 0xf<<24 | 0xf<<28);
m_pIOPregs->GPACON |= (0x2<<16 | 0x2<<20 | 0x2<<24 | 0x2<<28);
m_pIOPregs->GPAPUD &= ~(0x3<<8 | 0x3<<10 | 0x3<<12 | 0x3<<14);
#endif OMNIBOOK_VER
/* switch UART1 clock to EPLL to get access to higher baud rates */
CPdd6410Uart::SetClockSelect(UART_CS_EPLLCLK);
/* allow UART1 to use auto RTS/CTS flow control when requests by applications */
CPdd6410Uart::AllowAutoFlow(TRUE);
return CPdd6410Uart::Init();
}
return FALSE;
}
virtual BOOL Init()
{
PHYSICAL_ADDRESS ioPhysicalBase = { S3C6400_BASE_REG_PA_GPIO, 0};
ULONG inIoSpace = 0;
if (TranslateBusAddr(m_hParent,Internal,0, ioPhysicalBase,&inIoSpace,&ioPhysicalBase))
{
// Map it if it is Memeory Mapped IO.
m_pIOPregs = (S3C6400_GPIO_REG *)DrvLib_MapIoSpace(ioPhysicalBase.LowPart , sizeof(S3C6400_GPIO_REG),FALSE);
}
ioPhysicalBase.LowPart = S3C6400_BASE_REG_PA_SYSCON;
ioPhysicalBase.HighPart = 0;
if (TranslateBusAddr(m_hParent,Internal,0, ioPhysicalBase,&inIoSpace,&ioPhysicalBase))
{
m_pSysconRegs = (S3C6400_SYSCON_REG *) DrvLib_MapIoSpace(ioPhysicalBase.LowPart ,sizeof(S3C6400_SYSCON_REG),FALSE);
}
if(m_pSysconRegs)
{
m_pSysconRegs->PCLK_GATE |= (1<<1); // UART0
m_pSysconRegs->SCLK_GATE |= (1<<5); // UART0~3
}
if (m_pIOPregs)
{
DDKISRINFO ddi;
if (GetIsrInfo(&ddi)== ERROR_SUCCESS &&
KernelIoControl(IOCTL_HAL_REQUEST_SYSINTR, &ddi.dwIrq, sizeof(UINT32), &ddi.dwSysintr, sizeof(UINT32), NULL))
{
//RETAILMSG( TRUE, (TEXT("DEBUG: Serial0 SYSINTR : %d\r\n"), (PBYTE)&ddi.dwSysintr));
RegSetValueEx(DEVLOAD_SYSINTR_VALNAME,REG_DWORD,(PBYTE)&ddi.dwSysintr, sizeof(UINT32));
}
else
{
return FALSE;
}
m_pDTRPort = (volatile ULONG *)&(m_pIOPregs->GPNDAT);
m_pDSRPort = (volatile ULONG *)&(m_pIOPregs->GPNDAT);
m_dwDTRPortNum = 6;
m_dwDSRPortNum = 7;
// CTS0(GPA2), RTS0(GPA3), TXD0(GPA1), RXD0(GPA0)
m_pIOPregs->GPACON &= ~(0xf<<0 | 0xf<<4 | 0xf<<8 | 0xf<<12 ); ///< Clear Bit
m_pIOPregs->GPACON |= (0x2<<0 | 0x2<<4 | 0x2<<8 | 0x2<<12 ); ///< Select UART IP
m_pIOPregs->GPAPUD &= ~(0x3<<0 | 0x3<<2 | 0x3<<4 | 0x3<<6 ); ///< Pull-Up/Down Disable
// DTR0(GPN6), DSR0(GPN7)
// If you want to use COM1 port for ActiveSync, use these statements.
m_pIOPregs->GPNCON &= ~(0x3<<12); ///< DTR0 Clear Bit
m_pIOPregs->GPNCON |= (0x1<<12); ///< Output
m_pIOPregs->GPNPUD &= ~(0x3<<12); ///< Pull-Up/Down Disable
m_pIOPregs->GPNCON &= ~(0x3<<14); ///< DSR0 Clear Bit
m_pIOPregs->GPNCON |= (0x0<<14); ///< Input
m_pIOPregs->GPNPUD &= ~(0x3<<14); ///< Pull-Up/Down Disable
return CPdd6400Uart::Init();
}
return FALSE;
}
static BOOL InitializeIST()
{
BOOL r;
gMfcIntrEvent = CreateEvent(NULL, FALSE, FALSE, NULL);
if (!gMfcIntrEvent) {
ERRORMSG(1, (L"Unable to create interrupt event"));
return(FALSE);
}
if (!CreateInterruptNotification()) {
ERRORMSG(1, (L"Unable to create interrupt notification"));
CloseHandle(gMfcIntrEvent);
return FALSE;
}
r = KernelIoControl(IOCTL_HAL_REQUEST_SYSINTR,
&g_MfcIrq, sizeof(UINT32),
&g_MfcSysIntr, sizeof(UINT32),
NULL);
if (r != TRUE) {
ERRORMSG(1, (L"Failed to request sysintr value for MFC interrupt.\r\n"));
DeleteInterruptNotification();
CloseHandle(gMfcIntrEvent);
return FALSE;
}
r = InterruptInitialize(g_MfcSysIntr, gMfcIntrEvent, NULL, 0);
if (r != TRUE) {
ERRORMSG(1, (L"Unable to initialize output interrupt"));
DeleteInterruptNotification();
CloseHandle(gMfcIntrEvent);
return FALSE;
}
gMfcIntrThread = CreateThread((LPSECURITY_ATTRIBUTES)NULL,
0,
(LPTHREAD_START_ROUTINE)MFC_IntrThread,
0,
0,
NULL);
if (!gMfcIntrThread) {
ERRORMSG(1, (L"Unable to create interrupt thread"));
InterruptDisable(g_MfcSysIntr);
DeleteInterruptNotification();
CloseHandle(gMfcIntrEvent);
return FALSE;
}
// Bump up the priority since the interrupt must be serviced immediately.
CeSetThreadPriority(gMfcIntrThread, MFC_THREAD_PRIORITY_DEFAULT);
RETAILMSG(1, (L"MFC Interrupt has been initialized.\n"));
return TRUE;
}
void harness_deinit(void)
#define HAS_DEINIT
{
int res;
DWORD out;
res = KernelIoControl(IOCTL_HAL_RELEASE_SYSINTR,
&sysintr, sizeof(sysintr), NULL, 0, &out);
assert(res);
}
BOOL GetUUID (TCHAR* szClientHWID)
{
GUID myUUID;
BOOL bRetVal;
DWORD dwBytesReturned;
bRetVal = KernelIoControl (IOCTL_HAL_GET_UUID, NULL, 0, &myUUID,
sizeof (myUUID), &dwBytesReturned);
if (!bRetVal)
{
//MessageBox(NULL, L"KernelIoControl call failed!\r\n", L"getUUID", MB_OK | MB_TOPMOST | MB_SETFOREGROUND);
DEBUGMSG(1, (L"KernelIoControl call failed!\r\n"));
return FALSE;
}
TCHAR txt[MAX_PATH];
/*
[HKEY_LOCAL_MACHINE\Software\Microsoft\MSLicensing\HardwareID]
"ClientHWID"=hex(3):01,00,02,00,
00,40,05,6a,
0e,9d,
01,08,
00,20,
4f,ac,10,40,60,00
[HKEY_LOCAL_MACHINE\Software\Microsoft\Terminal Server Client]
"UUID"=hex(3):
00,40,05,6a,
0e,9d,
01,08,
00,20,
4f,ac,10,40,60,00
*/
// "6A054000-9D0E-0801-0020-4FAC10406000"
wsprintf(txt, L"UUID: \n%08X-%04X-%04X-%02X%02X-%02X%02X%02X%02X%02X%02X\r\n",
myUUID.Data1,
myUUID.Data2,
myUUID.Data3,
myUUID.Data4[0],
myUUID.Data4[1],
myUUID.Data4[2],
myUUID.Data4[3],
myUUID.Data4[4],
myUUID.Data4[5],
myUUID.Data4[6],
myUUID.Data4[7]);
RETAILMSG(
1,
(txt));
wsprintf(szClientHWID, txt);
//MessageBox(NULL, txt, L"getUUID", MB_OK | MB_TOPMOST | MB_SETFOREGROUND);
return TRUE;
}
//------------------------------------------------------------------------------
//
// Function: AllocatePMU
//
// Returns a handle identifying the PMU resource
// If PMU not available, returns 0.
//
PMUHandle WINAPI AllocatePMU(void (*pCallBack)(void))
{
PMUHandle handle = 0;
PMURegInfo PMURegBuffer;
BOOL rtnvalue = FALSE;
LPCTSTR semName = TEXT("XSC_PMU_ALLOC");
// Allocate a system resource, initialize to unsignalled state.
// If it's already allocated, return NULL handle.
//
trySemaphore = CreateSemaphore (NULL, 1, 1, semName);
if (trySemaphore == NULL)
{
return 0;
}
if (GetLastError() == ERROR_ALREADY_EXISTS)
{
//
// Invalidate this handle
//
CloseHandle(trySemaphore);
return 0;
}
semHandle = trySemaphore;
// Register callback with kernel
// NOTE: Intel no longer uses the pCallBack parameter that was stored in
// the PVTuneReleasePMU variable, it is understood to be NULL.
PMURegBuffer.subcode = PMU_ALLOCATE;
PMURegBuffer.pCallback = PVTuneReleasePMU;
rtnvalue =
KernelIoControl (IOCTL_PMU_CONFIG, (void *)&PMURegBuffer, sizeof(PMURegInfo),
(LPVOID)NULL, 0, (LPDWORD)NULL);
if (rtnvalue == FALSE)
{
return 0;
}
// Null other callbacks
//
PVTuneInterrupt = NULL;
PVTuneReleaseCCF = NULL;
// Allocate a PMUHandle
//
handle = (PMUHandle) malloc (sizeof (PMUHResource));
return handle;
}
//-----------------------------------------------------------------------------
//
// Function: SendRetentionVoltages
//
// Function that sends new retention voltages via KernelIOCTL
//
VOID
SendRetentionVoltages()
{
KernelIoControl(
IOCTL_UPDATE_RETENTION_VOLTAGES,
&s_KernIoCtlInfo,
sizeof(IOCTL_RETENTION_VOLTAGES),
NULL,
0,
NULL
);
}
// New function to request a SYSINTR for Card detect interrupt of HSMMC ch1 on SMDK6410.
BOOL CSDHControllerCh1::InitializeHardware() {
m_dwSDDetectIrq = SD_CD1_IRQ;
// convert the SDI hardware IRQ into a logical SYSINTR value
if (!KernelIoControl(IOCTL_HAL_REQUEST_SYSINTR, &m_dwSDDetectIrq, sizeof(DWORD), &m_dwSDDetectSysIntr, sizeof(DWORD), NULL)) {
// invalid SDDetect SYSINTR value!
RETAILMSG(1, (TEXT("[HSMMC1] invalid SD detect SYSINTR value!\n")));
m_dwSDDetectSysIntr = SYSINTR_UNDEFINED;
return FALSE;
}
return CSDHCBase::InitializeHardware();
}
void
GetDisplayResolutionFromBootArgs(
DWORD * pDispRes
)
{
DWORD dwKernelRet = 0;
if (!KernelIoControl(IOCTL_HAL_GET_DISPLAY_RES,
NULL, 0, pDispRes, sizeof(DWORD), &dwKernelRet))
{
RETAILMSG( TRUE,(TEXT("Failed to read Display resolution\r\n")));
return;
}
}
void
S3C6410Disp::InitializeDisplayMode()
{
DWORD dwDisplayType[2] = {123,16};
DWORD dwBytesRet = 0;
if (KernelIoControl(IOCTL_HAL_QUERY_DISPLAYSETTINGS, NULL, 0, dwDisplayType, sizeof(DWORD)*2, &dwBytesRet) // get data from BSP_ARGS via KernelIOCtl
&& (dwBytesRet == (sizeof(DWORD)*2)))
{
RETAILMSG(DISP_ZONE_ERROR,(TEXT("[DSPL_MODE] display driver display: %s\r\n"),LDI_getDisplayName((HITEG_DISPLAY_TYPE)dwDisplayType[0])));
LDI_set_LCD_module_type((HITEG_DISPLAY_TYPE)dwDisplayType[0]);
}
else
{
RETAILMSG(DISP_ZONE_ERROR,(TEXT("[DSPL_MODE] Error getting Display type from args section via Kernel IOCTL!!!\r\n")));
}
//Setup ModeInfoEx, ModeInfo
m_pModeEx = &m_ModeInfoEx;
m_pMode = &m_ModeInfoEx.modeInfo;
memset(m_pModeEx, 0, sizeof(GPEModeEx));
ULONG *gBitMasks=DrvGetMasks(NULL);
if(dwDisplayType[1]==16)
m_pModeEx->ePixelFormat = ddgpePixelFormat_565;
else if (dwDisplayType[1] >= 24 )
m_pModeEx->ePixelFormat = ddgpePixelFormat_8888;
else
m_pModeEx->ePixelFormat = ddgpePixelFormat_565; // fallback value if Bpp is unsupported
// Fill GPEMode modeInfo
m_pMode->modeId = 0;
m_pMode->width = m_nScreenWidth=LDI_GetDisplayWidth( LDI_getDisplayType() );
m_pMode->height = m_nScreenHeight=LDI_GetDisplayHeight( LDI_getDisplayType() );
m_pMode->format = EDDGPEPixelFormatToEGPEFormat[m_pModeEx->ePixelFormat];
m_pMode->Bpp = EGPEFormatToBpp[m_pMode->format];
m_pMode->frequency = 60; // Usually LCD Panel require 60Hz
// Fill DDGPEStandardHeader
m_pModeEx->dwSize = sizeof(GPEModeEx);
m_pModeEx->dwVersion = GPEMODEEX_CURRENTVERSION;
// Fill ModeInfoEX
m_pModeEx->dwPixelFourCC = 0; // Should be Zero
m_pModeEx->dwPixelFormatData = 0; // Don't care
m_pModeEx->lPitch = m_dwDeviceScreenWidth*(m_pMode->Bpp/8);
m_pModeEx->dwFlags = 0; // Should be Zero
m_pModeEx->dwRBitMask = gBitMasks[0];
m_pModeEx->dwGBitMask = gBitMasks[1];
m_pModeEx->dwBBitMask = gBitMasks[2];
m_pModeEx->dwAlphaBitMask = 0x00000000;
}
void
ACAudioHWContext::SetControllerClocks(BOOL fOn)
{
DEBUGMSG(ZONE_AC,(L"AC: SetControllerClocks (%x)\r\n", fOn));
DWORD regBit, cbRet;
if (fOn)
{
// enable the McBSP clocks
regBit = AUDIO_PRCM_FCLKEN_MCBSP;
KernelIoControl(IOCTL_FCLK1_ENB, (VOID *)®Bit, sizeof(DWORD), NULL, 0, &cbRet);
regBit = AUDIO_PRCM_ICLKEN_MCBSP;
KernelIoControl(IOCTL_ICLK1_ENB, (VOID *)®Bit, sizeof(DWORD), NULL, 0, &cbRet);
}
else
{
// disable the McBSP clocks
regBit = AUDIO_PRCM_FCLKEN_MCBSP;
KernelIoControl(IOCTL_FCLK1_DIS, (VOID *)®Bit, sizeof(DWORD), NULL, 0, &cbRet);
regBit = AUDIO_PRCM_ICLKEN_MCBSP;
KernelIoControl(IOCTL_ICLK1_DIS, (VOID *)®Bit, sizeof(DWORD), NULL, 0, &cbRet);
}
}
//-----------------------------------------------------------------------------
//
// Function: EnableSmartReflex
//
// Function that sends SmartReflex KernelIOCTL
//
VOID
EnableSmartReflex(
BOOL bEnable
)
{
KernelIoControl(
IOCTL_SMARTREFLEX_CONTROL,
&bEnable,
sizeof(BOOL),
NULL,
0,
NULL
);
RETAILMSG(ZONE_INFO,(L"SmartReflexPolicy: EnableSmartReflex(%d)",bEnable));
}
