/**
* @brief Return PLL clock frequency used for system domain
* @retval PLL clock frequency (in Hz)
*/
uint32_t RCC_PLL_GetFreqDomain_SYS(void)
{
uint32_t pllinputfreq = 0U, pllsource = 0U;
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL divider) * PLL Multiplicator */
/* Get PLL source */
pllsource = LL_RCC_PLL_GetMainSource();
switch (pllsource)
{
case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
pllinputfreq = HSI_VALUE;
break;
case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
pllinputfreq = HSE_VALUE;
break;
default:
pllinputfreq = HSI_VALUE;
break;
}
return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator(), LL_RCC_PLL_GetDivider());
}
/**
* @brief Return PLLI2S clock frequency used for SPDIFRX domain
* @retval PLLI2S clock frequency (in Hz)
*/
uint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void)
{
uint32_t pllinputfreq = 0U, pllsource = 0U;
/* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLI2SN
SPDIFRX Domain clock = PLLI2S_VCO / PLLI2SP
*/
pllsource = LL_RCC_PLL_GetMainSource();
switch (pllsource)
{
case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
pllinputfreq = HSI_VALUE;
break;
case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
pllinputfreq = HSE_VALUE;
break;
default:
pllinputfreq = HSI_VALUE;
break;
}
return __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetP());
}
/**
* @brief Return PLLI2S clock frequency used for SAI1 and SAI2 domains
* @retval PLLI2S clock frequency (in Hz)
*/
uint32_t RCC_PLLI2S_GetFreqDomain_SAI(void)
{
uint32_t pllinputfreq = 0U, pllsource = 0U;
/* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLI2SN
SAI1 and SAI2 domains clock = (PLLI2S_VCO / PLLI2SQ) / PLLI2SDIVQ
*/
pllsource = LL_RCC_PLL_GetMainSource();
switch (pllsource)
{
case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
pllinputfreq = HSI_VALUE;
break;
case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
pllinputfreq = HSE_VALUE;
break;
default:
pllinputfreq = HSI_VALUE;
break;
}
return __LL_RCC_CALC_PLLI2S_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetQ(), LL_RCC_PLLI2S_GetDIVQ());
}
/**
* @brief Return PLLSAI clock frequency used for LTDC domain
* @retval PLLSAI clock frequency (in Hz)
*/
uint32_t RCC_PLLSAI_GetFreqDomain_LTDC(void)
{
uint32_t pllinputfreq = 0U, pllsource = 0U;
/* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLSAIN
LTDC Domain clock = (PLLSAI_VCO / PLLSAIR) / PLLSAIDIVR
*/
pllsource = LL_RCC_PLL_GetMainSource();
switch (pllsource)
{
case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */
pllinputfreq = HSI_VALUE;
break;
case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */
pllinputfreq = HSE_VALUE;
break;
default:
pllinputfreq = HSI_VALUE;
break;
}
return __LL_RCC_CALC_PLLSAI_LTDC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetR(), LL_RCC_PLLSAI_GetDIVR());
}
/**
* @brief Return PLL clock frequency used for 48 MHz domain
* @retval PLL clock frequency (in Hz)
*/
uint32_t RCC_PLL_GetFreqDomain_48M(void)
{
uint32_t pllinputfreq = 0U, pllsource = 0U;
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM ) * PLLN
48M Domain clock = PLL_VCO / PLLQ
*/
pllsource = LL_RCC_PLL_GetMainSource();
switch (pllsource)
{
case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
pllinputfreq = HSI_VALUE;
break;
case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
pllinputfreq = HSE_VALUE;
break;
default:
pllinputfreq = HSI_VALUE;
break;
}
return __LL_RCC_CALC_PLLCLK_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ());
}
/**
* @brief Return PLLSAI2 clock frequency used for ADC domain
* @retval PLLSAI2 clock frequency (in Hz)
*/
uint32_t RCC_PLLSAI2_GetFreqDomain_ADC(void)
{
uint32_t pllinputfreq = 0, pllsource = 0;
/* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI2N
48M Domain clock = PLLSAI2_VCO / PLLSAI2R
*/
pllsource = LL_RCC_PLL_GetMainSource();
switch (pllsource)
{
case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI2 clock source */
pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
(LL_RCC_MSI_IsEnabledRangeSelect() ?
LL_RCC_MSI_GetRange() :
LL_RCC_MSI_GetRangeAfterStandby()));
break;
case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI2 clock source */
pllinputfreq = HSI_VALUE;
break;
case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI2 clock source */
pllinputfreq = HSE_VALUE;
break;
default:
pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
(LL_RCC_MSI_IsEnabledRangeSelect() ?
LL_RCC_MSI_GetRange() :
LL_RCC_MSI_GetRangeAfterStandby()));
break;
}
return __LL_RCC_CALC_PLLSAI2_ADC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetR());
}
