static int condpass(Instr i, ulong psr) { uchar n = COND_N(psr); uchar z = COND_Z(psr); uchar c = COND_C(psr); uchar v = COND_V(psr); switch(LSR(i,28)) { case 0: return z; case 1: return !z; case 2: return c; case 3: return !c; case 4: return n; case 5: return !n; case 6: return v; case 7: return !v; case 8: return c && !z; case 9: return !c || z; case 10: return n == v; case 11: return n != v; case 12: return !z && (n == v); case 13: return z && (n != v); case 14: return 1; case 15: return 0; } }
static void uart_init_line(int port, unsigned long baud) { int i, baudconst; switch (baud) { case 115200: baudconst = 1; break; case 57600: baudconst = 2; break; case 38400: baudconst = 3; break; case 19200: baudconst = 6; break; case 9600: default: baudconst = 12; break; } outb(0x87, LCR(port)); outb(0x00, DLM(port)); outb(baudconst, DLL(port)); outb(0x07, LCR(port)); outb(0x0f, MCR(port)); for (i = 10; i > 0; i--) { if (inb(LSR(port)) == (unsigned int) 0) break; inb(RBR(port)); } }
static void uart_port_putchar(int port, unsigned char c) { if (c == '\n') uart_port_putchar(port, '\r'); while (!(inb(LSR(port)) & 0x20)); outb(c, THR(port)); }
static int yam_open(struct net_device *dev) { struct yam_port *yp = netdev_priv(dev); enum uart u; int i; int ret=0; printk(KERN_INFO "Trying %s at iobase 0x%lx irq %u\n", dev->name, dev->base_addr, dev->irq); if (!yp->bitrate) return -ENXIO; if (!dev->base_addr || dev->base_addr > 0x1000 - YAM_EXTENT || dev->irq < 2 || dev->irq > 15) { return -ENXIO; } if (!request_region(dev->base_addr, YAM_EXTENT, dev->name)) { printk(KERN_ERR "%s: cannot 0x%lx busy\n", dev->name, dev->base_addr); return -EACCES; } if ((u = yam_check_uart(dev->base_addr)) == c_uart_unknown) { printk(KERN_ERR "%s: cannot find uart type\n", dev->name); ret = -EIO; goto out_release_base; } if (fpga_download(dev->base_addr, yp->bitrate)) { printk(KERN_ERR "%s: cannot init FPGA\n", dev->name); ret = -EIO; goto out_release_base; } outb(0, IER(dev->base_addr)); if (request_irq(dev->irq, yam_interrupt, IRQF_SHARED, dev->name, dev)) { printk(KERN_ERR "%s: irq %d busy\n", dev->name, dev->irq); ret = -EBUSY; goto out_release_base; } yam_set_uart(dev); netif_start_queue(dev); yp->slotcnt = yp->slot / 10; /* Reset overruns for all ports - FPGA programming makes overruns */ for (i = 0; i < NR_PORTS; i++) { struct net_device *yam_dev = yam_devs[i]; inb(LSR(yam_dev->base_addr)); yam_dev->stats.rx_fifo_errors = 0; } printk(KERN_INFO "%s at iobase 0x%lx irq %u uart %s\n", dev->name, dev->base_addr, dev->irq, uart_str[u]); return 0; out_release_base: release_region(dev->base_addr, YAM_EXTENT); return ret; }
void Apu4B() { // LSR dp uint8_t Work8 = S9xAPUGetByteZ(OP1); LSR(Work8); S9xAPUSetByteZ(Work8, OP1); IAPU.PC += 2; }
void Apu5B() { // LSR dp+X uint8_t Work8 = S9xAPUGetByteZ(OP1 + IAPU.Registers.X); LSR(Work8); S9xAPUSetByteZ(Work8, OP1 + IAPU.Registers.X); IAPU.PC += 2; }
void Apu4C() { // LSR abs Absolute(); uint8_t Work8 = S9xAPUGetByte(IAPU.Address); LSR(Work8); S9xAPUSetByte(Work8, IAPU.Address); IAPU.PC += 3; }
void _lsrZpx(void) { byte zaddr; zaddr = fetch_byte((word)(cpu.pc + 1)); LSR((word)(zaddr + cpu.x)); cpu.pc += 2; }
void _lsrZp(void) { byte zaddr; zaddr = fetch_byte((word)(cpu.pc + 1)); LSR(zaddr); cpu.pc += 2; }
void _lsrAbx(void) { word addr; addr = fetch_word((word)(cpu.pc + 1)); LSR((word)(addr + cpu.x)); cpu.pc += 3; }
void _lsrAbsl(void) { word addr; addr = fetch_word((word)(cpu.pc + 1)); LSR(addr); cpu.pc += 3; }
/* * Output a single byte to the serial port. */ void serial_putc (const char c) { /* wait for room in the tx FIFO on UART */ while ((LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_TEMT) == 0); THR(CONFIG_SYS_IXP425_CONSOLE) = c; /* If \n, also do \r */ if (c == '\n') serial_putc ('\r'); }
static irqreturn_t yam_interrupt(int irq, void *dev_id) { struct net_device *dev; struct yam_port *yp; unsigned char iir; int counter = 100; int i; int handled = 0; for (i = 0; i < NR_PORTS; i++) { dev = yam_devs[i]; yp = netdev_priv(dev); if (!netif_running(dev)) continue; while ((iir = IIR_MASK & inb(IIR(dev->base_addr))) != IIR_NOPEND) { unsigned char msr = inb(MSR(dev->base_addr)); unsigned char lsr = inb(LSR(dev->base_addr)); unsigned char rxb; handled = 1; if (lsr & LSR_OE) ++dev->stats.rx_fifo_errors; yp->dcd = (msr & RX_DCD) ? 1 : 0; if (--counter <= 0) { printk(KERN_ERR "%s: too many irq iir=%d\n", dev->name, iir); goto out; } if (msr & TX_RDY) { ++yp->nb_mdint; yam_tx_byte(dev, yp); } if (lsr & LSR_RXC) { ++yp->nb_rxint; rxb = inb(RBR(dev->base_addr)); if (msr & RX_FLAG) yam_rx_flag(dev, yp); else yam_rx_byte(dev, yp, rxb); } } } out: return IRQ_RETVAL(handled); }
static void fpga_reset(int iobase) { outb(0, IER(iobase)); outb(LCR_DLAB | LCR_BIT5, LCR(iobase)); outb(1, DLL(iobase)); outb(0, DLM(iobase)); outb(LCR_BIT5, LCR(iobase)); inb(LSR(iobase)); inb(MSR(iobase)); /* turn off FPGA supply voltage */ outb(MCR_OUT1 | MCR_OUT2, MCR(iobase)); delay(100); /* turn on FPGA supply voltage again */ outb(MCR_DTR | MCR_RTS | MCR_OUT1 | MCR_OUT2, MCR(iobase)); delay(100); }
static int fpga_write(int iobase, unsigned char wrd) { unsigned char bit; int k; unsigned long timeout = jiffies + HZ / 10; for (k = 0; k < 8; k++) { bit = (wrd & 0x80) ? (MCR_RTS | MCR_DTR) : MCR_DTR; outb(bit | MCR_OUT1 | MCR_OUT2, MCR(iobase)); wrd <<= 1; outb(0xfc, THR(iobase)); while ((inb(LSR(iobase)) & LSR_TSRE) == 0) if (time_after(jiffies, timeout)) return -1; } return 0; }
irqreturn_t serial_interrupt_handle(int irq_no, void *dev_id) { struct serial_dev *dev = (struct serial_dev *) dev_id; unsigned char iir, ch = 0, i; iir = inb(IIR(dev->base_port)); //printk(LOG_LEVEL "[serial interrupt handle] read IIR = %d", (int) iir); if (IIR_RDAI(iir)) { // Dezactivez întreruperea RDAI - read outb(inb(IER(dev->base_port)) & ~IER_RDAI, IER(dev->base_port)); //printk(LOG_LEVEL "[serial interrupt handle] reading data..."); while (inb(LSR(dev->base_port)) & 0x01) { ch = inb(dev->base_port); dev->read_buffer[dev->read++] = ch; } atomic_set(&dev->read_ready, 1); wake_up(&dev->wq_reads); //printk(LOG_LEVEL "[serial interrupt handle] wake up read()"); } if (IIR_THREI(iir)) { // Dezactivez întreruperea THREI - write outb(inb(IER(dev->base_port)) & ~IER_THREI, IER(dev->base_port)); //printk(LOG_LEVEL "[serial interrupt handle] writing data..."); for (i = 0; i < dev->write; i++) outb(dev->write_buffer[i], dev->base_port); atomic_set(&dev->write_ready, 0); wake_up(&dev->wq_writes); //printk(LOG_LEVEL "[serial interrupt handle] wake up write()"); } return IRQ_HANDLED; }
void position_decide() { float a[sample_num]; float error[sample_num]; for(int i=0;i<sample_num;++i) { myQueue.Get(&a[i]); } int min=0; for(int j=0;j<position_num;++j) { error[j]=LSR(a,s[j]); } for(int j=0;j<position_num;++j) { if(error[j]<error[min]) { min=j; } } pos=min; }
void decodeInstruction(instruction_t instruction, uint32_t *dir_reg, char *dir_flags, uint8_t *SRAM, uint16_t *dec) { uint8_t *R_activos=instruction.registers_list; /* Comparacion de mnemonic y Llamado de las funciones */ if( strcmp(instruction.mnemonic,"ADC") == 0 || strcmp(instruction.mnemonic,"ADCS") == 0){ dir_reg[PC]++; *dec=16704; *dec=*dec|instruction.op3_value<<3|instruction.op1_value; dir_reg[instruction.op1_value]=ADC(dir_reg[instruction.op2_value],dir_reg[instruction.op3_value],dir_flags); } if( strcmp(instruction.mnemonic,"ADDS") == 0 || strcmp(instruction.mnemonic,"ADD") == 0){ dir_reg[PC]++; if(instruction.op2_type=='S'){ *dec=45056; dir_reg[SP]=ADD(dir_reg[SP],instruction.op3_value,dir_flags); *dec=*dec|instruction.op3_value;} else if(instruction.op3_type=='#'){ *dec=7168; *dec=*dec|instruction.op3_value<<6|instruction.op2_value<<3|instruction.op1_value; dir_reg[instruction.op1_value]=ADD(dir_reg[instruction.op2_value], instruction.op3_value,dir_flags); mvprintw(4,20,"%X",*dec);} else{ *dec=6144; *dec=*dec|instruction.op3_value<<6|instruction.op2_value<<3|instruction.op1_value; dir_reg[instruction.op1_value]=ADD(dir_reg[instruction.op2_value],dir_reg[instruction.op3_value],dir_flags);} } if( strcmp(instruction.mnemonic,"AND") == 0 || strcmp(instruction.mnemonic,"ANDS") == 0){ dir_reg[PC]++; *dec=16384; if(instruction.op3_type=='#'){ dir_reg[instruction.op1_value]=AND(dir_reg[instruction.op2_value],instruction.op3_value,dir_flags);} else dir_reg[instruction.op1_value]=AND(dir_reg[instruction.op2_value],dir_reg[instruction.op3_value],dir_flags); } if( strcmp(instruction.mnemonic,"ASR") == 0 || strcmp(instruction.mnemonic,"ASRS") == 0){ dir_reg[PC]++; if(instruction.op3_type=='#'){ *dec=4096; *dec=*dec|instruction.op3_value<<6|instruction.op2_value<<3|instruction.op1_value; dir_reg[instruction.op1_value]=ASR(dir_reg[instruction.op2_value],instruction.op3_value,dir_flags);} else{ *dec=16640; *dec=*dec|instruction.op3_value<<3|instruction.op1_value; dir_reg[instruction.op1_value]=ASR(dir_reg[instruction.op2_value],dir_reg[instruction.op3_value],dir_flags);} } if( strcmp(instruction.mnemonic,"BICS") == 0 || strcmp(instruction.mnemonic,"BICS") == 0){ dir_reg[PC]++; if(instruction.op3_type=='#') dir_reg[instruction.op1_value]=BIC(dir_reg[instruction.op2_value],instruction.op3_value,dir_flags); else{ *dec=17280; dir_reg[instruction.op1_value]=BIC(dir_reg[instruction.op2_value],dir_reg[instruction.op3_value],dir_flags); *dec=*dec|instruction.op3_value<<3|instruction.op1_value;} } if( strcmp(instruction.mnemonic,"CMN" ) == 0 || strcmp(instruction.mnemonic,"CMNS") == 0){ dir_reg[PC]++; CMN(dir_reg[instruction.op1_value], dir_reg[instruction.op2_value],dir_flags); *dec=17088; *dec=*dec|instruction.op2_value<<3|instruction.op1_value; mvprintw(4,20,"%X",*dec); } if( strcmp(instruction.mnemonic,"CMP") == 0 || strcmp(instruction.mnemonic,"CMPS") == 0){ dir_reg[PC]++; CMP(dir_reg[instruction.op1_value],dir_reg[instruction.op2_value],dir_flags); *dec=17024; *dec=*dec|instruction.op2_value<<3|instruction.op1_value; mvprintw(4,20,"%X",*dec); } if( strcmp(instruction.mnemonic,"EOR") == 0 || strcmp(instruction.mnemonic,"EORS") == 0){ dir_reg[PC]++; *dec=16448; if(instruction.op3_type=='#') dir_reg[instruction.op1_value]=EOR(dir_reg[instruction.op2_value],instruction.op3_value,dir_flags); else dir_reg[instruction.op1_value]=EOR(dir_reg[instruction.op2_value],dir_reg[instruction.op3_value],dir_flags); } if( strcmp(instruction.mnemonic,"LSLS") == 0 || strcmp(instruction.mnemonic,"LSL") == 0){ dir_reg[PC]++; if(instruction.op3_type=='#'){ *dec=0; dir_reg[instruction.op1_value]=LSL(dir_reg[instruction.op2_value],instruction.op3_value,dir_flags); *dec=*dec|instruction.op3_value<<6|instruction.op2_value<<3|instruction.op1_value;} else{ *dec=16512; dir_reg[instruction.op1_value]=LSL(dir_reg[instruction.op2_value],dir_reg[instruction.op3_value],dir_flags); *dec=*dec|instruction.op3_value<<3|instruction.op1_value;} } if( strcmp(instruction.mnemonic,"LSRS") == 0 || strcmp(instruction.mnemonic,"LSR") == 0){ dir_reg[PC]++; if(instruction.op3_type=='#'){ *dec=2048; dir_reg[instruction.op1_value]=LSR(dir_reg[instruction.op2_value],instruction.op3_value,dir_flags); *dec=*dec|instruction.op3_value<<6|instruction.op2_value<<3|instruction.op1_value;} else{ *dec=16576; dir_reg[instruction.op1_value]=LSR(dir_reg[instruction.op2_value],dir_reg[instruction.op3_value],dir_flags); *dec=*dec|instruction.op3_value<<3|instruction.op1_value;} } if( strcmp(instruction.mnemonic,"MOV") == 0 || strcmp(instruction.mnemonic,"MOVS") == 0){ dir_reg[PC]++; if(instruction.op2_type=='#'){ *dec=8192; dir_reg[instruction.op1_value]=MOV(instruction.op2_value,dir_flags); *dec=*dec|instruction.op1_value<<8|instruction.op2_value;} else{ *dec=0; dir_reg[instruction.op1_value]=MOV(dir_reg[instruction.op2_value],dir_flags); *dec=*dec|instruction.op2_value<<3|instruction.op1_value;} } if( strcmp(instruction.mnemonic,"MUL") == 0 || strcmp(instruction.mnemonic,"MULS") == 0){ dir_reg[PC]++; *dec=17216; if(instruction.op3_type=='#'){ dir_reg[instruction.op1_value]=MUL(dir_reg[instruction.op2_value],instruction.op3_value,dir_flags);} else{ dir_reg[instruction.op1_value]=MUL(dir_reg[instruction.op2_value],dir_reg[instruction.op3_value],dir_flags); *dec=*dec|instruction.op2_value<<3|instruction.op1_value;} } if( strcmp(instruction.mnemonic,"MVN") == 0 || strcmp(instruction.mnemonic,"MVNS") == 0){ dir_reg[PC]++; *dec=17344; dir_reg[instruction.op1_value]=MVN(dir_reg[instruction.op2_value], dir_flags); *dec=*dec|instruction.op2_value<<3|instruction.op1_value; } if( strcmp(instruction.mnemonic,"ORR") == 0 || strcmp(instruction.mnemonic,"ORRS") == 0){ dir_reg[PC]++; *dec=17152; if(instruction.op3_type=='#'){ dir_reg[instruction.op1_value]=ORR(dir_reg[instruction.op2_value],instruction.op3_value,dir_flags);} else{ dir_reg[instruction.op1_value]=ORR(dir_reg[instruction.op2_value],dir_reg[instruction.op3_value],dir_flags); *dec=*dec|instruction.op3_value<<3|instruction.op1_value;} } if( strcmp(instruction.mnemonic,"REV") == 0 || strcmp(instruction.mnemonic,"REVS") == 0){ dir_reg[PC]++; *dec=47616; dir_reg[instruction.op1_value]=REV(dir_reg[instruction.op2_value]); *dec=*dec|instruction.op2_value<<3|instruction.op1_value; } if( strcmp(instruction.mnemonic,"REVG") == 0 || strcmp(instruction.mnemonic,"REVGS") == 0){ dir_reg[PC]++; *dec=47680; dir_reg[instruction.op1_value]=REVG(dir_reg[instruction.op2_value]); *dec=*dec|instruction.op2_value<<3|instruction.op1_value; } if( strcmp(instruction.mnemonic,"REVSH") == 0 || strcmp(instruction.mnemonic,"REVSHS") == 0){ dir_reg[PC]++; *dec=47808; dir_reg[instruction.op1_value]=REVSH(dir_reg[instruction.op2_value]); *dec=*dec|instruction.op2_value<<3|instruction.op1_value; } if( strcmp(instruction.mnemonic,"ROR") == 0 || strcmp(instruction.mnemonic,"RORS") == 0){ dir_reg[PC]++; *dec=16832; if(instruction.op3_type=='#'){ dir_reg[instruction.op1_value]=ROR(dir_reg[instruction.op2_value],instruction.op3_value,dir_flags);} else{ dir_reg[instruction.op1_value]=ROR(dir_reg[instruction.op2_value],dir_reg[instruction.op3_value],dir_flags); *dec=*dec|instruction.op3_value<<3|instruction.op1_value;} } if( strcmp(instruction.mnemonic,"RSB") == 0 || strcmp(instruction.mnemonic,"RSBS") == 0){ dir_reg[PC]++; *dec=16690; dir_reg[instruction.op1_value]=RSB(dir_reg[instruction.op2_value], dir_flags); *dec=*dec|instruction.op2_value<<3|instruction.op1_value; } if( strcmp(instruction.mnemonic,"SBC") == 0 || strcmp(instruction.mnemonic,"SBCS") == 0){ dir_reg[PC]++; *dec=16768; SBC(dir_reg[instruction.op1_value],dir_reg[instruction.op2_value], dir_flags); *dec=*dec|instruction.op2_value<<3|instruction.op1_value; } if( strcmp(instruction.mnemonic,"SUBS") == 0 || strcmp(instruction.mnemonic,"SUB") == 0){ dir_reg[PC]++; if(instruction.op2_type=='S'){ *dec=45184; dir_reg[SP]=SUB(dir_reg[SP],instruction.op3_value,dir_flags); *dec=*dec|instruction.op3_value;} else if(instruction.op3_type=='#'){ *dec=7680; dir_reg[instruction.op1_value]=SUB(dir_reg[instruction.op2_value],instruction.op3_value,dir_flags); *dec=*dec|instruction.op3_value<<6|instruction.op2_value<<3|instruction.op1_value;} else{ *dec=6656; dir_reg[instruction.op1_value]=SUB(dir_reg[instruction.op2_value],dir_reg[instruction.op3_value],dir_flags); *dec=*dec|instruction.op3_value<<6|instruction.op2_value<<3|instruction.op1_value;} } if( strcmp(instruction.mnemonic,"TST") == 0 || strcmp(instruction.mnemonic,"TSTS") == 0){ dir_reg[PC]++; *dec=16896; TST(dir_reg[instruction.op1_value], dir_reg[instruction.op2_value], dir_flags); *dec=*dec|instruction.op2_value<<3|instruction.op1_value; } if( strcmp(instruction.mnemonic,"NOP") == 0 ){ NOP(dir_reg); *dec=48896; } if( strcmp(instruction.mnemonic,"B") == 0 ){ *dec=57344; *dec=*dec|instruction.op1_value; B(instruction.op1_value, dir_reg); } if( strcmp(instruction.mnemonic,"BL") == 0 ){ *dec=0; BL(instruction.op1_value, dir_reg); } if( strcmp(instruction.mnemonic,"BX") == 0 ){ *dec=18176; BX(dir_reg); } if( strcmp(instruction.mnemonic,"BEQ") == 0 ){ *dec=0; BEQ(instruction.op1_value, dir_reg, dir_flags); } if( strcmp(instruction.mnemonic,"BNE") == 0 ){ *dec=0; BNE(instruction.op1_value, dir_reg, dir_flags); } if( strcmp(instruction.mnemonic,"BCS") == 0 ){ *dec=0; BCS(instruction.op1_value, dir_reg, dir_flags); } if( strcmp(instruction.mnemonic,"BCC") == 0 ){ *dec=0; BCC(instruction.op1_value, dir_reg, dir_flags); } if( strcmp(instruction.mnemonic,"BMI") == 0 ){ *dec=0; BMI(instruction.op1_value, dir_reg, dir_flags); } if( strcmp(instruction.mnemonic,"BPL") == 0 ){ *dec=0; BPL(instruction.op1_value, dir_reg, dir_flags); } if( strcmp(instruction.mnemonic,"BVS") == 0 ){ *dec=0; BVS(instruction.op1_value, dir_reg, dir_flags); } if( strcmp(instruction.mnemonic,"BVC") == 0 ){ *dec=0; BVC(instruction.op1_value, dir_reg, dir_flags); } if( strcmp(instruction.mnemonic,"BHI") == 0 ){ *dec=0; BHI(instruction.op1_value, dir_reg, dir_flags); } if( strcmp(instruction.mnemonic,"BLS") == 0 ){ *dec=0; BLS(instruction.op1_value, dir_reg, dir_flags); } if( strcmp(instruction.mnemonic,"BGE") == 0 ){ *dec=0; BGE(instruction.op1_value, dir_reg, dir_flags); } if( strcmp(instruction.mnemonic,"BLT") == 0 ){ *dec=0; BLT(instruction.op1_value, dir_reg, dir_flags); } if( strcmp(instruction.mnemonic,"BGT") == 0 ){ *dec=0; BGT(instruction.op1_value, dir_reg, dir_flags); } if( strcmp(instruction.mnemonic,"BLE") == 0 ){ *dec=0; BLE(instruction.op1_value, dir_reg, dir_flags); } if( strcmp(instruction.mnemonic,"BAL") == 0 ){ *dec=0; BAL(instruction.op1_value, dir_reg); } if(strcmp(instruction.mnemonic,"PUSH")==0){ dir_reg[PC]++; *dec=46080; PUSH(SRAM, dir_reg,R_activos); } if(strcmp(instruction.mnemonic,"POP")==0){ dir_reg[PC]++; *dec=48128; POP(SRAM,dir_reg,R_activos); } data=(uint8_t)dir_reg[instruction.op1_value]; if(strcmp(instruction.mnemonic,"LDR")==0){ dir_reg[PC]++; if(instruction.op2_type=='=' && instruction.op3_type=='N'){ *dec=0; dir_reg[instruction.op1_value]=instruction.op2_value;} else if(instruction.op2_type=='S'){ *dec=38912; dir_reg[instruction.op1_value]=LDR(dir_reg[SP], instruction.op3_value<<2, SRAM); *dec=*dec|instruction.op3_value|instruction.op1_value<<8;} else if(instruction.op3_type=='#' || instruction.op3_type=='N'){ *dec=26624; if((dir_reg[instruction.op2_value]+(instruction.op3_value<<2))>=0x40000000) IOAccess((uint8_t)(dir_reg[instruction.op2_value]+(instruction.op3_value<<2)), &data,Read); else dir_reg[instruction.op1_value]=LDR(dir_reg[instruction.op2_value], instruction.op3_value<<2, SRAM); *dec=*dec|instruction.op3_value<<6|instruction.op2_value|instruction.op1_value;} else{ *dec=22528; if((dir_reg[instruction.op2_value]+dir_reg[instruction.op3_value])>=0x40000000) IOAccess((uint8_t)(dir_reg[instruction.op2_value]+dir_reg[instruction.op3_value]), &data,Read); else dir_reg[instruction.op1_value]=LDR(dir_reg[instruction.op2_value], dir_reg[instruction.op3_value], SRAM); *dec=*dec|instruction.op3_value<<6|instruction.op2_value<<3|instruction.op1_value;} } if(strcmp(instruction.mnemonic,"LDRB")==0){ dir_reg[PC]++; if(instruction.op3_type=='#' || instruction.op3_type=='N'){ *dec=30720; if((dir_reg[instruction.op2_value]+instruction.op3_value)>=0x40000000) IOAccess((uint8_t)(dir_reg[instruction.op2_value]+instruction.op3_value), &data,Read); else dir_reg[instruction.op1_value]=LDRB(dir_reg[instruction.op2_value], instruction.op3_value, SRAM); *dec=*dec|instruction.op3_value<<6|instruction.op2_value<<3|instruction.op1_value;} else{ *dec=23552; if((dir_reg[instruction.op2_value]+dir_reg[instruction.op3_value])>=0x40000000) IOAccess((uint8_t)(dir_reg[instruction.op2_value]+dir_reg[instruction.op3_value]), &data,Read); else dir_reg[instruction.op1_value]=LDRB(dir_reg[instruction.op2_value], dir_reg[instruction.op3_value], SRAM); *dec=*dec|instruction.op3_value<<6|instruction.op2_value<<3|instruction.op1_value;} } if(strcmp(instruction.mnemonic,"LDRH")==0){ dir_reg[PC]++; if(instruction.op3_type=='#' || instruction.op3_type=='N'){ *dec=34816; if((dir_reg[instruction.op2_value]+(instruction.op3_value<<1))>=0x40000000) IOAccess((uint8_t)(dir_reg[instruction.op2_value]+(instruction.op3_value<<1)), &data,Read); else dir_reg[instruction.op1_value]=LDRH(dir_reg[instruction.op2_value], instruction.op3_value<<1, SRAM); *dec=*dec|instruction.op3_value<<6|instruction.op2_value<<3|instruction.op1_value;} else{ *dec=23040; if((dir_reg[instruction.op2_value]+dir_reg[instruction.op3_value])>=0x40000000) IOAccess((uint8_t)(dir_reg[instruction.op2_value]+dir_reg[instruction.op3_value]), &data,Read); else dir_reg[instruction.op1_value]=LDRH(dir_reg[instruction.op2_value], dir_reg[instruction.op3_value], SRAM); *dec=*dec|instruction.op3_value<<6|instruction.op2_value<<3|instruction.op1_value;} } if(strcmp(instruction.mnemonic,"LDRSB")==0){ dir_reg[PC]++; *dec=22016; *dec=*dec|instruction.op3_value<<6|instruction.op2_value<<3|instruction.op1_value; if((dir_reg[instruction.op2_value]+dir_reg[instruction.op3_value])>=0x40000000) IOAccess((uint8_t)(dir_reg[instruction.op2_value]+dir_reg[instruction.op3_value]), &data,Read); else dir_reg[instruction.op1_value]=LDRSB(dir_reg[instruction.op2_value], dir_reg[instruction.op3_value], SRAM); } if(strcmp(instruction.mnemonic,"LDRSH")==0){ dir_reg[PC]++; *dec=24064; *dec=*dec|instruction.op3_value<<6|instruction.op2_value<<3|instruction.op1_value; if((dir_reg[instruction.op2_value]+dir_reg[instruction.op3_value])>=0x40000000) IOAccess((uint8_t)(dir_reg[instruction.op2_value]+dir_reg[instruction.op3_value]), &data,Read); else dir_reg[instruction.op1_value]=LDRSH(dir_reg[instruction.op2_value], dir_reg[instruction.op3_value], SRAM); } if(strcmp(instruction.mnemonic,"STR")==0){ dir_reg[PC]++; if(instruction.op2_type=='S'){ *dec=38912; STR(dir_reg[instruction.op1_value],dir_reg[SP], instruction.op3_value<<2, SRAM); *dec=*dec|instruction.op3_value|instruction.op1_value<<8;} else if(instruction.op3_type=='#' || instruction.op3_type=='N'){ *dec=24576; if((dir_reg[instruction.op2_value]+(instruction.op3_value<<2))>=0x40000000){ IOAccess((uint8_t)(dir_reg[instruction.op2_value]+(instruction.op3_value<<2)), &data,Write);} else{ STR(dir_reg[instruction.op1_value], dir_reg[instruction.op2_value], instruction.op3_value<<2, SRAM);} *dec=*dec|instruction.op3_value<<6|instruction.op2_value<<3|instruction.op1_value; mvprintw(1,3,"Hola");} else{ *dec=20480; if((dir_reg[instruction.op2_value]+dir_reg[instruction.op2_value])>=0x40000000) IOAccess((uint8_t)(dir_reg[instruction.op2_value]+(dir_reg[instruction.op3_value])), &data,Write); else{ STR(dir_reg[instruction.op1_value], instruction.op2_value, instruction.op3_value, SRAM);} *dec=*dec|instruction.op3_value<<6|instruction.op2_value<<3|instruction.op1_value;} } if(strcmp(instruction.mnemonic,"STRB")==0){ dir_reg[PC]++; if(instruction.op3_type=='#' || instruction.op3_type=='N'){ *dec=28672; if(dir_reg[instruction.op2_value]+instruction.op3_value>=0x40000000){ IOAccess((uint8_t)(dir_reg[instruction.op2_value]+instruction.op3_value), &data,Write);} else{ STRB(dir_reg[instruction.op1_value], dir_reg[instruction.op2_value], instruction.op3_value, SRAM);} *dec=*dec|instruction.op3_value<<6|instruction.op2_value<<3|instruction.op1_value;} else{ *dec=21504; if((dir_reg[instruction.op2_value]+dir_reg[instruction.op3_value])>=0x40000000){ IOAccess((uint8_t)(dir_reg[instruction.op2_value]+(dir_reg[instruction.op3_value])), &data,Write);} else{ STRB(dir_reg[instruction.op1_value], dir_reg[instruction.op2_value], dir_reg[instruction.op3_value], SRAM);} *dec=*dec|instruction.op3_value<<6|instruction.op2_value<<3|instruction.op1_value;} } if(strcmp(instruction.mnemonic,"STRH")==0){ dir_reg[PC]++; if(instruction.op3_type=='#' || instruction.op3_type=='N'){ *dec=32768; if(((dir_reg[instruction.op2_value])+(instruction.op3_value<<1))>=0x40000000) IOAccess((uint8_t)(dir_reg[instruction.op2_value]+(instruction.op3_value<<1)),&data,Write); else STRH(dir_reg[instruction.op1_value], dir_reg[instruction.op2_value], instruction.op3_value<<1, SRAM); *dec=*dec|instruction.op3_value<<6|instruction.op2_value<<3|instruction.op1_value;} else{ *dec=20992; if((dir_reg[instruction.op2_value]+dir_reg[instruction.op3_value])>=0x40000000) IOAccess((uint8_t)(dir_reg[instruction.op2_value]+(dir_reg[instruction.op3_value])), &data,Write); else STRH(dir_reg[instruction.op1_value], dir_reg[instruction.op2_value], dir_reg[instruction.op3_value], SRAM); *dec=*dec|instruction.op3_value<<6|instruction.op2_value<<3|instruction.op1_value;} } }
// // 柦椷幚峴 // INT CPU::EXEC( INT request_cycles ) { BYTE opcode; // 僆儁僐乕僪 INT OLD_cycles = TOTAL_cycles; INT exec_cycles; BYTE nmi_request, irq_request; BOOL bClockProcess = m_bClockProcess; // TEMP register WORD EA; register WORD ET; register WORD WT; register BYTE DT; while( request_cycles > 0 ) { exec_cycles = 0; if( DMA_cycles ) { if( request_cycles <= DMA_cycles ) { DMA_cycles -= request_cycles; TOTAL_cycles += request_cycles; // 僋儘僢僋摨婜張棟 mapper->Clock( request_cycles ); #if DPCM_SYNCCLOCK apu->SyncDPCM( request_cycles ); #endif if( bClockProcess ) { nes->Clock( request_cycles ); } // nes->Clock( request_cycles ); goto _execute_exit; } else { exec_cycles += DMA_cycles; // request_cycles -= DMA_cycles; DMA_cycles = 0; } } nmi_request = irq_request = 0; opcode = OP6502( R.PC++ ); if( R.INT_pending ) { if( R.INT_pending & NMI_FLAG ) { nmi_request = 0xFF; R.INT_pending &= ~NMI_FLAG; } else if( R.INT_pending & IRQ_MASK ) { R.INT_pending &= ~IRQ_TRIGGER2; if( !(R.P & I_FLAG) && opcode != 0x40 ) { irq_request = 0xFF; R.INT_pending &= ~IRQ_TRIGGER; } } } //增加指令预测忽略功能 //opcode BYTE iInstructionLen =1; switch (TraceAddrMode[opcode]) { case IND: case ADR: case ABS: case ABX: case ABY: iInstructionLen = 3; break; case IMM: case ZPG: case ZPX: case ZPY: case INX: case INY: iInstructionLen = 2; break; case IMP:case ACC:case ERR: break; case REL:iInstructionLen = 2;break; } if( ((TraceArr[opcode][0]=='*') || (TraceArr[opcode][1]=='?'))&& (!Config.emulator.bIllegalOp) ) { //这里可以优化输出信息 //char str[111]; //DecodeInstruction (R.PC-1, str); //DEBUGOUT( "Bad Instruction:%s\n",str); R.PC=(R.PC-1)+iInstructionLen; ADD_CYCLE(iInstructionLen*2); goto end_is; } // switch( opcode ) { case 0x69: // ADC #$?? MR_IM(); ADC(); ADD_CYCLE(2); break; case 0x65: // ADC $?? MR_ZP(); ADC(); ADD_CYCLE(3); break; case 0x75: // ADC $??,X MR_ZX(); ADC(); ADD_CYCLE(4); break; case 0x6D: // ADC $???? MR_AB(); ADC(); ADD_CYCLE(4); break; case 0x7D: // ADC $????,X MR_AX(); ADC(); CHECK_EA(); ADD_CYCLE(4); break; case 0x79: // ADC $????,Y MR_AY(); ADC(); CHECK_EA(); ADD_CYCLE(4); break; case 0x61: // ADC ($??,X) MR_IX(); ADC(); ADD_CYCLE(6); break; case 0x71: // ADC ($??),Y MR_IY(); ADC(); CHECK_EA(); ADD_CYCLE(4); break; case 0xE9: // SBC #$?? MR_IM(); SBC(); ADD_CYCLE(2); break; case 0xE5: // SBC $?? MR_ZP(); SBC(); ADD_CYCLE(3); break; case 0xF5: // SBC $??,X MR_ZX(); SBC(); ADD_CYCLE(4); break; case 0xED: // SBC $???? MR_AB(); SBC(); ADD_CYCLE(4); break; case 0xFD: // SBC $????,X MR_AX(); SBC(); CHECK_EA(); ADD_CYCLE(4); break; case 0xF9: // SBC $????,Y MR_AY(); SBC(); CHECK_EA(); ADD_CYCLE(4); break; case 0xE1: // SBC ($??,X) MR_IX(); SBC(); ADD_CYCLE(6); break; case 0xF1: // SBC ($??),Y MR_IY(); SBC(); CHECK_EA(); ADD_CYCLE(5); break; case 0xC6: // DEC $?? MR_ZP(); DEC(); MW_ZP(); ADD_CYCLE(5); break; case 0xD6: // DEC $??,X MR_ZX(); DEC(); MW_ZP(); ADD_CYCLE(6); break; case 0xCE: // DEC $???? MR_AB(); DEC(); MW_EA(); ADD_CYCLE(6); break; case 0xDE: // DEC $????,X MR_AX(); DEC(); MW_EA(); ADD_CYCLE(7); break; case 0xCA: // DEX DEX(); ADD_CYCLE(2); break; case 0x88: // DEY DEY(); ADD_CYCLE(2); break; case 0xE6: // INC $?? MR_ZP(); INC(); MW_ZP(); ADD_CYCLE(5); break; case 0xF6: // INC $??,X MR_ZX(); INC(); MW_ZP(); ADD_CYCLE(6); break; case 0xEE: // INC $???? MR_AB(); INC(); MW_EA(); ADD_CYCLE(6); break; case 0xFE: // INC $????,X MR_AX(); INC(); MW_EA(); ADD_CYCLE(7); break; case 0xE8: // INX INX(); ADD_CYCLE(2); break; case 0xC8: // INY INY(); ADD_CYCLE(2); break; case 0x29: // AND #$?? MR_IM(); AND(); ADD_CYCLE(2); break; case 0x25: // AND $?? MR_ZP(); AND(); ADD_CYCLE(3); break; case 0x35: // AND $??,X MR_ZX(); AND(); ADD_CYCLE(4); break; case 0x2D: // AND $???? MR_AB(); AND(); ADD_CYCLE(4); break; case 0x3D: // AND $????,X MR_AX(); AND(); CHECK_EA(); ADD_CYCLE(4); break; case 0x39: // AND $????,Y MR_AY(); AND(); CHECK_EA(); ADD_CYCLE(4); break; case 0x21: // AND ($??,X) MR_IX(); AND(); ADD_CYCLE(6); break; case 0x31: // AND ($??),Y MR_IY(); AND(); CHECK_EA(); ADD_CYCLE(5); break; case 0x0A: // ASL A ASL_A(); ADD_CYCLE(2); break; case 0x06: // ASL $?? MR_ZP(); ASL(); MW_ZP(); ADD_CYCLE(5); break; case 0x16: // ASL $??,X MR_ZX(); ASL(); MW_ZP(); ADD_CYCLE(6); break; case 0x0E: // ASL $???? MR_AB(); ASL(); MW_EA(); ADD_CYCLE(6); break; case 0x1E: // ASL $????,X MR_AX(); ASL(); MW_EA(); ADD_CYCLE(7); break; case 0x24: // BIT $?? MR_ZP(); BIT(); ADD_CYCLE(3); break; case 0x2C: // BIT $???? MR_AB(); BIT(); ADD_CYCLE(4); break; case 0x49: // EOR #$?? MR_IM(); EOR(); ADD_CYCLE(2); break; case 0x45: // EOR $?? MR_ZP(); EOR(); ADD_CYCLE(3); break; case 0x55: // EOR $??,X MR_ZX(); EOR(); ADD_CYCLE(4); break; case 0x4D: // EOR $???? MR_AB(); EOR(); ADD_CYCLE(4); break; case 0x5D: // EOR $????,X MR_AX(); EOR(); CHECK_EA(); ADD_CYCLE(4); break; case 0x59: // EOR $????,Y MR_AY(); EOR(); CHECK_EA(); ADD_CYCLE(4); break; case 0x41: // EOR ($??,X) MR_IX(); EOR(); ADD_CYCLE(6); break; case 0x51: // EOR ($??),Y MR_IY(); EOR(); CHECK_EA(); ADD_CYCLE(5); break; case 0x4A: // LSR A LSR_A(); ADD_CYCLE(2); break; case 0x46: // LSR $?? MR_ZP(); LSR(); MW_ZP(); ADD_CYCLE(5); break; case 0x56: // LSR $??,X MR_ZX(); LSR(); MW_ZP(); ADD_CYCLE(6); break; case 0x4E: // LSR $???? MR_AB(); LSR(); MW_EA(); ADD_CYCLE(6); break; case 0x5E: // LSR $????,X MR_AX(); LSR(); MW_EA(); ADD_CYCLE(7); break; case 0x09: // ORA #$?? MR_IM(); ORA(); ADD_CYCLE(2); break; case 0x05: // ORA $?? MR_ZP(); ORA(); ADD_CYCLE(3); break; case 0x15: // ORA $??,X MR_ZX(); ORA(); ADD_CYCLE(4); break; case 0x0D: // ORA $???? MR_AB(); ORA(); ADD_CYCLE(4); break; case 0x1D: // ORA $????,X MR_AX(); ORA(); CHECK_EA(); ADD_CYCLE(4); break; case 0x19: // ORA $????,Y MR_AY(); ORA(); CHECK_EA(); ADD_CYCLE(4); break; case 0x01: // ORA ($??,X) MR_IX(); ORA(); ADD_CYCLE(6); break; case 0x11: // ORA ($??),Y MR_IY(); ORA(); CHECK_EA(); ADD_CYCLE(5); break; case 0x2A: // ROL A ROL_A(); ADD_CYCLE(2); break; case 0x26: // ROL $?? MR_ZP(); ROL(); MW_ZP(); ADD_CYCLE(5); break; case 0x36: // ROL $??,X MR_ZX(); ROL(); MW_ZP(); ADD_CYCLE(6); break; case 0x2E: // ROL $???? MR_AB(); ROL(); MW_EA(); ADD_CYCLE(6); break; case 0x3E: // ROL $????,X MR_AX(); ROL(); MW_EA(); ADD_CYCLE(7); break; case 0x6A: // ROR A ROR_A(); ADD_CYCLE(2); break; case 0x66: // ROR $?? MR_ZP(); ROR(); MW_ZP(); ADD_CYCLE(5); break; case 0x76: // ROR $??,X MR_ZX(); ROR(); MW_ZP(); ADD_CYCLE(6); break; case 0x6E: // ROR $???? MR_AB(); ROR(); MW_EA(); ADD_CYCLE(6); break; case 0x7E: // ROR $????,X MR_AX(); ROR(); MW_EA(); ADD_CYCLE(7); break; case 0xA9: // LDA #$?? MR_IM(); LDA(); ADD_CYCLE(2); break; case 0xA5: // LDA $?? MR_ZP(); LDA(); ADD_CYCLE(3); break; case 0xB5: // LDA $??,X MR_ZX(); LDA(); ADD_CYCLE(4); break; case 0xAD: // LDA $???? MR_AB(); LDA(); ADD_CYCLE(4); break; case 0xBD: // LDA $????,X MR_AX(); LDA(); CHECK_EA(); ADD_CYCLE(4); break; case 0xB9: // LDA $????,Y MR_AY(); LDA(); CHECK_EA(); ADD_CYCLE(4); break; case 0xA1: // LDA ($??,X) MR_IX(); LDA(); ADD_CYCLE(6); break; case 0xB1: // LDA ($??),Y MR_IY(); LDA(); CHECK_EA(); ADD_CYCLE(5); break; case 0xA2: // LDX #$?? MR_IM(); LDX(); ADD_CYCLE(2); break; case 0xA6: // LDX $?? MR_ZP(); LDX(); ADD_CYCLE(3); break; case 0xB6: // LDX $??,Y MR_ZY(); LDX(); ADD_CYCLE(4); break; case 0xAE: // LDX $???? MR_AB(); LDX(); ADD_CYCLE(4); break; case 0xBE: // LDX $????,Y MR_AY(); LDX(); CHECK_EA(); ADD_CYCLE(4); break; case 0xA0: // LDY #$?? MR_IM(); LDY(); ADD_CYCLE(2); break; case 0xA4: // LDY $?? MR_ZP(); LDY(); ADD_CYCLE(3); break; case 0xB4: // LDY $??,X MR_ZX(); LDY(); ADD_CYCLE(4); break; case 0xAC: // LDY $???? MR_AB(); LDY(); ADD_CYCLE(4); break; case 0xBC: // LDY $????,X MR_AX(); LDY(); CHECK_EA(); ADD_CYCLE(4); break; case 0x85: // STA $?? EA_ZP(); STA(); MW_ZP(); ADD_CYCLE(3); break; case 0x95: // STA $??,X EA_ZX(); STA(); MW_ZP(); ADD_CYCLE(4); break; case 0x8D: // STA $???? EA_AB(); STA(); MW_EA(); ADD_CYCLE(4); break; case 0x9D: // STA $????,X EA_AX(); STA(); MW_EA(); ADD_CYCLE(5); break; case 0x99: // STA $????,Y EA_AY(); STA(); MW_EA(); ADD_CYCLE(5); break; case 0x81: // STA ($??,X) EA_IX(); STA(); MW_EA(); ADD_CYCLE(6); break; case 0x91: // STA ($??),Y EA_IY(); STA(); MW_EA(); ADD_CYCLE(6); break; case 0x86: // STX $?? EA_ZP(); STX(); MW_ZP(); ADD_CYCLE(3); break; case 0x96: // STX $??,Y EA_ZY(); STX(); MW_ZP(); ADD_CYCLE(4); break; case 0x8E: // STX $???? EA_AB(); STX(); MW_EA(); ADD_CYCLE(4); break; case 0x84: // STY $?? EA_ZP(); STY(); MW_ZP(); ADD_CYCLE(3); break; case 0x94: // STY $??,X EA_ZX(); STY(); MW_ZP(); ADD_CYCLE(4); break; case 0x8C: // STY $???? EA_AB(); STY(); MW_EA(); ADD_CYCLE(4); break; case 0xAA: // TAX TAX(); ADD_CYCLE(2); break; case 0x8A: // TXA TXA(); ADD_CYCLE(2); break; case 0xA8: // TAY TAY(); ADD_CYCLE(2); break; case 0x98: // TYA TYA(); ADD_CYCLE(2); break; case 0xBA: // TSX TSX(); ADD_CYCLE(2); break; case 0x9A: // TXS TXS(); ADD_CYCLE(2); break; case 0xC9: // CMP #$?? MR_IM(); CMP_(); ADD_CYCLE(2); break; case 0xC5: // CMP $?? MR_ZP(); CMP_(); ADD_CYCLE(3); break; case 0xD5: // CMP $??,X MR_ZX(); CMP_(); ADD_CYCLE(4); break; case 0xCD: // CMP $???? MR_AB(); CMP_(); ADD_CYCLE(4); break; case 0xDD: // CMP $????,X MR_AX(); CMP_(); CHECK_EA(); ADD_CYCLE(4); break; case 0xD9: // CMP $????,Y MR_AY(); CMP_(); CHECK_EA(); ADD_CYCLE(4); break; case 0xC1: // CMP ($??,X) MR_IX(); CMP_(); ADD_CYCLE(6); break; case 0xD1: // CMP ($??),Y MR_IY(); CMP_(); CHECK_EA(); ADD_CYCLE(5); break; case 0xE0: // CPX #$?? MR_IM(); CPX(); ADD_CYCLE(2); break; case 0xE4: // CPX $?? MR_ZP(); CPX(); ADD_CYCLE(3); break; case 0xEC: // CPX $???? MR_AB(); CPX(); ADD_CYCLE(4); break; case 0xC0: // CPY #$?? MR_IM(); CPY(); ADD_CYCLE(2); break; case 0xC4: // CPY $?? MR_ZP(); CPY(); ADD_CYCLE(3); break; case 0xCC: // CPY $???? MR_AB(); CPY(); ADD_CYCLE(4); break; case 0x90: // BCC MR_IM(); BCC(); ADD_CYCLE(2); break; case 0xB0: // BCS MR_IM(); BCS(); ADD_CYCLE(2); break; case 0xF0: // BEQ MR_IM(); BEQ(); ADD_CYCLE(2); break; case 0x30: // BMI MR_IM(); BMI(); ADD_CYCLE(2); break; case 0xD0: // BNE MR_IM(); BNE(); ADD_CYCLE(2); break; case 0x10: // BPL MR_IM(); BPL(); ADD_CYCLE(2); break; case 0x50: // BVC MR_IM(); BVC(); ADD_CYCLE(2); break; case 0x70: // BVS MR_IM(); BVS(); ADD_CYCLE(2); break; case 0x4C: // JMP $???? JMP(); ADD_CYCLE(3); break; case 0x6C: // JMP ($????) JMP_ID(); ADD_CYCLE(5); break; case 0x20: // JSR JSR(); ADD_CYCLE(6); break; case 0x40: // RTI RTI(); ADD_CYCLE(6); break; case 0x60: // RTS RTS(); ADD_CYCLE(6); break; // 僼儔僌惂屼宯 case 0x18: // CLC CLC(); ADD_CYCLE(2); break; case 0xD8: // CLD CLD(); ADD_CYCLE(2); break; case 0x58: // CLI CLI(); ADD_CYCLE(2); break; case 0xB8: // CLV CLV(); ADD_CYCLE(2); break; case 0x38: // SEC SEC(); ADD_CYCLE(2); break; case 0xF8: // SED SED(); ADD_CYCLE(2); break; case 0x78: // SEI SEI(); ADD_CYCLE(2); break; // 僗僞僢僋宯 case 0x48: // PHA PUSH( R.A ); ADD_CYCLE(3); break; case 0x08: // PHP PUSH( R.P | B_FLAG ); ADD_CYCLE(3); break; case 0x68: // PLA (N-----Z-) R.A = POP(); SET_ZN_FLAG(R.A); ADD_CYCLE(4); break; case 0x28: // PLP R.P = POP() | R_FLAG; ADD_CYCLE(4); break; // 偦偺懠 case 0x00: // BRK BRK(); ADD_CYCLE(7); break; case 0xEA: // NOP ADD_CYCLE(2); break; // 枹岞奐柦椷孮 case 0x0B: // ANC #$?? case 0x2B: // ANC #$?? MR_IM(); ANC(); ADD_CYCLE(2); break; case 0x8B: // ANE #$?? MR_IM(); ANE(); ADD_CYCLE(2); break; case 0x6B: // ARR #$?? MR_IM(); ARR(); ADD_CYCLE(2); break; case 0x4B: // ASR #$?? MR_IM(); ASR(); ADD_CYCLE(2); break; case 0xC7: // DCP $?? MR_ZP(); DCP(); MW_ZP(); ADD_CYCLE(5); break; case 0xD7: // DCP $??,X MR_ZX(); DCP(); MW_ZP(); ADD_CYCLE(6); break; case 0xCF: // DCP $???? MR_AB(); DCP(); MW_EA(); ADD_CYCLE(6); break; case 0xDF: // DCP $????,X MR_AX(); DCP(); MW_EA(); ADD_CYCLE(7); break; case 0xDB: // DCP $????,Y MR_AY(); DCP(); MW_EA(); ADD_CYCLE(7); break; case 0xC3: // DCP ($??,X) MR_IX(); DCP(); MW_EA(); ADD_CYCLE(8); break; case 0xD3: // DCP ($??),Y MR_IY(); DCP(); MW_EA(); ADD_CYCLE(8); break; case 0xE7: // ISB $?? MR_ZP(); ISB(); MW_ZP(); ADD_CYCLE(5); break; case 0xF7: // ISB $??,X MR_ZX(); ISB(); MW_ZP(); ADD_CYCLE(5); break; case 0xEF: // ISB $???? MR_AB(); ISB(); MW_EA(); ADD_CYCLE(5); break; case 0xFF: // ISB $????,X MR_AX(); ISB(); MW_EA(); ADD_CYCLE(5); break; case 0xFB: // ISB $????,Y MR_AY(); ISB(); MW_EA(); ADD_CYCLE(5); break; case 0xE3: // ISB ($??,X) MR_IX(); ISB(); MW_EA(); ADD_CYCLE(5); break; case 0xF3: // ISB ($??),Y MR_IY(); ISB(); MW_EA(); ADD_CYCLE(5); break; case 0xBB: // LAS $????,Y MR_AY(); LAS(); CHECK_EA(); ADD_CYCLE(4); break; case 0xA7: // LAX $?? MR_ZP(); LAX(); ADD_CYCLE(3); break; case 0xB7: // LAX $??,Y MR_ZY(); LAX(); ADD_CYCLE(4); break; case 0xAF: // LAX $???? MR_AB(); LAX(); ADD_CYCLE(4); break; case 0xBF: // LAX $????,Y MR_AY(); LAX(); CHECK_EA(); ADD_CYCLE(4); break; case 0xA3: // LAX ($??,X) MR_IX(); LAX(); ADD_CYCLE(6); break; case 0xB3: // LAX ($??),Y MR_IY(); LAX(); CHECK_EA(); ADD_CYCLE(5); break; case 0xAB: // LXA #$?? MR_IM(); LXA(); ADD_CYCLE(2); break; case 0x27: // RLA $?? MR_ZP(); RLA(); MW_ZP(); ADD_CYCLE(5); break; case 0x37: // RLA $??,X MR_ZX(); RLA(); MW_ZP(); ADD_CYCLE(6); break; case 0x2F: // RLA $???? MR_AB(); RLA(); MW_EA(); ADD_CYCLE(6); break; case 0x3F: // RLA $????,X MR_AX(); RLA(); MW_EA(); ADD_CYCLE(7); break; case 0x3B: // RLA $????,Y MR_AY(); RLA(); MW_EA(); ADD_CYCLE(7); break; case 0x23: // RLA ($??,X) MR_IX(); RLA(); MW_EA(); ADD_CYCLE(8); break; case 0x33: // RLA ($??),Y MR_IY(); RLA(); MW_EA(); ADD_CYCLE(8); break; case 0x67: // RRA $?? MR_ZP(); RRA(); MW_ZP(); ADD_CYCLE(5); break; case 0x77: // RRA $??,X MR_ZX(); RRA(); MW_ZP(); ADD_CYCLE(6); break; case 0x6F: // RRA $???? MR_AB(); RRA(); MW_EA(); ADD_CYCLE(6); break; case 0x7F: // RRA $????,X MR_AX(); RRA(); MW_EA(); ADD_CYCLE(7); break; case 0x7B: // RRA $????,Y MR_AY(); RRA(); MW_EA(); ADD_CYCLE(7); break; case 0x63: // RRA ($??,X) MR_IX(); RRA(); MW_EA(); ADD_CYCLE(8); break; case 0x73: // RRA ($??),Y MR_IY(); RRA(); MW_EA(); ADD_CYCLE(8); break; case 0x87: // SAX $?? MR_ZP(); SAX(); MW_ZP(); ADD_CYCLE(3); break; case 0x97: // SAX $??,Y MR_ZY(); SAX(); MW_ZP(); ADD_CYCLE(4); break; case 0x8F: // SAX $???? MR_AB(); SAX(); MW_EA(); ADD_CYCLE(4); break; case 0x83: // SAX ($??,X) MR_IX(); SAX(); MW_EA(); ADD_CYCLE(6); break; case 0xCB: // SBX #$?? MR_IM(); SBX(); ADD_CYCLE(2); break; case 0x9F: // SHA $????,Y MR_AY(); SHA(); MW_EA(); ADD_CYCLE(5); break; case 0x93: // SHA ($??),Y MR_IY(); SHA(); MW_EA(); ADD_CYCLE(6); break; case 0x9B: // SHS $????,Y MR_AY(); SHS(); MW_EA(); ADD_CYCLE(5); break; case 0x9E: // SHX $????,Y MR_AY(); SHX(); MW_EA(); ADD_CYCLE(5); break; case 0x9C: // SHY $????,X MR_AX(); SHY(); MW_EA(); ADD_CYCLE(5); break; case 0x07: // SLO $?? MR_ZP(); SLO(); MW_ZP(); ADD_CYCLE(5); break; case 0x17: // SLO $??,X MR_ZX(); SLO(); MW_ZP(); ADD_CYCLE(6); break; case 0x0F: // SLO $???? MR_AB(); SLO(); MW_EA(); ADD_CYCLE(6); break; case 0x1F: // SLO $????,X MR_AX(); SLO(); MW_EA(); ADD_CYCLE(7); break; case 0x1B: // SLO $????,Y MR_AY(); SLO(); MW_EA(); ADD_CYCLE(7); break; case 0x03: // SLO ($??,X) MR_IX(); SLO(); MW_EA(); ADD_CYCLE(8); break; case 0x13: // SLO ($??),Y MR_IY(); SLO(); MW_EA(); ADD_CYCLE(8); break; case 0x47: // SRE $?? MR_ZP(); SRE(); MW_ZP(); ADD_CYCLE(5); break; case 0x57: // SRE $??,X MR_ZX(); SRE(); MW_ZP(); ADD_CYCLE(6); break; case 0x4F: // SRE $???? MR_AB(); SRE(); MW_EA(); ADD_CYCLE(6); break; case 0x5F: // SRE $????,X MR_AX(); SRE(); MW_EA(); ADD_CYCLE(7); break; case 0x5B: // SRE $????,Y MR_AY(); SRE(); MW_EA(); ADD_CYCLE(7); break; case 0x43: // SRE ($??,X) MR_IX(); SRE(); MW_EA(); ADD_CYCLE(8); break; case 0x53: // SRE ($??),Y MR_IY(); SRE(); MW_EA(); ADD_CYCLE(8); break; case 0xEB: // SBC #$?? (Unofficial) MR_IM(); SBC(); ADD_CYCLE(2); break; case 0x1A: // NOP (Unofficial) case 0x3A: // NOP (Unofficial) case 0x5A: // NOP (Unofficial) case 0x7A: // NOP (Unofficial) case 0xDA: // NOP (Unofficial) case 0xFA: // NOP (Unofficial) ADD_CYCLE(2); break; case 0x80: // DOP (CYCLES 2) case 0x82: // DOP (CYCLES 2) case 0x89: // DOP (CYCLES 2) case 0xC2: // DOP (CYCLES 2) case 0xE2: // DOP (CYCLES 2) R.PC++; ADD_CYCLE(2); break; case 0x04: // DOP (CYCLES 3) case 0x44: // DOP (CYCLES 3) case 0x64: // DOP (CYCLES 3) R.PC++; ADD_CYCLE(3); break; case 0x14: // DOP (CYCLES 4) case 0x34: // DOP (CYCLES 4) case 0x54: // DOP (CYCLES 4) case 0x74: // DOP (CYCLES 4) case 0xD4: // DOP (CYCLES 4) case 0xF4: // DOP (CYCLES 4) R.PC++; ADD_CYCLE(4); break; case 0x0C: // TOP case 0x1C: // TOP case 0x3C: // TOP case 0x5C: // TOP case 0x7C: // TOP case 0xDC: // TOP case 0xFC: // TOP R.PC+=2; ADD_CYCLE(4); break; case 0x02: /* JAM */ case 0x12: /* JAM */ case 0x22: /* JAM */ case 0x32: /* JAM */ case 0x42: /* JAM */ case 0x52: /* JAM */ case 0x62: /* JAM */ case 0x72: /* JAM */ case 0x92: /* JAM */ case 0xB2: /* JAM */ case 0xD2: /* JAM */ case 0xF2: /* JAM */ default: if( !Config.emulator.bIllegalOp ) { throw CApp::GetErrorString( IDS_ERROR_ILLEGALOPCODE ); goto _execute_exit; } else { R.PC--; ADD_CYCLE(4); } break; // default: // __assume(0); } end_is: __asm nop; if( nmi_request ) { _NMI(); } else if( irq_request ) { _IRQ(); } request_cycles -= exec_cycles; TOTAL_cycles += exec_cycles; // 僋儘僢僋摨婜張棟 mapper->Clock( exec_cycles ); #if DPCM_SYNCCLOCK apu->SyncDPCM( exec_cycles ); #endif if( bClockProcess ) { nes->Clock( exec_cycles ); } // nes->Clock( exec_cycles ); } _execute_exit: #if !DPCM_SYNCCLOCK apu->SyncDPCM( TOTAL_cycles - OLD_cycles ); #endif return TOTAL_cycles - OLD_cycles; }
int main() { int op; uint32_t registro[16]={0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; char banderas[4]; do{ system("cls"); printf("seleccione la opcion 1 para mostrar los valores de los registros\n"); printf("seleccione la opcion 2 para sumar registros \n"); printf("seleccione la opcion 3 para multiplicacion logica (AND) de registros \n"); printf("seleccione la opcion 4 para Eor a nivel de bits \n"); printf("seleccione la opcion 5 para desplazar de un registro a otro \n"); printf("seleccione la opcion 6 para suma logica (OR) de registro\n"); printf("seleccione la opcion 7 para ADN sin almacenar, solo modifica banderas \n"); printf("seleccione la opcion 8 para comparar (SUB sin almacenar), solo modifica banderas\n"); printf("seleccione la opcion 9 Multiplicacion de registros, solo se alacenan 32 bits menos significativos\n"); printf("seleccione la opcion 10 AND sin almacenacmiento, solo modifica banderas\n"); printf("seleccione la opcion 11 para LSL desplazamiento logico a la izquierda \n"); printf("seleccione la opcion 12 para LSR desplazamiento logico a la derecha \n"); printf("seleccione la opcion 13 para ROR rotacion a la derecha \n"); printf("seleccione la opcion 14 para ASR desplazamiento aritmetico a la derecha \n"); printf("seleccione la opcion 15 para BIC Realiza una AND de un registro con otro negado \n"); printf("seleccione la opcion 16 para MUN guarda en un registro la negacion de otro\n"); printf("seleccione la opcion 17 para RSB niega un valor de registro\n"); printf("seleccione la opcion 18 para NOP da un retardo de un ciclo de reloj (no hace nada) \n"); printf("seleccione la opcion 19 para REV toma grupos de 8 bits y los desplaza \n"); printf("seleccione la opcion 20 para REVIG toma grupos de 16 bits y los agrupa en grupos de dos bytes\n"); printf("seleccione la opcion 21 para REVSH extencion con signo\n\n"); scanf("%d",&op); system("cls"); switch(op){ case 1: //mostrar_valores(registro); break; case 2: printf("ingrese el valor del primer registro:\n"); scanf("%d",®istro[1]); printf("ingrese el valor del segundo registro:\n"); scanf("%d",®istro[2]); ADD(registro,®istro[0],registro[1],registro[2],&banderas[0]); printf("%d valor del resultado \n",registro[0]); printf("%d valor del resultado bandera n \n",banderas[N]); printf("%d valor del resultado bandera z \n",banderas[Z]); printf("%d valor del resultado bandera c \n",banderas[C]); printf("%d valor del resultado bandera v \n",banderas[V]); break; case 3: printf("ingrese el valor del primer registro:\n"); scanf("%d",®istro[1]); printf("ingrese el valor del segundo registro:\n"); scanf("%d",®istro[2]); AND(registro,®istro[0],registro[1],registro[2],&banderas[0]); printf("%d valor del resultado \n",registro[0]); printf("%d valor del resultado bandera n \n",banderas[N]); printf("%d valor del resultado bandera z \n",banderas[Z]); printf("%d valor del resultado bandera c \n",banderas[C]); printf("%d valor del resultado bandera v \n",banderas[V]); break; case 4: printf("ingrese el valor del primer registro:\n"); scanf("%d",®istro[1]); printf("ingrese el valor del segundo registro:\n"); scanf("%d",®istro[2]); EOR(registro,®istro[0],registro[1],registro[2],&banderas[0]); printf("%d valor del resultado \n",registro[0]); printf("%d valor del resultado bandera n \n",banderas[N]); printf("%d valor del resultado bandera z \n",banderas[Z]); printf("%d valor del resultado bandera c \n",banderas[C]); printf("%d valor del resultado bandera v \n",banderas[V]); break; case 5: printf("ingrese el valor del registro origen:\n"); scanf("%d",®istro[1]); MOV(registro,®istro[0],registro[1],banderas); printf("%d valor del resultado \n",registro[0]); break; case 7: printf("ingrese el valor del primer registro:\n"); scanf("%d",®istro[1]); printf("ingrese el valor del segundo registro:\n"); scanf("%d",®istro[2]); CMN(registro,registro[1],registro[2],&banderas[0]); printf("%d valor del resultado \n",registro[0]); printf("%d valor del resultado bandera n \n",banderas[N]); printf("%d valor del resultado bandera z \n",banderas[Z]); printf("%d valor del resultado bandera c \n",banderas[C]); printf("%d valor del resultado bandera v \n",banderas[V]); break; case 8: printf("ingrese el valor del primer registro:\n"); scanf("%d",®istro[1]); printf("ingrese el valor del segundo registro:\n"); scanf("%d",®istro[2]); CMP(registro,registro[1],registro[2],&banderas[0]); printf("%d valor del resultado \n",registro[0]); printf("%d valor del resultado bandera n \n",banderas[N]); printf("%d valor del resultado bandera z \n",banderas[Z]); printf("%d valor del resultado bandera c \n",banderas[C]); printf("%d valor del resultado bandera v \n",banderas[V]); break; case 9: printf("ingrese el valor del primer registro:\n"); scanf("%d",®istro[1]); printf("ingrese el valor del segundo registro:\n"); scanf("%d",®istro[2]); MUL(registro,®istro[0],registro[1],registro[2],&banderas[0]); printf("%d valor del resultado \n",registro[0]); printf("%d valor del resultado bandera n \n",banderas[N]); printf("%d valor del resultado bandera z \n",banderas[Z]); printf("%d valor del resultado bandera c \n",banderas[C]); printf("%d valor del resultado bandera v \n",banderas[V]); break; case 10: printf("ingrese el valor del primer registro:\n"); scanf("%d",®istro[1]); printf("ingrese el valor del segundo registro:\n"); scanf("%d",®istro[2]); TST(registro,registro[1],registro[2],&banderas[0]); printf("%d valor del resultado \n",registro[0]); printf("%d valor del resultado bandera n \n",banderas[N]); printf("%d valor del resultado bandera z \n",banderas[Z]); printf("%d valor del resultado bandera c \n",banderas[C]); printf("%d valor del resultado bandera v \n",banderas[V]); break; case 11: printf("ingrese el valor del registro:\n"); scanf("%d",®istro[1]); printf("ingrese el numero de desplazamientos:\n"); scanf("%d",®istro[2]); LSL(registro,®istro[0],registro[1],registro[2],banderas); printf("%d valor del resultado \n",registro[0]); break; case 12: printf("ingrese el valor del primer registro:\n"); scanf("%d",®istro[1]); printf("ingrese elnumero de desplazamientos:\n"); scanf("%d",®istro[2]); LSR(registro,®istro[0],registro[1],registro[2],banderas); printf("%d valor del resultado \n",registro[0]); break; case 13: printf("ingrese el valor del primer registro:\n"); scanf("%d",®istro[1]); printf("ingrese elnumero de desplazamientos:\n"); scanf("%d",®istro[2]); ROR(registro,®istro[0],registro[1],registro[2],banderas); printf("%d valor del resultado \n",registro[0]); break; case 14: printf("ingrese el valor del primer registro:\n"); scanf("%d",®istro[1]); printf("ingrese elnumero de desplazamientos:\n"); scanf("%d",®istro[2]); ASR(registro,®istro[0],registro[1],registro[2],banderas); printf("%d valor del resultado \n",registro[0]); break; case 15: printf("ingrese el valor del primer registro:\n"); scanf("%d",®istro[0]); printf("ingrese el valor del segundo registro:\n"); scanf("%d",®istro[1]); BIC(registro,®istro[0],registro[1],banderas); printf("%d valor del resultado \n",registro[0]); break; case 16: printf("ingrese un valor del registro origen\n"); scanf("%d",®istro[1]); MVN(registro,®istro[0],registro[1],banderas); printf("%d valor del resultado \n",registro[0]); break; case 17: printf("ingrese un valor de registro\n"); scanf("%d",®istro[1]); RSB(registro,®istro[0],registro[1],0,banderas); printf("%d valor del resultado \n",registro[0]); break; case 18: NOP(registro); break; case 19: printf("ingrese un valor de registro \n"); scanf("%d",®istro[0]); REV(registro,®istro[0]); printf("%d valor del resultado \n",registro[0]); break; case 20: printf("ingrese un valor de registro \n"); scanf("%d",®istro[0]); REVIG(registro,®istro[0]); printf("%d valor del resultado \n",registro[0]); break; case 21: printf("ingrese un valor de registro \n"); scanf("%d",®istro[0]); REVSH(registro,®istro[0]); printf("%d valor del resultado \n",registro[0]); break; default: printf("Opcion invalida\n\n"); break; } printf("\nDesea realizar otra operacion?\n<1>-si\n<0>-no\n"); scanf("%d",&op); system("cls"); }while(op); return 0; }
//////////////////////////////////////////////////// // Run! void Cpu::run(timestamp_t runto) { if(cpuJammed && (curCyc() < runto)) { setMainTimestamp(runto); } while( curCyc() < runto ) { ///////////////////////////////////// // Are we to take an interrupt if(wantInterrupt) { performInterrupt(false); continue; } if( *tracer ) tracer->traceCpuLine( cpu ); ///////////////////////////////////// // No interrupt, do an instruction u8 opcode = rd( cpu.PC++ ); switch(opcode) { /* Branches */ case 0x10: adBranch( !cpu.getN() ); break; /* BPL */ case 0x30: adBranch( cpu.getN() ); break; /* BMI */ case 0x50: adBranch( !cpu.getV() ); break; /* BVC */ case 0x70: adBranch( cpu.getV() ); break; /* BVS */ case 0x90: adBranch( !cpu.getC() ); break; /* BCC */ case 0xB0: adBranch( cpu.getC() ); break; /* BCS */ case 0xD0: adBranch( !cpu.getZ() ); break; /* BNE */ case 0xF0: adBranch( cpu.getZ() ); break; /* BEQ */ /* Flag flip-flop */ case 0x18: adImplied(); cpu.setC(0); break; /* CLC */ case 0x38: adImplied(); cpu.setC(1); break; /* SEC */ case 0x58: adImplied(); cpu.setI(0); break; /* CLI */ case 0x78: adImplied(); cpu.setI(1); break; /* SEI */ case 0xB8: adImplied(); cpu.setV(0); break; /* CLV */ case 0xD8: adImplied(); cpu.setD(0); break; /* CLD */ case 0xF8: adImplied(); cpu.setD(1); break; /* SED */ /* Stack push/pull */ case 0x08: adPush( cpu.getStatus(true) ); break; /* PHP */ case 0x28: cpu.setStatus( adPull() ); break; /* PLP */ case 0x48: adPush( cpu.A ); break; /* PHA */ case 0x68: cpu.NZ( cpu.A = adPull() ); break; /* PLA */ /* Reg Xfer */ case 0xAA: adImplied(); cpu.NZ( cpu.X = cpu.A ); break; /* TAX */ case 0xA8: adImplied(); cpu.NZ( cpu.Y = cpu.A ); break; /* TAY */ case 0xBA: adImplied(); cpu.NZ( cpu.X = cpu.SP ); break; /* TSX */ case 0x8A: adImplied(); cpu.NZ( cpu.A = cpu.X ); break; /* TXA */ case 0x9A: adImplied(); cpu.SP = cpu.X; break; /* TXS */ case 0x98: adImplied(); cpu.NZ( cpu.A = cpu.Y ); break; /* TYA */ /* Misc */ case 0x00: performInterrupt(true); break; /* BRK */ case 0x4C: full_JMP(); break; /* JMP $xxxx */ case 0x6C: full_JMP_Indirect(); break; /* JMP ($xxxx) */ case 0x20: full_JSR(); break; /* JSR $xxxx */ case 0xEA: adImplied(); break; /* NOP */ case 0x40: full_RTI(); break; /* RTI */ case 0x60: full_RTS(); break; /* RTS */ /* ADC */ case 0x69: ADC( adRdIm() ); break; case 0x65: ADC( adRdZp() ); break; case 0x75: ADC( adRdZx() ); break; case 0x6D: ADC( adRdAb() ); break; case 0x7D: ADC( adRdAx() ); break; case 0x79: ADC( adRdAy() ); break; case 0x61: ADC( adRdIx() ); break; case 0x71: ADC( adRdIy() ); break; /* AND */ case 0x29: AND( adRdIm() ); break; case 0x25: AND( adRdZp() ); break; case 0x35: AND( adRdZx() ); break; case 0x2D: AND( adRdAb() ); break; case 0x3D: AND( adRdAx() ); break; case 0x39: AND( adRdAy() ); break; case 0x21: AND( adRdIx() ); break; case 0x31: AND( adRdIy() ); break; /* ASL */ case 0x0A: adImplied(); ASL(cpu.A); break; case 0x06: adRWZp( &Cpu::ASL ); break; case 0x16: adRWZx( &Cpu::ASL ); break; case 0x0E: adRWAb( &Cpu::ASL ); break; case 0x1E: adRWAx( &Cpu::ASL ); break; /* BIT */ case 0x24: BIT( adRdZp() ); break; case 0x2C: BIT( adRdAb() ); break; /* CMP */ case 0xC9: CMP( adRdIm() ); break; case 0xC5: CMP( adRdZp() ); break; case 0xD5: CMP( adRdZx() ); break; case 0xCD: CMP( adRdAb() ); break; case 0xDD: CMP( adRdAx() ); break; case 0xD9: CMP( adRdAy() ); break; case 0xC1: CMP( adRdIx() ); break; case 0xD1: CMP( adRdIy() ); break; /* CPX */ case 0xE0: CPX( adRdIm() ); break; case 0xE4: CPX( adRdZp() ); break; case 0xEC: CPX( adRdAb() ); break; /* CPY */ case 0xC0: CPY( adRdIm() ); break; case 0xC4: CPY( adRdZp() ); break; case 0xCC: CPY( adRdAb() ); break; /* DEC */ case 0xCA: adImplied(); DEC(cpu.X); break; /* DEX */ case 0x88: adImplied(); DEC(cpu.Y); break; /* DEY */ case 0xC6: adRWZp( &Cpu::DEC ); break; case 0xD6: adRWZx( &Cpu::DEC ); break; case 0xCE: adRWAb( &Cpu::DEC ); break; case 0xDE: adRWAx( &Cpu::DEC ); break; /* EOR */ case 0x49: EOR( adRdIm() ); break; case 0x45: EOR( adRdZp() ); break; case 0x55: EOR( adRdZx() ); break; case 0x4D: EOR( adRdAb() ); break; case 0x5D: EOR( adRdAx() ); break; case 0x59: EOR( adRdAy() ); break; case 0x41: EOR( adRdIx() ); break; case 0x51: EOR( adRdIy() ); break; /* INC */ case 0xE8: adImplied(); INC(cpu.X); break; /* INX */ case 0xC8: adImplied(); INC(cpu.Y); break; /* INY */ case 0xE6: adRWZp( &Cpu::INC ); break; case 0xF6: adRWZx( &Cpu::INC ); break; case 0xEE: adRWAb( &Cpu::INC ); break; case 0xFE: adRWAx( &Cpu::INC ); break; /* LDA */ case 0xA9: cpu.NZ( cpu.A = adRdIm() ); break; case 0xA5: cpu.NZ( cpu.A = adRdZp() ); break; case 0xB5: cpu.NZ( cpu.A = adRdZx() ); break; case 0xAD: cpu.NZ( cpu.A = adRdAb() ); break; case 0xBD: cpu.NZ( cpu.A = adRdAx() ); break; case 0xB9: cpu.NZ( cpu.A = adRdAy() ); break; case 0xA1: cpu.NZ( cpu.A = adRdIx() ); break; case 0xB1: cpu.NZ( cpu.A = adRdIy() ); break; /* LDX */ case 0xA2: cpu.NZ( cpu.X = adRdIm() ); break; case 0xA6: cpu.NZ( cpu.X = adRdZp() ); break; case 0xB6: cpu.NZ( cpu.X = adRdZy() ); break; case 0xAE: cpu.NZ( cpu.X = adRdAb() ); break; case 0xBE: cpu.NZ( cpu.X = adRdAy() ); break; /* LDY */ case 0xA0: cpu.NZ( cpu.Y = adRdIm() ); break; case 0xA4: cpu.NZ( cpu.Y = adRdZp() ); break; case 0xB4: cpu.NZ( cpu.Y = adRdZx() ); break; case 0xAC: cpu.NZ( cpu.Y = adRdAb() ); break; case 0xBC: cpu.NZ( cpu.Y = adRdAx() ); break; /* LSR */ case 0x4A: adImplied(); LSR(cpu.A); break; case 0x46: adRWZp( &Cpu::LSR ); break; case 0x56: adRWZx( &Cpu::LSR ); break; case 0x4E: adRWAb( &Cpu::LSR ); break; case 0x5E: adRWAx( &Cpu::LSR ); break; /* ORA */ case 0x09: ORA( adRdIm() ); break; case 0x05: ORA( adRdZp() ); break; case 0x15: ORA( adRdZx() ); break; case 0x0D: ORA( adRdAb() ); break; case 0x1D: ORA( adRdAx() ); break; case 0x19: ORA( adRdAy() ); break; case 0x01: ORA( adRdIx() ); break; case 0x11: ORA( adRdIy() ); break; /* ROL */ case 0x2A: adImplied(); ROL(cpu.A); break; case 0x26: adRWZp( &Cpu::ROL ); break; case 0x36: adRWZx( &Cpu::ROL ); break; case 0x2E: adRWAb( &Cpu::ROL ); break; case 0x3E: adRWAx( &Cpu::ROL ); break; /* ROR */ case 0x6A: adImplied(); ROR(cpu.A); break; case 0x66: adRWZp( &Cpu::ROR ); break; case 0x76: adRWZx( &Cpu::ROR ); break; case 0x6E: adRWAb( &Cpu::ROR ); break; case 0x7E: adRWAx( &Cpu::ROR ); break; /* SBC */ case 0xE9: SBC( adRdIm() ); break; case 0xE5: SBC( adRdZp() ); break; case 0xF5: SBC( adRdZx() ); break; case 0xED: SBC( adRdAb() ); break; case 0xFD: SBC( adRdAx() ); break; case 0xF9: SBC( adRdAy() ); break; case 0xE1: SBC( adRdIx() ); break; case 0xF1: SBC( adRdIy() ); break; /* STA */ case 0x85: adWrZp( cpu.A ); break; case 0x95: adWrZx( cpu.A ); break; case 0x8D: adWrAb( cpu.A ); break; case 0x9D: adWrAx( cpu.A ); break; case 0x99: adWrAy( cpu.A ); break; case 0x81: adWrIx( cpu.A ); break; case 0x91: adWrIy( cpu.A ); break; /* STX */ case 0x86: adWrZp( cpu.X ); break; case 0x96: adWrZy( cpu.X ); break; case 0x8E: adWrAb( cpu.X ); break; /* STY */ case 0x84: adWrZp( cpu.Y ); break; case 0x94: adWrZx( cpu.Y ); break; case 0x8C: adWrAb( cpu.Y ); break; ///////////////////////////////////// // Unofficial ops /* One offs */ case 0x0B: case 0x2B: ANC( adRdIm() ); break; /* ANC */ case 0x4B: ALR( adRdIm() ); break; /* ALR */ case 0x6B: ARR( adRdIm() ); break; /* ARR */ case 0xCB: AXS( adRdIm() ); break; /* AXS */ case 0xBB: LAS( adRdAy() ); break; /* LAS */ case 0xEB: SBC( adRdIm() ); break; /* alternative SBC */ case 0x9E: adWrAy_xxx( cpu.X ); break; /* SHX */ case 0x9C: adWrAx_xxx( cpu.Y ); break; /* SHY */ case 0x8B: XAA( adRdIm() ); break; /* XAA */ case 0x9B: cpu.SP = cpu.A & cpu.X; adWrAy_xxx( cpu.SP ); break; /* TAS */ /* AHX */ case 0x9F: adWrAy_xxx( cpu.A & cpu.X ); break; case 0x93: adWrIy_xxx( cpu.A & cpu.X ); break; /* DCP */ case 0xC7: adRWZp( &Cpu::DCP ); break; case 0xD7: adRWZx( &Cpu::DCP ); break; case 0xCF: adRWAb( &Cpu::DCP ); break; case 0xDF: adRWAx( &Cpu::DCP ); break; case 0xDB: adRWAy( &Cpu::DCP ); break; case 0xC3: adRWIx( &Cpu::DCP ); break; case 0xD3: adRWIy( &Cpu::DCP ); break; /* ISC */ case 0xE7: adRWZp( &Cpu::ISC ); break; case 0xF7: adRWZx( &Cpu::ISC ); break; case 0xEF: adRWAb( &Cpu::ISC ); break; case 0xFF: adRWAx( &Cpu::ISC ); break; case 0xFB: adRWAy( &Cpu::ISC ); break; case 0xE3: adRWIx( &Cpu::ISC ); break; case 0xF3: adRWIy( &Cpu::ISC ); break; /* LAX */ case 0xAB: LAX( adRdIm() ); break; case 0xA7: LAX( adRdZp() ); break; case 0xB7: LAX( adRdZy() ); break; case 0xAF: LAX( adRdAb() ); break; case 0xBF: LAX( adRdAy() ); break; case 0xA3: LAX( adRdIx() ); break; case 0xB3: LAX( adRdIy() ); break; /* NOP */ case 0x1A: case 0x3A: case 0x5A: case 0x7A: case 0xDA: case 0xFA: adImplied();break; case 0x04: case 0x44: case 0x64: adRdZp(); break; case 0x14: case 0x34: case 0x54: case 0x74: case 0xD4: case 0xF4: adRdZx(); break; case 0x80: case 0x82: case 0x89: case 0xC2: case 0xE2: adRdIm(); break; case 0x0C: adRdAb(); break; case 0x1C: case 0x3C: case 0x5C: case 0x7C: case 0xDC: case 0xFC: adRdAx(); break; /* RLA */ case 0x27: adRWZp( &Cpu::RLA ); break; case 0x37: adRWZx( &Cpu::RLA ); break; case 0x2F: adRWAb( &Cpu::RLA ); break; case 0x3F: adRWAx( &Cpu::RLA ); break; case 0x3B: adRWAy( &Cpu::RLA ); break; case 0x23: adRWIx( &Cpu::RLA ); break; case 0x33: adRWIy( &Cpu::RLA ); break; /* RRA */ case 0x67: adRWZp( &Cpu::RRA ); break; case 0x77: adRWZx( &Cpu::RRA ); break; case 0x6F: adRWAb( &Cpu::RRA ); break; case 0x7F: adRWAx( &Cpu::RRA ); break; case 0x7B: adRWAy( &Cpu::RRA ); break; case 0x63: adRWIx( &Cpu::RRA ); break; case 0x73: adRWIy( &Cpu::RRA ); break; /* SAX */ case 0x87: adWrZp( cpu.A & cpu.X ); break; case 0x97: adWrZy( cpu.A & cpu.X ); break; case 0x8F: adWrAb( cpu.A & cpu.X ); break; case 0x83: adWrIx( cpu.A & cpu.X ); break; /* SLO */ case 0x07: adRWZp( &Cpu::SLO ); break; case 0x17: adRWZx( &Cpu::SLO ); break; case 0x0F: adRWAb( &Cpu::SLO ); break; case 0x1F: adRWAx( &Cpu::SLO ); break; case 0x1B: adRWAy( &Cpu::SLO ); break; case 0x03: adRWIx( &Cpu::SLO ); break; case 0x13: adRWIy( &Cpu::SLO ); break; /* SRE */ case 0x47: adRWZp( &Cpu::SRE ); break; case 0x57: adRWZx( &Cpu::SRE ); break; case 0x4F: adRWAb( &Cpu::SRE ); break; case 0x5F: adRWAx( &Cpu::SRE ); break; case 0x5B: adRWAy( &Cpu::SRE ); break; case 0x43: adRWIx( &Cpu::SRE ); break; case 0x53: adRWIy( &Cpu::SRE ); break; /* STP */ case 0x02: case 0x12: case 0x22: case 0x32: case 0x42: case 0x52: case 0x62: case 0x72: case 0x92: case 0xB2: case 0xD2: case 0xF2: cpuJammed = true; setMainTimestamp(runto); break; } } }
void Apu5C() { // LSR A LSR(IAPU.Registers.YA.B.A); IAPU.PC++; }
/*===================================================================*/ void K6502_Step( WORD wClocks ) { /* * Only the specified number of the clocks execute Op. * * Parameters * WORD wClocks (Read) * The number of the clocks */ BYTE byCode; WORD wA0; BYTE byD0; BYTE byD1; WORD wD0; // Dispose of it if there is an interrupt requirement if ( NMI_State != NMI_Wiring ) { // NMI Interrupt NMI_State = NMI_Wiring; CLK( 7 ); PUSHW( PC ); PUSH( F & ~FLAG_B ); RSTF( FLAG_D ); SETF( FLAG_I ); PC = K6502_ReadW( VECTOR_NMI ); } else if ( IRQ_State != IRQ_Wiring ) { // IRQ Interrupt // Execute IRQ if an I flag isn't being set if ( !( F & FLAG_I ) ) { IRQ_State = IRQ_Wiring; CLK( 7 ); PUSHW( PC ); PUSH( F & ~FLAG_B ); RSTF( FLAG_D ); SETF( FLAG_I ); PC = K6502_ReadW( VECTOR_IRQ ); } } // It has a loop until a constant clock passes while ( g_wPassedClocks < wClocks ) { // Read an instruction byCode = K6502_Read( PC++ ); // Execute an instruction. switch ( byCode ) { case 0x00: // BRK ++PC; PUSHW( PC ); SETF( FLAG_B ); PUSH( F ); SETF( FLAG_I ); RSTF( FLAG_D ); PC = K6502_ReadW( VECTOR_IRQ ); CLK( 7 ); break; case 0x01: // ORA (Zpg,X) ORA( A_IX ); CLK( 6 ); break; case 0x05: // ORA Zpg ORA( A_ZP ); CLK( 3 ); break; case 0x06: // ASL Zpg ASL( AA_ZP ); CLK( 5 ); break; case 0x08: // PHP SETF( FLAG_B ); PUSH( F ); CLK( 3 ); break; case 0x09: // ORA #Oper ORA( A_IMM ); CLK( 2 ); break; case 0x0A: // ASL A ASLA; CLK( 2 ); break; case 0x0D: // ORA Abs ORA( A_ABS ); CLK( 4 ); break; case 0x0e: // ASL Abs ASL( AA_ABS ); CLK( 6 ); break; case 0x10: // BPL Oper BRA( !( F & FLAG_N ) ); break; case 0x11: // ORA (Zpg),Y ORA( A_IY ); CLK( 5 ); break; case 0x15: // ORA Zpg,X ORA( A_ZPX ); CLK( 4 ); break; case 0x16: // ASL Zpg,X ASL( AA_ZPX ); CLK( 6 ); break; case 0x18: // CLC RSTF( FLAG_C ); CLK( 2 ); break; case 0x19: // ORA Abs,Y ORA( A_ABSY ); CLK( 4 ); break; case 0x1D: // ORA Abs,X ORA( A_ABSX ); CLK( 4 ); break; case 0x1E: // ASL Abs,X ASL( AA_ABSX ); CLK( 7 ); break; case 0x20: // JSR Abs JSR; CLK( 6 ); break; case 0x21: // AND (Zpg,X) AND( A_IX ); CLK( 6 ); break; case 0x24: // BIT Zpg BIT( A_ZP ); CLK( 3 ); break; case 0x25: // AND Zpg AND( A_ZP ); CLK( 3 ); break; case 0x26: // ROL Zpg ROL( AA_ZP ); CLK( 5 ); break; case 0x28: // PLP POP( F ); SETF( FLAG_R ); CLK( 4 ); break; case 0x29: // AND #Oper AND( A_IMM ); CLK( 2 ); break; case 0x2A: // ROL A ROLA; CLK( 2 ); break; case 0x2C: // BIT Abs BIT( A_ABS ); CLK( 4 ); break; case 0x2D: // AND Abs AND( A_ABS ); CLK( 4 ); break; case 0x2E: // ROL Abs ROL( AA_ABS ); CLK( 6 ); break; case 0x30: // BMI Oper BRA( F & FLAG_N ); break; case 0x31: // AND (Zpg),Y AND( A_IY ); CLK( 5 ); break; case 0x35: // AND Zpg,X AND( A_ZPX ); CLK( 4 ); break; case 0x36: // ROL Zpg,X ROL( AA_ZPX ); CLK( 6 ); break; case 0x38: // SEC SETF( FLAG_C ); CLK( 2 ); break; case 0x39: // AND Abs,Y AND( A_ABSY ); CLK( 4 ); break; case 0x3D: // AND Abs,X AND( A_ABSX ); CLK( 4 ); break; case 0x3E: // ROL Abs,X ROL( AA_ABSX ); CLK( 7 ); break; case 0x40: // RTI POP( F ); SETF( FLAG_R ); POPW( PC ); CLK( 6 ); break; case 0x41: // EOR (Zpg,X) EOR( A_IX ); CLK( 6 ); break; case 0x45: // EOR Zpg EOR( A_ZP ); CLK( 3 ); break; case 0x46: // LSR Zpg LSR( AA_ZP ); CLK( 5 ); break; case 0x48: // PHA PUSH( A ); CLK( 3 ); break; case 0x49: // EOR #Oper EOR( A_IMM ); CLK( 2 ); break; case 0x4A: // LSR A LSRA; CLK( 2 ); break; case 0x4C: // JMP Abs JMP( AA_ABS ); CLK( 3 ); break; case 0x4D: // EOR Abs EOR( A_ABS ); CLK( 4 ); break; case 0x4E: // LSR Abs LSR( AA_ABS ); CLK( 6 ); break; case 0x50: // BVC BRA( !( F & FLAG_V ) ); break; case 0x51: // EOR (Zpg),Y EOR( A_IY ); CLK( 5 ); break; case 0x55: // EOR Zpg,X EOR( A_ZPX ); CLK( 4 ); break; case 0x56: // LSR Zpg,X LSR( AA_ZPX ); CLK( 6 ); break; case 0x58: // CLI byD0 = F; RSTF( FLAG_I ); CLK( 2 ); if ( ( byD0 & FLAG_I ) && IRQ_State != IRQ_Wiring ) { IRQ_State = IRQ_Wiring; CLK( 7 ); PUSHW( PC ); PUSH( F & ~FLAG_B ); RSTF( FLAG_D ); SETF( FLAG_I ); PC = K6502_ReadW( VECTOR_IRQ ); } break; case 0x59: // EOR Abs,Y EOR( A_ABSY ); CLK( 4 ); break; case 0x5D: // EOR Abs,X EOR( A_ABSX ); CLK( 4 ); break; case 0x5E: // LSR Abs,X LSR( AA_ABSX ); CLK( 7 ); break; case 0x60: // RTS POPW( PC ); ++PC; CLK( 6 ); break; case 0x61: // ADC (Zpg,X) ADC( A_IX ); CLK( 6 ); break; case 0x65: // ADC Zpg ADC( A_ZP ); CLK( 3 ); break; case 0x66: // ROR Zpg ROR( AA_ZP ); CLK( 5 ); break; case 0x68: // PLA POP( A ); TEST( A ); CLK( 4 ); break; case 0x69: // ADC #Oper ADC( A_IMM ); CLK( 2 ); break; case 0x6A: // ROR A RORA; CLK( 2 ); break; case 0x6C: // JMP (Abs) JMP( K6502_ReadW2( AA_ABS ) ); CLK( 5 ); break; case 0x6D: // ADC Abs ADC( A_ABS ); CLK( 4 ); break; case 0x6E: // ROR Abs ROR( AA_ABS ); CLK( 6 ); break; case 0x70: // BVS BRA( F & FLAG_V ); break; case 0x71: // ADC (Zpg),Y ADC( A_IY ); CLK( 5 ); break; case 0x75: // ADC Zpg,X ADC( A_ZPX ); CLK( 4 ); break; case 0x76: // ROR Zpg,X ROR( AA_ZPX ); CLK( 6 ); break; case 0x78: // SEI SETF( FLAG_I ); CLK( 2 ); break; case 0x79: // ADC Abs,Y ADC( A_ABSY ); CLK( 4 ); break; case 0x7D: // ADC Abs,X ADC( A_ABSX ); CLK( 4 ); break; case 0x7E: // ROR Abs,X ROR( AA_ABSX ); CLK( 7 ); break; case 0x81: // STA (Zpg,X) STA( AA_IX ); CLK( 6 ); break; case 0x84: // STY Zpg STY( AA_ZP ); CLK( 3 ); break; case 0x85: // STA Zpg STA( AA_ZP ); CLK( 3 ); break; case 0x86: // STX Zpg STX( AA_ZP ); CLK( 3 ); break; case 0x88: // DEY --Y; TEST( Y ); CLK( 2 ); break; case 0x8A: // TXA A = X; TEST( A ); CLK( 2 ); break; case 0x8C: // STY Abs STY( AA_ABS ); CLK( 4 ); break; case 0x8D: // STA Abs STA( AA_ABS ); CLK( 4 ); break; case 0x8E: // STX Abs STX( AA_ABS ); CLK( 4 ); break; case 0x90: // BCC BRA( !( F & FLAG_C ) ); break; case 0x91: // STA (Zpg),Y STA( AA_IY ); CLK( 6 ); break; case 0x94: // STY Zpg,X STY( AA_ZPX ); CLK( 4 ); break; case 0x95: // STA Zpg,X STA( AA_ZPX ); CLK( 4 ); break; case 0x96: // STX Zpg,Y STX( AA_ZPY ); CLK( 4 ); break; case 0x98: // TYA A = Y; TEST( A ); CLK( 2 ); break; case 0x99: // STA Abs,Y STA( AA_ABSY ); CLK( 5 ); break; case 0x9A: // TXS SP = X; CLK( 2 ); break; case 0x9D: // STA Abs,X STA( AA_ABSX ); CLK( 5 ); break; case 0xA0: // LDY #Oper LDY( A_IMM ); CLK( 2 ); break; case 0xA1: // LDA (Zpg,X) LDA( A_IX ); CLK( 6 ); break; case 0xA2: // LDX #Oper LDX( A_IMM ); CLK( 2 ); break; case 0xA4: // LDY Zpg LDY( A_ZP ); CLK( 3 ); break; case 0xA5: // LDA Zpg LDA( A_ZP ); CLK( 3 ); break; case 0xA6: // LDX Zpg LDX( A_ZP ); CLK( 3 ); break; case 0xA8: // TAY Y = A; TEST( A ); CLK( 2 ); break; case 0xA9: // LDA #Oper LDA( A_IMM ); CLK( 2 ); break; case 0xAA: // TAX X = A; TEST( A ); CLK( 2 ); break; case 0xAC: // LDY Abs LDY( A_ABS ); CLK( 4 ); break; case 0xAD: // LDA Abs LDA( A_ABS ); CLK( 4 ); break; case 0xAE: // LDX Abs LDX( A_ABS ); CLK( 4 ); break; case 0xB0: // BCS BRA( F & FLAG_C ); break; case 0xB1: // LDA (Zpg),Y LDA( A_IY ); CLK( 5 ); break; case 0xB4: // LDY Zpg,X LDY( A_ZPX ); CLK( 4 ); break; case 0xB5: // LDA Zpg,X LDA( A_ZPX ); CLK( 4 ); break; case 0xB6: // LDX Zpg,Y LDX( A_ZPY ); CLK( 4 ); break; case 0xB8: // CLV RSTF( FLAG_V ); CLK( 2 ); break; case 0xB9: // LDA Abs,Y LDA( A_ABSY ); CLK( 4 ); break; case 0xBA: // TSX X = SP; TEST( X ); CLK( 2 ); break; case 0xBC: // LDY Abs,X LDY( A_ABSX ); CLK( 4 ); break; case 0xBD: // LDA Abs,X LDA( A_ABSX ); CLK( 4 ); break; case 0xBE: // LDX Abs,Y LDX( A_ABSY ); CLK( 4 ); break; case 0xC0: // CPY #Oper CPY( A_IMM ); CLK( 2 ); break; case 0xC1: // CMP (Zpg,X) CMP( A_IX ); CLK( 6 ); break; case 0xC4: // CPY Zpg CPY( A_ZP ); CLK( 3 ); break; case 0xC5: // CMP Zpg CMP( A_ZP ); CLK( 3 ); break; case 0xC6: // DEC Zpg DEC( AA_ZP ); CLK( 5 ); break; case 0xC8: // INY ++Y; TEST( Y ); CLK( 2 ); break; case 0xC9: // CMP #Oper CMP( A_IMM ); CLK( 2 ); break; case 0xCA: // DEX --X; TEST( X ); CLK( 2 ); break; case 0xCC: // CPY Abs CPY( A_ABS ); CLK( 4 ); break; case 0xCD: // CMP Abs CMP( A_ABS ); CLK( 4 ); break; case 0xCE: // DEC Abs DEC( AA_ABS ); CLK( 6 ); break; case 0xD0: // BNE BRA( !( F & FLAG_Z ) ); break; case 0xD1: // CMP (Zpg),Y CMP( A_IY ); CLK( 5 ); break; case 0xD5: // CMP Zpg,X CMP( A_ZPX ); CLK( 4 ); break; case 0xD6: // DEC Zpg,X DEC( AA_ZPX ); CLK( 6 ); break; case 0xD8: // CLD RSTF( FLAG_D ); CLK( 2 ); break; case 0xD9: // CMP Abs,Y CMP( A_ABSY ); CLK( 4 ); break; case 0xDD: // CMP Abs,X CMP( A_ABSX ); CLK( 4 ); break; case 0xDE: // DEC Abs,X DEC( AA_ABSX ); CLK( 7 ); break; case 0xE0: // CPX #Oper CPX( A_IMM ); CLK( 2 ); break; case 0xE1: // SBC (Zpg,X) SBC( A_IX ); CLK( 6 ); break; case 0xE4: // CPX Zpg CPX( A_ZP ); CLK( 3 ); break; case 0xE5: // SBC Zpg SBC( A_ZP ); CLK( 3 ); break; case 0xE6: // INC Zpg INC( AA_ZP ); CLK( 5 ); break; case 0xE8: // INX ++X; TEST( X ); CLK( 2 ); break; case 0xE9: // SBC #Oper SBC( A_IMM ); CLK( 2 ); break; case 0xEA: // NOP CLK( 2 ); break; case 0xEC: // CPX Abs CPX( A_ABS ); CLK( 4 ); break; case 0xED: // SBC Abs SBC( A_ABS ); CLK( 4 ); break; case 0xEE: // INC Abs INC( AA_ABS ); CLK( 6 ); break; case 0xF0: // BEQ BRA( F & FLAG_Z ); break; case 0xF1: // SBC (Zpg),Y SBC( A_IY ); CLK( 5 ); break; case 0xF5: // SBC Zpg,X SBC( A_ZPX ); CLK( 4 ); break; case 0xF6: // INC Zpg,X INC( AA_ZPX ); CLK( 6 ); break; case 0xF8: // SED SETF( FLAG_D ); CLK( 2 ); break; case 0xF9: // SBC Abs,Y SBC( A_ABSY ); CLK( 4 ); break; case 0xFD: // SBC Abs,X SBC( A_ABSX ); CLK( 4 ); break; case 0xFE: // INC Abs,X INC( AA_ABSX ); CLK( 7 ); break; /*-----------------------------------------------------------*/ /* Unlisted Instructions ( thanks to virtualnes ) */ /*-----------------------------------------------------------*/ case 0x1A: // NOP (Unofficial) case 0x3A: // NOP (Unofficial) case 0x5A: // NOP (Unofficial) case 0x7A: // NOP (Unofficial) case 0xDA: // NOP (Unofficial) case 0xFA: // NOP (Unofficial) CLK( 2 ); break; case 0x80: // DOP (CYCLES 2) case 0x82: // DOP (CYCLES 2) case 0x89: // DOP (CYCLES 2) case 0xC2: // DOP (CYCLES 2) case 0xE2: // DOP (CYCLES 2) PC++; CLK( 2 ); break; case 0x04: // DOP (CYCLES 3) case 0x44: // DOP (CYCLES 3) case 0x64: // DOP (CYCLES 3) PC++; CLK( 3 ); break; case 0x14: // DOP (CYCLES 4) case 0x34: // DOP (CYCLES 4) case 0x54: // DOP (CYCLES 4) case 0x74: // DOP (CYCLES 4) case 0xD4: // DOP (CYCLES 4) case 0xF4: // DOP (CYCLES 4) PC++; CLK( 4 ); break; case 0x0C: // TOP case 0x1C: // TOP case 0x3C: // TOP case 0x5C: // TOP case 0x7C: // TOP case 0xDC: // TOP case 0xFC: // TOP PC+=2; CLK( 4 ); break; default: // Unknown Instruction CLK( 2 ); #if 0 InfoNES_MessageBox( "0x%02x is unknown instruction.\n", byCode ) ; #endif break; } /* end of switch ( byCode ) */ } /* end of while ... */ // Correct the number of the clocks g_wPassedClocks -= wClocks; }
/* * Read a single byte from the serial port. Returns 1 on success, 0 * otherwise. When the function is succesfull, the character read is * written into its argument c. */ int serial_tstc (void) { return LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_DR; }
/* * Read a single byte from the serial port. Returns 1 on success, 0 * otherwise. When the function is succesfull, the character read is * written into its argument c. */ int serial_getc (void) { while (!(LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_DR)); return (char) RBR(CONFIG_SYS_IXP425_CONSOLE) & 0xff; }
void Apu5C() { // LSR A LSR(IAPU.YA.B.A); IAPU.PC++; }
/* typedef struct { char mnemonic[10]; char op1_type; // reconoce una r o un numeral char op2_type; char op3_type; uint32_t op1_value; guarda el numero del registro o el valor del inmediato uint32_t op2_value; uint32_t op3_value; }instruction_t; */ void decodeInstruction(instruction_t instruction,uint32_t* Rd, uint32_t* Rm, uint32_t* Rr, bool flg[], int*pc, uint8_t pila)// recibe el retorno de getInstruccion { uint32_t cero=0; if( strcmp(instruction.mnemonic,"PUSH") == 0 ) { } else if( strcmp(instruction.mnemonic,"ADD") == 0) { if((instruction.op1_type=='R')&&(instruction.op2_type=='R')&&(instruction.op3_type=='R')) { ADD(Rd[instruction.op1_value],Rm[instruction.op2_value],Rr[instruction.op3_value],flg,&pc); }else if((instruction.op1_type=='R')&&(instruction.op2_type=='R')&&(instruction.op3_type=='#')) ADD(&Rd[instruction.op1_value],&Rm[instruction.op2_value],&instruction.op3_value,flg, &pc); }else if( strcmp(instruction.mnemonic,"AND") == 0) { if((instruction.op1_type=='R')&&(instruction.op2_type=='R')&&(instruction.op3_type=='R')) { AND(&Rd[instruction.op1_value],&Rm[instruction.op2_value],&Rr[instruction.op3_value],&flg[0], &pc); }else if((instruction.op1_type=='R')&&(instruction.op2_type=='R')&&(instruction.op3_type=='#')) AND(&Rd[instruction.op1_value],&Rm[instruction.op2_value],instruction.op3_value,&flg[0], &pc); } else if( strcmp(instruction.mnemonic,"ASRS") == 0 ) { if((instruction.op1_type=='R')&&(instruction.op2_type=='R')) { ASRS(&Rd[instruction.op1_value],&Rm[instruction.op2_value], &pc); }else if((instruction.op1_type=='R')&&(instruction.op2_type=='#')) ASRS(&Rd[instruction.op1_value],instruction.op2_value, &pc); } else if( strcmp(instruction.mnemonic,"BIC") == 0 ) { if((instruction.op1_type=='R')&&(instruction.op2_type=='R')) { BIC(&Rd[instruction.op1_value],&Rm[instruction.op2_value], &pc); }else if((instruction.op1_type=='R')&&(instruction.op2_type=='#')) BIC(&Rd[instruction.op1_value],instruction.op2_value, &pc); } else if( strcmp(instruction.mnemonic,"CMN") == 0) { if((instruction.op1_type=='R')&&(instruction.op2_type=='R')&&(instruction.op3_type=='R')) { CMN(&Rd[instruction.op1_value],&Rm[instruction.op2_value],&Rr[instruction.op3_value], &pc); }else if((instruction.op1_type=='R')&&(instruction.op2_type=='R')&&(instruction.op3_type=='#')) CMN(&Rd[instruction.op1_value],&Rm[instruction.op2_value],instruction.op3_value, &pc); } else if( strcmp(instruction.mnemonic,"CMP") == 0 ) { if((instruction.op1_type=='R')&&(instruction.op2_type=='R')&&(instruction.op3_type=='R')) { CMP(&Rd[instruction.op1_value],&Rm[instruction.op2_value],&Rr[instruction.op3_value], &pc); }else if((instruction.op1_type=='R')&&(instruction.op2_type=='R')&&(instruction.op3_type=='#')) CMP(&Rd[instruction.op1_value],&Rm[instruction.op2_value],instruction.op3_value, &pc); } else if( strcmp(instruction.mnemonic,"EOR") == 0) {if((instruction.op1_type=='R')&&(instruction.op2_type=='R')&&(instruction.op3_type=='R')) { EOR(&Rd[instruction.op1_value],&Rm[instruction.op2_value],&Rr[instruction.op3_value],&flg[0], &pc); }else if((instruction.op1_type=='R')&&(instruction.op2_type=='R')&&(instruction.op3_type=='#')) EOR(&Rd[instruction.op1_value],&Rm[instruction.op2_value],instruction.op3_value,&flg[0], &pc); } else if( strcmp(instruction.mnemonic,"LSL") == 0 ) {if((instruction.op1_type=='R')&&(instruction.op2_type=='R')&&(instruction.op3_type=='R')) { LSL(&Rd[instruction.op1_value],&Rm[instruction.op2_value],instruction.op3_value, &pc); }else if((instruction.op1_type=='R')&&(instruction.op2_type=='R')&&(instruction.op3_type=='#')) LSL(&Rd[instruction.op1_value],&Rm[instruction.op2_value],cero, &pc); } else if( strcmp(instruction.mnemonic,"LSR") == 0) { {if((instruction.op1_type=='R')&&(instruction.op2_type=='R')&&(instruction.op3_type=='R')) { LSR(&Rd[instruction.op1_value],&Rm[instruction.op2_value],cero, &pc); }else if((instruction.op1_type=='R')&&(instruction.op2_type=='R')&&(instruction.op3_type=='#')) LSR(&Rd[instruction.op1_value],&Rm[instruction.op2_value],instruction.op3_value, &pc); } } else if( strcmp(instruction.mnemonic,"MOV") == 0) { if((instruction.op1_type=='R')&&(instruction.op2_type=='R')) { MOV(&Rd[instruction.op1_value],&Rm[instruction.op2_value],&flg[0], &pc); }else if((instruction.op1_type=='R')&&(instruction.op2_type=='#')) MOV(&Rd[instruction.op1_value],instruction.op2_value,&flg[0], &pc); } else if( strcmp(instruction.mnemonic,"MUL") == 0) { if((instruction.op1_type=='R')&&(instruction.op2_type=='R')&&(instruction.op3_type=='R')) { MUL(&Rd[instruction.op1_value],&Rm[instruction.op2_value],&Rr[instruction.op3_value],&flg[0], &pc); }else if((instruction.op1_type=='R')&&(instruction.op2_type=='R')&&(instruction.op3_type=='#')) MUL(&Rd[instruction.op1_value],&Rm[instruction.op2_value],instruction.op3_value,&flg[0], &pc); } else if(strcmp(instruction.mnemonic,"MVN") == 0) { if((instruction.op1_type=='R')&&(instruction.op2_type=='R')) { MVN(&Rd[instruction.op1_value],&Rm[instruction.op2_value], &pc); /* solo opera registros }else if((instruction.op1_type=='R')&&(instruction.op2_type=='#')) LSL(&Rd[instruction.op1_value],&instruction.op2_value); } */ } } else if(strcmp(instruction.mnemonic,"NOP") == 0 ) { NOP( &pc); } else if(strcmp(instruction.mnemonic,"OR") == 0) { if((instruction.op1_type=='R')&&(instruction.op2_type=='R')&&(instruction.op3_type=='R')) { OR(&Rd[instruction.op1_value],&Rm[instruction.op2_value],&Rr[instruction.op3_value],&flg[0], &pc); }else if((instruction.op1_type=='R')&&(instruction.op2_type=='R')&&(instruction.op3_type=='#')) OR(&Rd[instruction.op1_value],&Rm[instruction.op2_value],instruction.op3_value,&flg[0], &pc); } else if( strcmp(instruction.mnemonic,"REV") == 0 ) //1 { // instruction.op1_value --> Valor primer operando // instruction.op1_type --> Tipo primer operando (R->Registro #->Numero N->Ninguno) // ... Igual para los otros operandos } else if( strcmp(instruction.mnemonic,"REV16") == 0 ) //2 { // instruction.op1_value --> Valor primer operando // instruction.op1_type --> Tipo primer operando (R->Registro #->Numero N->Ninguno) // ... Igual para los otros operandos } else if( strcmp(instruction.mnemonic,"REVSH") == 0 )//3 { // instruction.op1_value --> Valor primer operando // instruction.op1_type --> Tipo primer operando (R->Registro #->Numero N->Ninguno) // ... Igual para los otros operandos } else if( strcmp(instruction.mnemonic,"ROR") == 0 ) { if((instruction.op1_type=='R')&&(instruction.op2_type=='R')) { ROR(&Rd[instruction.op1_value],&Rm[instruction.op2_value], &pc); } } else if( strcmp(instruction.mnemonic,"RSBS") == 0 ) { if((instruction.op1_type=='R')&&(instruction.op2_type=='R')) { RSBS(&Rd[instruction.op1_value],&Rm[instruction.op2_value], &pc); }else if((instruction.op1_type=='R')&&instruction.op2_type=='#') RSBS(&Rd[instruction.op1_value],instruction.op2_value, &pc); } else /*if( strcmp(instruction.mnemonic,"SBC") == 0 ) //4 { } else*/ if( strcmp(instruction.mnemonic,"SUB") == 0 ) { if((instruction.op1_type=='R')&&(instruction.op2_type=='R')&&(instruction.op3_type=='R')) { SUB(&Rd[instruction.op1_value],&Rm[instruction.op2_value],&Rr[instruction.op3_value],&flg[0], &pc); }else if((instruction.op1_type=='R')&&(instruction.op2_type=='R')&&(instruction.op3_type=='#')) SUB(&Rd[instruction.op1_value],&Rm[instruction.op2_value],instruction.op3_value,&flg[0], &pc); } else if( strcmp(instruction.mnemonic,"LDR") == 0) //5 { if((instruction.op1_type=='R')&&(instruction.op2_type=='R')&&(instruction.op3_type=='#')) { LDR(&Rd[instruction.op1_value],Rm[instruction.op1_value],instruction.op3_value); }else if ((instruction.op1_type=='R')&&(instruction.op2_type=='S')&&(instruction.op3_type=='#')) { LDR(&Rd[instruction.op1_value],pila,instruction.op3_value); }else if((instruction.op1_type=='R')&&(instruction.op2_type=='P')&&(instruction.op3_type=='#')) { LDR(&Rd[instruction.op1_value],pc,instruction.op3_value); }else if((instruction.op1_type=='R')&&(instruction.op2_type=='R')&&(instruction.op3_type=='R')) {LDR(&Rd[instruction.op1_value],Rd[instruction.op2_value],instruction.op3_value); } }else if( strcmp(instruction.mnemonic,"LDR") == 0) { } }
int uart_charav(int port) { return ((inb(LSR(port)) & 1) != 0); }