/* Starts a read operation via the MII link (non-blocking) */
void lpc_mii_read_noblock(u32_t PhyReg)
{
/* Read value at PHY address and register */
LPC_ETHERNET->MAC_MII_ADDR = MAC_MIIA_PA(LPC_PHYDEF_PHYADDR) |
MAC_MIIA_GR(PhyReg) | MAC_MIIA_CR(4);
LPC_ETHERNET->MAC_MII_ADDR |= MAC_MIIA_GB;
}
/* Write a value via the MII link (non-blocking) */
void lpc_mii_write_noblock(u32_t PhyReg, u32_t Value)
{
/* Write value at PHY address and register */
LPC_ETHERNET->MAC_MII_ADDR = MAC_MIIA_PA(LPC_PHYDEF_PHYADDR) |
MAC_MIIA_GR(PhyReg) | MAC_MIIA_CR(4) | MAC_MIIA_W;
LPC_ETHERNET->MAC_MII_DATA = Value;
LPC_ETHERNET->MAC_MII_ADDR |= MAC_MIIA_GB;
}
/* Sets up the PHY link clock divider and PHY address */
void IP_ENET_SetupMII(IP_ENET_001_Type *LPC_ENET, uint32_t div, uint8_t addr)
{
/* Save clock divider and PHY address in MII address register */
phyCfg = MAC_MIIA_PA(addr) | MAC_MIIA_CR(div);
}
/* Sets up the PHY link clock divider and PHY address */
void Chip_ENET_SetupMII(LPC_ENET_T *pENET, uint32_t div, uint8_t addr)
{
/* Save clock divider and PHY address in MII address register */
phyCfg = MAC_MIIA_PA(addr) | MAC_MIIA_CR(div);
}
