// System memory
.shared_mem_size = 1024 * 1024 * 1024, /* 1GB */
// Framebuffer physical address, only for validation usage
.fb_start = 0x80000000,
.fb_size = 0x80000000,
// DVFS
.utilization_interval = 200, /* ms */
.utilization_callback = mali_pmm_utilization_handler /*<utilization function>,*/
};
static struct resource mali_gpu_resources[] =
{
MALI_GPU_RESOURCES_MALI400_MP1(
IO_VIRT_TO_PHYS(MALI_BASE),
MT_MFG0_IRQ_ID,
MT_MFG1_IRQ_ID,
MT_MFG2_IRQ_ID,
MT_MFG3_IRQ_ID
)
};
static struct dev_pm_ops mali_gpu_device_type_pm_ops =
{
.suspend = mali_pm_suspend,
.resume = mali_pm_resume,
.freeze = mali_pm_suspend,
.thaw = mali_pm_resume,
.restore = mali_pm_resume,
#ifdef CONFIG_PM_RUNTIME
.runtime_suspend = mali_runtime_suspend,
static struct clk *sys_pll = NULL;
static struct clk *media_pll = NULL;
#endif
static struct clk *mali_clock = NULL; /* mali clk IP */
static struct clk *media_clk_g3d = NULL;
static struct regulator *mali_regulator = NULL; /* mali g3d regulator */
static u32 s_uwDebugFsPowerDown = 1;
static mali_bool g_swGpuPowerState = MALI_FALSE; /* globle power state,1 up ;0 down*/
static struct device_node *np = NULL;
static struct resource mali_gpu_resources_m400_mp1[] =
{
MALI_GPU_RESOURCES_MALI400_MP1(MALI_BASE_ADDR, MALI_IRQ_ID, MALI_IRQ_ID, MALI_IRQ_ID, MALI_IRQ_ID)
};
static struct resource mali_gpu_resources_m400_mp2[] =
{
MALI_GPU_RESOURCES_MALI400_MP2(MALI_BASE_ADDR, MALI_IRQ_ID, MALI_IRQ_ID, MALI_IRQ_ID, MALI_IRQ_ID, MALI_IRQ_ID, MALI_IRQ_ID)
};
static struct resource mali_gpu_resources_m450_mp4[] =
{
MALI_GPU_RESOURCES_MALI450_MP4(MALI_BASE_ADDR, MALI_IRQ_ID, MALI_IRQ_ID, MALI_IRQ_ID, MALI_IRQ_ID, MALI_IRQ_ID, MALI_IRQ_ID, MALI_IRQ_ID, MALI_IRQ_ID, MALI_IRQ_ID, MALI_IRQ_ID, MALI_IRQ_ID)
};
extern mali_bool mali_gpu_class_is_mali450;
/*****************************************************************************
function name : mali_os_suspend
MALI_GPU_RESOURCES_MALI400_MP2(0xd0060000,
INT_MALI_GP, INT_MALI_GP_MMU,
INT_MALI_PP, INT_MALI_PP2_MMU,
INT_MALI_PP_MMU, INT_MALI_PP2_MMU)
};
#else
#define INT_MALI_GP 48
#define INT_MALI_GP_MMU 49
#define INT_MALI_PP 50
#define INT_MALI_PP_MMU 51
static struct resource meson_mali_resources[] =
{
MALI_GPU_RESOURCES_MALI400_MP1(0xd0060000,
INT_MALI_GP, INT_MALI_GP_MMU, INT_MALI_PP, INT_MALI_PP_MMU)
};
#endif
static struct dev_pm_ops mali_gpu_device_type_pm_ops =
{
.suspend = mali_os_suspend,
.resume = mali_os_resume,
.freeze = mali_os_freeze,
.thaw = mali_os_thaw,
#ifdef CONFIG_PM_RUNTIME
.runtime_suspend = mali_runtime_suspend,
.runtime_resume = mali_runtime_resume,
.runtime_idle = mali_runtime_idle,
#endif
};
.shared_mem_size = 512 * 1024 * 1024, /* 1GB */
// Framebuffer physical address, only for validation usage
.fb_start = 0x80000000,
.fb_size = 0x80000000,
// DVFS
.control_interval = 8, /* ms */
.utilization_callback = mali_pmm_utilization_handler, /*<utilization function>,*/
};
static struct resource mali_gpu_resources_mp1[] =
{
MALI_GPU_RESOURCES_MALI400_MP1(
IO_VIRT_TO_PHYS(0xF3010000),
176, //MT_MFG_IRQ_GP_ID,
177, //MT_MFG_IRQ_GPMMU_ID ,
178, //MT_MFG_IRQ_PP0_ID,
179 //MT_MFG_IRQ_PPMMU0_ID
)
};
static struct resource mali_gpu_resources_mp2[] =
{
MALI_GPU_RESOURCES_MALI400_MP2(
IO_VIRT_TO_PHYS(0xF3010000),
176, //MT_MFG_IRQ_GP_ID,
177, //MT_MFG_IRQ_GPMMU_ID ,
178, //MT_MFG_IRQ_PP0_ID,
179, //MT_MFG_IRQ_PPMMU0_ID,
180, //MT_MFG_IRQ_PP1_ID,
181 //MT_MFG_IRQ_PPMMU1_ID
