#ifdef CONFIG_HAS_EARLYSUSPEND
static struct early_suspend mali_early_suspend_handler =
{
.level = EARLY_SUSPEND_LEVEL_DISABLE_FB + 100,
.suspend = mali_driver_early_suspend_scheduler,
.resume = mali_driver_late_resume_scheduler,
};
#endif /* CONFIG_HAS_EARLYSUSPEND */
static struct mali_gpu_device_data mali_gpu_data;
#if defined(CONFIG_ARCH_SUN8IW3P1) || defined(CONFIG_ARCH_SUN8IW5P1) || defined(CONFIG_ARCH_SUN8IW9P1)
static struct resource mali_gpu_resources[]=
{
MALI_GPU_RESOURCES_MALI400_MP2_PMU(SUNXI_GPU_PBASE, SUNXI_IRQ_GPUGP, SUNXI_IRQ_GPUGPMMU, \
SUNXI_IRQ_GPUPP0, SUNXI_IRQ_GPUPPMMU0, SUNXI_IRQ_GPUPP1, SUNXI_IRQ_GPUPPMMU1)
};
#elif defined(CONFIG_ARCH_SUN8IW7P1)
static struct resource mali_gpu_resources[]=
{
MALI_GPU_RESOURCES_MALI400_MP2_PMU(SUNXI_GPU_PBASE, SUNXI_IRQ_GPU_GP, SUNXI_IRQ_GPU_GPMMU, \
SUNXI_IRQ_GPU_PP0, SUNXI_IRQ_GPU_PPMMU0, SUNXI_IRQ_GPU_PP1, SUNXI_IRQ_GPU_PPMMU1)
};
#endif
static struct platform_device mali_gpu_device =
{
.name = MALI_GPU_NAME_UTGARD,
.id = 0,
.dev.coherent_dma_mask = DMA_BIT_MASK(32),
};
MALI_GPU_RESOURCES_MALI200(0xC0000000, -1, -1, -1)
};
static struct resource mali_gpu_resources_m300[] =
{
MALI_GPU_RESOURCES_MALI300_PMU(0xC0000000, -1, -1, -1, -1)
};
static struct resource mali_gpu_resources_m400_mp1[] =
{
MALI_GPU_RESOURCES_MALI400_MP1_PMU(0xC0000000, -1, -1, -1, -1)
};
static struct resource mali_gpu_resources_m400_mp2[] =
{
MALI_GPU_RESOURCES_MALI400_MP2_PMU(0xC0000000, -1, -1, -1, -1, -1, -1)
};
#endif
static struct platform_device mali_gpu_device =
{
.name = MALI_GPU_NAME_UTGARD,
.id = 0,
.dev.release = mali_platform_device_release,
};
static struct mali_gpu_device_data mali_gpu_data =
{
#if defined(CONFIG_ARCH_VEXPRESS)
.shared_mem_size =256 * 1024 * 1024, /* 256MB */
