Uart0::Error Uart0::send_raw(const char* data, uint32_t size) {
if (!is_open())
return kPortClosed;
/* Put the data in the buffer */
if (blocking) {
/* If blocking, wait for space in the buffer */
for (unsigned int i = 0; i < size; i++) {
char *data_ptr = const_cast<char *>(&data[i]);
out_buffer_.push(*data_ptr, portMAX_DELAY);
}
}
else {
/* If not blocking and there is no space in the buffer, return error */
for (unsigned int i = 0; i < size; i++) {
uint32_t buffer_ok;
char *data_ptr = const_cast<char *>(&data[i]);
buffer_ok = out_buffer_.push(*data_ptr, 0);
if (buffer_ok != pdTRUE)
return kBufferFull;
}
}
MAP_IntPendSet(INT_UARTA0);
return kOK;
}
//****************************************************************************
//
//! \brief This function simulates the nvic interrupt for TIMERA0
//!
//! \param none
//!
//! \return none
//
//****************************************************************************
void sw_simulate_timer_intr()
{
sw_simulate_timer = 1;
MAP_IntPendSet(INT_TIMERA0A);
}
//****************************************************************************
//
//! \brief This function simulates the nvic interrupt for RTC
//!
//! \param none
//!
//! \return none
//
//****************************************************************************
void sw_simulate_rtc_intr()
{
sw_simulate_rtc = 1;
MAP_IntPendSet(INT_PRCM);
}
/* Process events that have woken up system from S3 (LPDS) */
i32 cc_handle_S3_wakeup()
{
/* Trigger the SW interrupt */
MAP_IntPendSet(INT_PRCM);
return 0;
}
void pyb_sleep_suspend_exit (void) {
// take the I2C semaphore
uint32_t reg = HWREG(COMMON_REG_BASE + COMMON_REG_O_I2C_Properties_Register);
reg = (reg & ~0x3) | 0x1;
HWREG(COMMON_REG_BASE + COMMON_REG_O_I2C_Properties_Register) = reg;
// take the GPIO semaphore
reg = HWREG(COMMON_REG_BASE + COMMON_REG_O_GPIO_properties_register);
reg = (reg & ~0x3FF) | 0x155;
HWREG(COMMON_REG_BASE + COMMON_REG_O_GPIO_properties_register) = reg;
// restore de NVIC control registers
HWREG(NVIC_VTABLE) = nvic_reg_store->vector_table;
HWREG(NVIC_ACTLR) = nvic_reg_store->aux_ctrl;
HWREG(NVIC_INT_CTRL) = nvic_reg_store->int_ctrl_state;
HWREG(NVIC_APINT) = nvic_reg_store->app_int;
HWREG(NVIC_SYS_CTRL) = nvic_reg_store->sys_ctrl;
HWREG(NVIC_CFG_CTRL) = nvic_reg_store->config_ctrl;
HWREG(NVIC_SYS_PRI1) = nvic_reg_store->sys_pri_1;
HWREG(NVIC_SYS_PRI2) = nvic_reg_store->sys_pri_2;
HWREG(NVIC_SYS_PRI3) = nvic_reg_store->sys_pri_3;
HWREG(NVIC_SYS_HND_CTRL) = nvic_reg_store->sys_hcrs;
// restore the systick register
HWREG(NVIC_ST_CTRL) = nvic_reg_store->systick_ctrl;
HWREG(NVIC_ST_RELOAD) = nvic_reg_store->systick_reload;
HWREG(NVIC_ST_CAL) = nvic_reg_store->systick_calib;
// restore the interrupt priority registers
uint32_t *base_reg_addr = (uint32_t *)NVIC_PRI0;
for (uint32_t i = 0; i < (sizeof(nvic_reg_store->int_priority) / 4); i++) {
base_reg_addr[i] = nvic_reg_store->int_priority[i];
}
// restore the interrupt enable registers
base_reg_addr = (uint32_t *)NVIC_EN0;
for(uint32_t i = 0; i < (sizeof(nvic_reg_store->int_en) / 4); i++) {
base_reg_addr[i] = nvic_reg_store->int_en[i];
}
HAL_INTRODUCE_SYNC_BARRIER();
// ungate the clock to the shared spi bus
MAP_PRCMPeripheralClkEnable(PRCM_SSPI, PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK);
#if MICROPY_HW_ANTENNA_DIVERSITY
// re-configure the antenna selection pins
antenna_init0();
#endif
// reinitialize simplelink's interface
sl_IfOpen (NULL, 0);
// restore the configuration of all active peripherals
pyb_sleep_obj_wakeup();
// reconfigure all the previously enabled interrupts
mp_irq_wake_all();
// we need to init the crypto hash engine again
//CRYPTOHASH_Init();
// trigger a sw interrupt
MAP_IntPendSet(INT_PRCM);
// force an exception to go back to the point where suspend mode was entered
nlr_raise(mp_obj_new_exception(&mp_type_SystemExit));
}
