static void interrupt_handler()
{
uint32_t recv_data;
uint32_t status;
status = MAP_SPIIntStatus(GSPI_BASE,true);
MAP_SPIIntClear(GSPI_BASE,SPI_INT_RX_FULL|SPI_INT_TX_EMPTY);
if(status & SPI_INT_TX_EMPTY)
{
MAP_SPIDataPut(GSPI_BASE,tx_buffer[tx_count % TR_BUFF_SIZE]);
tx_count++;
}
if(status & SPI_INT_RX_FULL)
{
MAP_SPIDataGetNonBlocking(GSPI_BASE,&recv_data);
rx_buffer[rx_count % TR_BUFF_SIZE] = recv_data;
rx_count++;
}
interrupt_count++;
if(interrupt_count % (TR_BUFF_SIZE * 2) == 0 && interrupt_count > 0)
{
transfer_count++;
}
}
static void interrupt_handler()
{
uint32_t status = MAP_SPIIntStatus(GSPI_BASE,true);
MAP_SPIIntClear(GSPI_BASE,SPI_INT_EOW);
transfer_counter = (transfer_counter + DMA_SIZE) % BUFFER_SIZE;
if(transfer_counter == 0)
{
transfer_mode = !transfer_mode;
}
if(transfer_mode == RX)
{
spi_transfer(tx_buffer,data_buffer + transfer_counter);
}
if(transfer_mode == TX)
{
spi_transfer(data_buffer + transfer_counter,rx_buffer);
}
if(!(status & SPI_INT_EOW))
{
Message("Error: Unexpected SPI interrupt!\n\r");
while(1){};
}
}
/*
* ======== SPICC3200DMA_hwiFxn ========
* ISR for the SPI when we use the DMA is used.
*/
void SPICC3200DMA_hwiFxn(uintptr_t arg)
{
SPI_Transaction *msg;
SPICC3200DMA_Object *object = ((SPI_Handle)arg)->object;
SPICC3200DMA_HWAttrs const *hwAttrs = ((SPI_Handle)arg)->hwAttrs;
uint32_t intCode = 0;
DebugP_log1("SPI:(%p) interrupt context start", hwAttrs->baseAddr);
intCode = MAP_SPIIntStatus(hwAttrs->baseAddr, false);
if (intCode & SPI_INT_DMATX) {
/* DMA finished transfering; clear & disable interrupt */
MAP_SPIIntDisable(hwAttrs->baseAddr, SPI_INT_DMATX);
MAP_SPIIntClear(hwAttrs->baseAddr, SPI_INT_DMATX);
}
/* Determine if the TX & RX DMA channels have completed */
if ((object->transaction) &&
(MAP_uDMAChannelIsEnabled(hwAttrs->rxChannelIndex) == false) &&
(MAP_uDMAIntStatus() & (1 << hwAttrs->rxChannelIndex))) {
MAP_SPIDisable(hwAttrs->baseAddr);
MAP_SPICSDisable(hwAttrs->baseAddr);
MAP_SPIIntDisable(hwAttrs->baseAddr, SPI_INT_DMARX);
MAP_SPIIntClear(hwAttrs->baseAddr, SPI_INT_DMARX);
MAP_SPIIntClear(hwAttrs->baseAddr, SPI_INT_EOW);
/*
* Clear any pending interrupt
* As the TX DMA channel interrupt gets service, it may be possible
* that the RX DMA channel finished in the meantime, which means
* the IRQ for RX DMA channel is still pending...
*/
HwiP_clearInterrupt(hwAttrs->intNum);
/*
* Use a temporary transaction pointer in case the callback function
* attempts to perform another SPI_transfer call
*/
msg = object->transaction;
/* Indicate we are done with this transfer */
object->transaction = NULL;
/* Release constraint since transaction is done */
Power_releaseConstraint(PowerCC3200_DISALLOW_DEEPSLEEP);
DebugP_log2("SPI:(%p) DMA transaction: %p complete",
hwAttrs->baseAddr, (uintptr_t)msg);
object->transferCallbackFxn((SPI_Handle)arg, msg);
}
DebugP_log1("SPI:(%p) interrupt context end", hwAttrs->baseAddr);
}
