void HardwareSerial::begin(unsigned long baud)
{
baudRate = baud;
/* Set the UART to interrupt whenever the TX FIFO is almost empty or
* when any character is received. */
//MAP_UARTFIFOLevelSet(UART_BASE, UART_FIFO_TX7_8, UART_FIFO_RX7_8);
/* Initialize the UART. */
// UARTClockSourceSet(UART_BASE, UART_CLOCK_SYSTEM);
MAP_PRCMPeripheralReset(g_ulUARTPeriph[uartModule]);
MAP_PRCMPeripheralClkEnable(g_ulUARTPeriph[uartModule], PRCM_RUN_MODE_CLK);
MAP_PinTypeUART(g_ulUARTConfig[uartModule][0], PIN_MODE_3);
MAP_PinTypeUART(g_ulUARTConfig[uartModule][1], PIN_MODE_3);
MAP_UARTConfigSetExpClk(UART_BASE, 80000000, baudRate,
(UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE |
UART_CONFIG_WLEN_8));
flushAll();
MAP_IntEnable(g_ulUARTInt[uartModule]);
/* Enable the UART operation. */
MAP_UARTEnable(UART_BASE);
MAP_UARTIntEnable(UART_BASE, UART_INT_RT | UART_INT_TX);
}
//--------------------------------
void esp8266::ConfigureUART(uint32_t nBps) {
SysCtlPeripheralEnable(SYSCTL_PERIPH_UART1);
GPIOPinConfigure(GPIO_PC4_U1RX);
GPIOPinConfigure(GPIO_PC5_U1TX);
GPIOPinTypeUART(GPIO_PORTC_BASE, GPIO_PIN_4 | GPIO_PIN_5);
UARTClockSourceSet(UART_BASE, UART_CLOCK_PIOSC);
SetBitrate(nBps);
MAP_UARTFIFOLevelSet(UART_BASE, UART_FIFO_TX1_8, UART_FIFO_RX1_8);
MAP_UARTIntDisable(UART_BASE, 0xFFFFFFFF);
MAP_UARTIntEnable(UART_BASE, UART_INT_RX | UART_INT_RT);
MAP_IntEnable(UART_INT);
MAP_UARTEnable(UART_BASE);
}
void GPS_init()
{
dbg_printf("Initializing GPS module...");
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART);
MAP_GPIOPinConfigure(GPIO_PA0_U0RX);
MAP_GPIOPinConfigure(GPIO_PA1_U0TX);
MAP_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);
MAP_UARTConfigSetExpClk(UART_BASE, MAP_SysCtlClockGet(), UART_SPEED, UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE);
MAP_UARTDisable(UART_BASE);
MAP_UARTTxIntModeSet(UART_BASE, UART_TXINT_MODE_EOT);
MAP_UARTIntEnable(UART_BASE, UART_INT_RX | UART_INT_TX);
MAP_IntEnable(INT_UART);
MAP_UARTEnable(UART_BASE);
MAP_UARTFIFODisable(UART_BASE);
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG);
//
MAP_IntEnable(INT_GPIOG);
// Настроить прерывания на PPS
MAP_GPIOIntTypeSet(GPIO_PORTG_BASE, GPIO_PIN_7, GPIO_FALLING_EDGE);
MAP_GPIOPinIntEnable(GPIO_PORTG_BASE, GPIO_PIN_7);
//
if (tn_task_create(&task_GPS_tcb, &task_GPS_func, TASK_GPS_PRI,
&task_GPS_stk[TASK_GPS_STK_SZ - 1], TASK_GPS_STK_SZ, 0,
TN_TASK_START_ON_CREATION) != TERR_NO_ERR)
{
dbg_puts("tn_task_create(&task_GPS_tcb) error");
goto err;
}
// Настроить прерывания на PPS
//MAP_IntEnable(INT_GPIOG);
//MAP_GPIOIntTypeSet(GPIO_PORTG_BASE, GPIO_PIN_7, GPIO_FALLING_EDGE);
//MAP_GPIOPinIntEnable(GPIO_PORTG_BASE, GPIO_PIN_7);
dbg_puts("[done]");
return;
err:
dbg_trace();
tn_halt();
}
void SetupStdio(void)
{
//Put these into variables because passing macros to macros isnt fun.
const unsigned long srcClock = MAP_SysCtlClockGet();
const unsigned long baud = 115200;
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
MAP_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);
MAP_UARTConfigSetExpClk(UART0_BASE, srcClock, baud,
(UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE |
UART_CONFIG_WLEN_8));
MAP_UARTEnable(UART0_BASE);
}
u32 platform_uart_setup( unsigned id, u32 baud, int databits, int parity, int stopbits )
{
u32 config;
if( id < NUM_UART )
{
MAP_GPIOPinConfigure( uart_gpiofunc[ id << 1 ] );
MAP_GPIOPinConfigure( uart_gpiofunc[ ( id << 1 ) + 1 ] );
MAP_GPIOPinTypeUART( uart_gpio_base[ id ], uart_gpio_pins[ id ] );
switch( databits )
{
case 5:
config = UART_CONFIG_WLEN_5;
break;
case 6:
config = UART_CONFIG_WLEN_6;
break;
case 7:
config = UART_CONFIG_WLEN_7;
break;
default:
config = UART_CONFIG_WLEN_8;
break;
}
config |= ( stopbits == PLATFORM_UART_STOPBITS_1 ) ? UART_CONFIG_STOP_ONE : UART_CONFIG_STOP_TWO;
if( parity == PLATFORM_UART_PARITY_EVEN )
config |= UART_CONFIG_PAR_EVEN;
else if( parity == PLATFORM_UART_PARITY_ODD )
config |= UART_CONFIG_PAR_ODD;
else if( parity == PLATFORM_UART_PARITY_MARK )
config |= UART_CONFIG_PAR_ONE;
else if( parity == PLATFORM_UART_PARITY_SPACE )
config |= UART_CONFIG_PAR_ZERO;
else
config |= UART_CONFIG_PAR_NONE;
MAP_UARTConfigSetExpClk( uart_base[ id ], MAP_SysCtlClockGet(), baud, config );
MAP_UARTConfigGetExpClk( uart_base[ id ], MAP_SysCtlClockGet(), &baud, &config );
MAP_UARTEnable( uart_base[ id ] );
}
return baud;
}
//*****************************************************************************
//
//! Initializes the UART0 peripheral and sets up the TX and RX uDMA channels.
//! The UART is configured for loopback mode so that any data sent on TX will be
//! received on RX. The uDMA channels are configured so that the TX channel
//! will copy data from a buffer to the UART TX output. And the uDMA RX channel
//! will receive any incoming data into a pair of buffers in ping-pong mode.
//!
//! \param None
//!
//! \return None
//!
//*****************************************************************************
void
InitUART0Transfer(void)
{
unsigned int uIdx;
//
// Fill the TX buffer with a simple data pattern.
//
for(uIdx = 0; uIdx < UART_TXBUF_SIZE; uIdx++)
{
g_ucTxBuf[uIdx] = 65;
}
MAP_PRCMPeripheralReset(PRCM_UARTA0);
MAP_PRCMPeripheralClkEnable(PRCM_UARTA0,PRCM_RUN_MODE_CLK);
MAP_UARTConfigSetExpClk(CONSOLE,SYSCLK, UART_BAUD_RATE,
(UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE |
UART_CONFIG_PAR_NONE));
MAP_uDMAChannelAssign(UDMA_CH8_UARTA0_RX);
MAP_uDMAChannelAssign(UDMA_CH9_UARTA0_TX);
MAP_UARTIntRegister(UARTA0_BASE,UART0IntHandler);
//
// Set both the TX and RX trigger thresholds to 4. This will be used by
// the uDMA controller to signal when more data should be transferred. The
// uDMA TX and RX channels will be configured so that it can transfer 4
// bytes in a burst when the UART is ready to transfer more data.
//
MAP_UARTFIFOLevelSet(UARTA0_BASE, UART_FIFO_TX4_8, UART_FIFO_RX4_8);
//
// Enable the UART for operation, and enable the uDMA interface for both TX
// and RX channels.
//
MAP_UARTEnable(UARTA0_BASE);
//
// This register write will set the UART to operate in loopback mode. Any
// data sent on the TX output will be received on the RX input.
//
HWREG(UARTA0_BASE + UART_O_CTL) |= UART_CTL_LBE;
//
// Enable the UART peripheral interrupts. uDMA controller will cause an
// interrupt on the UART interrupt signal when a uDMA transfer is complete.
//
MAP_UARTIntEnable(UARTA0_BASE,UART_INT_DMATX);
MAP_UARTIntEnable(UARTA0_BASE,UART_INT_DMARX);
//
// Configure the control parameters for the UART TX. The uDMA UART TX
// channel is used to transfer a block of data from a buffer to the UART.
// The data size is 8 bits. The source address increment is 8-bit bytes
// since the data is coming from a buffer. The destination increment is
// none since the data is to be written to the UART data register. The
// arbitration size is set to 4, which matches the UART TX FIFO trigger
// threshold.
//
UDMASetupTransfer(UDMA_CH8_UARTA0_RX | UDMA_PRI_SELECT, UDMA_MODE_PINGPONG,
sizeof(g_ucRxBufA),UDMA_SIZE_8, UDMA_ARB_4,
(void *)(UARTA0_BASE + UART_O_DR), UDMA_SRC_INC_NONE,
g_ucRxBufA, UDMA_DST_INC_8);
UDMASetupTransfer(UDMA_CH8_UARTA0_RX | UDMA_ALT_SELECT, UDMA_MODE_PINGPONG,
sizeof(g_ucRxBufB),UDMA_SIZE_8, UDMA_ARB_4,
(void *)(UARTA0_BASE + UART_O_DR), UDMA_SRC_INC_NONE,
g_ucRxBufB, UDMA_DST_INC_8);
UDMASetupTransfer(UDMA_CH9_UARTA0_TX| UDMA_PRI_SELECT,
UDMA_MODE_BASIC,sizeof(g_ucTxBuf),UDMA_SIZE_8, UDMA_ARB_4,
g_ucTxBuf, UDMA_SRC_INC_8,(void *)(UARTA0_BASE + UART_O_DR),
UDMA_DST_INC_NONE);
MAP_UARTDMAEnable(UARTA0_BASE, UART_DMA_RX | UART_DMA_TX);
}
bool initializeUartChannel(uint8_t channel,
uint8_t uartPort,
uint32_t baudRate,
uint32_t cpuSpeedHz,
uint32_t flags)
{
if (channel >= UART_NUMBER_OF_CHANNELS ||
uartPort >= UART_COUNT)
{
return false;
}
if (uart2UartChannelData[uartPort] != 0)
{
return false;
}
if (!(flags & UART_FLAGS_RECEIVE) && !(flags & UART_FLAGS_SEND))
{
return false;
}
uint32_t uartBase;
uint32_t uartInterruptId;
uint32_t uartPeripheralSysCtl;
switch (uartPort)
{
#ifdef DEBUG
case UART_0:
{
uartBase = UART0_BASE;
uartInterruptId = INT_UART0;
uartPeripheralSysCtl = SYSCTL_PERIPH_UART0;
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);
ROM_GPIOPinConfigure(GPIO_PA0_U0RX);
ROM_GPIOPinConfigure(GPIO_PA1_U0TX);
ROM_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);
break;
}
#endif
case UART_1:
{
uartBase = UART1_BASE;
uartInterruptId = INT_UART1;
uartPeripheralSysCtl = SYSCTL_PERIPH_UART1;
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART1);
ROM_GPIOPinConfigure(GPIO_PB0_U1RX);
ROM_GPIOPinConfigure(GPIO_PB1_U1TX);
ROM_GPIOPinTypeUART(GPIO_PORTB_BASE, GPIO_PIN_0 | GPIO_PIN_1);
break;
}
case UART_2:
{
uartBase = UART2_BASE;
uartInterruptId = INT_UART2;
uartPeripheralSysCtl = SYSCTL_PERIPH_UART2;
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART2);
ROM_GPIOPinConfigure(GPIO_PD6_U2RX);
ROM_GPIOPinConfigure(GPIO_PD7_U2TX);
ROM_GPIOPinTypeUART(GPIO_PORTD_BASE, GPIO_PIN_6 | GPIO_PIN_7);
break;
}
case UART_3:
{
uartBase = UART3_BASE;
uartInterruptId = INT_UART3;
uartPeripheralSysCtl = SYSCTL_PERIPH_UART3;
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART3);
ROM_GPIOPinConfigure(GPIO_PC6_U3RX);
ROM_GPIOPinConfigure(GPIO_PC7_U3TX);
ROM_GPIOPinTypeUART(GPIO_PORTC_BASE, GPIO_PIN_6 | GPIO_PIN_7);
break;
}
case UART_4:
{
uartBase = UART4_BASE;
uartInterruptId = INT_UART4;
uartPeripheralSysCtl = SYSCTL_PERIPH_UART4;
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART4);
ROM_GPIOPinConfigure(GPIO_PC4_U4RX);
ROM_GPIOPinConfigure(GPIO_PC5_U4TX);
ROM_GPIOPinTypeUART(GPIO_PORTC_BASE, GPIO_PIN_4 | GPIO_PIN_5);
break;
}
default:
{
return false;
}
}
UARTClockSourceSet(uartBase, UART_CLOCK_PIOSC);
if(!MAP_SysCtlPeripheralPresent(uartPeripheralSysCtl))
{
return false;
}
MAP_SysCtlPeripheralEnable(uartPeripheralSysCtl);
MAP_UARTConfigSetExpClk(uartBase,
cpuSpeedHz,
baudRate,
(UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE | UART_CONFIG_WLEN_8));
MAP_UARTFIFOLevelSet(uartBase, UART_FIFO_TX1_8, UART_FIFO_RX1_8);
MAP_UARTIntDisable(uartBase, 0xFFFFFFFF);
if (flags & UART_FLAGS_RECEIVE)
{
MAP_UARTIntEnable(uartBase, UART_INT_RX | UART_INT_RT);
}
if (flags & UART_FLAGS_SEND)
{
MAP_UARTIntEnable(uartBase, UART_INT_TX);
}
MAP_IntEnable(uartInterruptId);
MAP_UARTEnable(uartBase);
uartChannelData[channel].base = uartBase;
uartChannelData[channel].interruptId = uartInterruptId;
uartChannelData[channel].writeBuffer.isEmpty = true;
uart2UartChannelData[uartPort] = &uartChannelData[channel];
return true;
}
Uart0::Error Uart0::config_uart() {
if (is_open())
return kPortAlreadyOpen;
uint32_t data_bits_cc3200;
switch (data_bits) {
case 5:
data_bits_cc3200 = UART_CONFIG_WLEN_5;
break;
case 6:
data_bits_cc3200 = UART_CONFIG_WLEN_6;
break;
case 7:
data_bits_cc3200 = UART_CONFIG_WLEN_7;
break;
case 8:
data_bits_cc3200 = UART_CONFIG_WLEN_8;
break;
default:
return kUnsuportedFeature;
}
uint32_t stop_bits_cc3200;
switch (stop_bits) {
case 1:
stop_bits_cc3200 = UART_CONFIG_STOP_ONE;
break;
case 2:
stop_bits_cc3200 = UART_CONFIG_STOP_TWO;
break;
default:
return kUnsuportedFeature;
}
uint32_t parity_cc3200;
switch (parity) {
case kParityEven:
parity_cc3200 = UART_CONFIG_PAR_EVEN;
break;
case kParityMark:
parity_cc3200 = UART_CONFIG_PAR_ONE;
break;
case kParityNone:
parity_cc3200 = UART_CONFIG_PAR_NONE;
break;
case kParityOdd:
parity_cc3200 = UART_CONFIG_PAR_ODD;
break;
case kParitySpace:
parity_cc3200 = UART_CONFIG_PAR_ZERO;
break;
default:
return kUnsuportedFeature;
}
MAP_UARTConfigSetExpClk(UARTA0_BASE, 80000000, baud,
(data_bits_cc3200 | stop_bits_cc3200 | parity_cc3200));
/*
* Disable UART to modify the configuration.
* This is needed because the SetExpClk function enables the UART
*/
MAP_UARTDisable(UARTA0_BASE);
switch (flow_control) {
case kFlowControlNone:
MAP_UARTFlowControlSet(UARTA0_BASE, UART_FLOWCONTROL_NONE);
break;
case kFlowControlHardware:
/* Enable RTS/CTS Flow Control */
if (mode == kModeDuplex)
MAP_UARTFlowControlSet(UARTA0_BASE,
UART_FLOWCONTROL_TX | UART_FLOWCONTROL_RX);
if (mode == kModeRxOnly)
MAP_UARTFlowControlSet(UARTA0_BASE,
UART_FLOWCONTROL_RX);
if (mode == kModeTxOnly)
MAP_UARTFlowControlSet(UARTA0_BASE,
UART_FLOWCONTROL_TX);
break;
default:
return kUnsuportedFeature;
break;
}
/* Register Interrupt */
MAP_UARTIntRegister(UARTA0_BASE, isr);
/* Enable Interrupt */
MAP_UARTTxIntModeSet(UARTA0_BASE, UART_TXINT_MODE_EOT);
MAP_UARTIntClear(UARTA0_BASE, UART_INT_TX | UART_INT_RX);
uint32_t interrupts = 0;
if ((mode == kModeDuplex) || (mode == kModeTxOnly))
interrupts |= UART_INT_TX;
if ((mode == kModeDuplex) || (mode == kModeRxOnly))
interrupts |= UART_INT_RX;
MAP_UARTIntEnable(UARTA0_BASE, interrupts);
/* Enable UART */
MAP_UARTEnable(UARTA0_BASE);
/* Disable Fifo */
MAP_UARTFIFODisable(UARTA0_BASE);
return kOK;
}
//*****************************************************************************
//
// The main function sets up the peripherals for the example, then enters
// a wait loop until the DMA transfers are complete. At the end some
// information is printed for the user.
//
//*****************************************************************************
int
main(void)
{
unsigned long ulIdx;
//
// Set the clocking to run directly from the PLL at 50 MHz.
//
MAP_SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN |
SYSCTL_XTAL_16MHZ);
//
// Initialize the console UART and write a message to the terminal.
//
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
MAP_GPIOPinConfigure(GPIO_PA0_U0RX);
MAP_GPIOPinConfigure(GPIO_PA1_U0TX);
MAP_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);
UARTStdioInit(0);
UARTprintf("\033[2JMemory/UART scatter-gather uDMA example\n\n");
//
// Configure UART1 to be used for the loopback peripheral
//
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART1);
//
// Configure the UART communication parameters.
//
MAP_UARTConfigSetExpClk(UART1_BASE, MAP_SysCtlClockGet(), 115200,
UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE |
UART_CONFIG_PAR_NONE);
//
// Set both the TX and RX trigger thresholds to one-half (8 bytes). This
// will be used by the uDMA controller to signal when more data should be
// transferred. The uDMA TX and RX channels will be configured so that it
// can transfer 8 bytes in a burst when the UART is ready to transfer more
// data.
//
MAP_UARTFIFOLevelSet(UART1_BASE, UART_FIFO_TX4_8, UART_FIFO_RX4_8);
//
// Enable the UART for operation, and enable the uDMA interface for both TX
// and RX channels.
//
MAP_UARTEnable(UART1_BASE);
MAP_UARTDMAEnable(UART1_BASE, UART_DMA_RX | UART_DMA_TX);
//
// This register write will set the UART to operate in loopback mode. Any
// data sent on the TX output will be received on the RX input.
//
HWREG(UART1_BASE + UART_O_CTL) |= UART_CTL_LBE;
//
// Enable the UART peripheral interrupts. Note that no UART interrupts
// were enabled, but the uDMA controller will cause an interrupt on the
// UART interrupt signal when a uDMA transfer is complete.
//
MAP_IntEnable(INT_UART1);
//
// Enable the uDMA peripheral clocking.
//
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_UDMA);
//
// Enable the uDMA controller.
//
MAP_uDMAEnable();
//
// Point at the control table to use for channel control structures.
//
MAP_uDMAControlBaseSet(sControlTable);
//
// Configure the UART TX channel for scatter-gather
// Peripheral scatter-gather is used because transfers are gated by
// requests from the peripheral
//
UARTprintf("Configuring UART TX uDMA channel for scatter-gather\n");
#ifndef USE_SGSET_API
//
// Use the original method for configuring the scatter-gather transfer
//
uDMAChannelControlSet(UDMA_CHANNEL_UART1TX, UDMA_SIZE_32 |
UDMA_SRC_INC_32 | UDMA_DST_INC_32 | UDMA_ARB_4);
uDMAChannelTransferSet(UDMA_CHANNEL_UART1TX, UDMA_MODE_PER_SCATTER_GATHER,
g_TaskTableSrc,
&sControlTable[UDMA_CHANNEL_UART1TX], 6 * 4);
#else
//
// Use the simplified API for configuring the scatter-gather transfer
//
uDMAChannelScatterGatherSet(UDMA_CHANNEL_UART1TX, 6, g_TaskTableSrc, 1);
#endif
//
// Configure the UART RX channel for scatter-gather task list.
// This is set to peripheral s-g because it starts by receiving data
// from the UART
//
UARTprintf("Configuring UART RX uDMA channel for scatter-gather\n");
#ifndef USE_SGSET_API
//
// Use the original method for configuring the scatter-gather transfer
//
uDMAChannelControlSet(UDMA_CHANNEL_UART1RX, UDMA_SIZE_32 |
UDMA_SRC_INC_32 | UDMA_DST_INC_32 | UDMA_ARB_4);
uDMAChannelTransferSet(UDMA_CHANNEL_UART1RX, UDMA_MODE_PER_SCATTER_GATHER,
g_TaskTableDst,
&sControlTable[UDMA_CHANNEL_UART1RX], 7 * 4);
#else
//
// Use the simplified API for configuring the scatter-gather transfer
//
uDMAChannelScatterGatherSet(UDMA_CHANNEL_UART1RX, 7, g_TaskTableDst, 1);
#endif
//
// Fill the source buffer with a pattern
//
for(ulIdx = 0; ulIdx < 1024; ulIdx++)
{
g_ucSrcBuf[ulIdx] = ulIdx + (ulIdx / 256);
}
//
// Enable the uDMA controller error interrupt. This interrupt will occur
// if there is a bus error during a transfer.
//
IntEnable(INT_UDMAERR);
//
// Enable the UART RX DMA channel. It will wait for data to be available
// from the UART.
//
UARTprintf("Enabling uDMA channel for UART RX\n");
MAP_uDMAChannelEnable(UDMA_CHANNEL_UART1RX);
//
// Enable the UART TX DMA channel. Since the UART TX will be asserting
// a DMA request (since the TX FIFO is empty), this will cause this
// DMA channel to start running.
//
UARTprintf("Enabling uDMA channel for UART TX\n");
MAP_uDMAChannelEnable(UDMA_CHANNEL_UART1TX);
//
// Wait for the TX task list to be finished
//
UARTprintf("Waiting for TX task list to finish ... ");
while(!g_bTXdone)
{
}
UARTprintf("done\n");
//
// Wait for the RX task list to be finished
//
UARTprintf("Waiting for RX task list to finish ... ");
while(!g_bRXdone)
{
}
UARTprintf("done\n");
//
// Verify that all the counters are in the expected state
//
UARTprintf("Verifying counters\n");
if(g_ulDMAIntCount != 2)
{
UARTprintf("ERROR in interrupt count, found %d, expected 2\n",
g_ulDMAIntCount);
}
if(g_uluDMAErrCount != 0)
{
UARTprintf("ERROR in error counter, found %d, expected 0\n",
g_uluDMAErrCount);
}
//
// Now verify the contents of the final destination buffer. Compare it
// to the original source buffer.
//
UARTprintf("Verifying buffer contents ... ");
for(ulIdx = 0; ulIdx < 1024; ulIdx++)
{
if(g_ucDstBuf[ulIdx] != g_ucSrcBuf[ulIdx])
{
UARTprintf("ERROR\n @ index %d: expected 0x%02X, found 0x%02X\n",
ulIdx, g_ucSrcBuf[ulIdx], g_ucDstBuf[ulIdx]);
UARTprintf("Checking stopped. There may be additional errors\n");
break;
}
}
if(ulIdx == 1024)
{
UARTprintf("OK\n");
}
//
// End of program, loop forever
//
for(;;)
{
}
}