/************************************************ halBsTimerStart() *************************************************/ void halBsTimerStart(void) { uint32_t reload; uint8_t prio; halTimerAdjustment = 0; halTimerExt.u.u32 = 0; reload = (bsAttr.timerBasicResNSec * SYSTEM_CLOCK) / (1 << (7 + 1)); reload = reload / 1000; /* Round up microsec*/ prio = (uint8_t)bsAttr.basicTimerPriority; MCF_INTC_ICR55 = (uint8_t)(MCF_INTC_ICR_IL(prio) | MCF_INTC_ICR_IP(0)); // Set PIT0 interrupt level MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK55; // Enable the PIT0 interrupt MCF_INTC_IMRL &= ~MCF_INTC_IMRL_MASKALL; // Enable interrupts MCF_PIT0_PCSR = MCF_PIT_PCSR_PRE(7) | MCF_PIT_PCSR_RLD | MCF_PIT_PCSR_DBG | MCF_PIT_PCSR_OVW; MCF_PIT0_PMR = (uint16_t)reload; MCF_PIT0_PCSR &= ~MCF_PIT_PCSR_OVW; MCF_PIT0_PCSR |= MCF_PIT_PCSR_EN; MCF_PIT1_PCSR = MCF_PIT_PCSR_PRE(7) | MCF_PIT_PCSR_OVW; MCF_PIT1_PMR = 0xffff; MCF_PIT1_PCSR |= MCF_PIT_PCSR_EN; /* MCF_PIT2_PCSR = MCF_PIT_PCSR_PRE(7) | MCF_PIT_PCSR_OVW; MCF_PIT2_PMR = 0xffff; MCF_PIT2_PCSR |= MCF_PIT_PCSR_EN; */ halBsTimerEnable(); }
BaseType_t xPortStartScheduler( void ) { extern void ( *portVECTOR_TABLE[ ] ) ( ); /* Add entry in vector table for yield system call. */ portVECTOR_TABLE[ portVECTOR_SYSCALL ] = prvPortYield; /* Add entry in vector table for periodic timer. */ portVECTOR_TABLE[ portVECTOR_TIMER ] = prvPortPreemptiveTick; /* Configure the timer for the system clock. */ if ( configTICK_RATE_HZ > 0) { /* Configure prescaler */ MCF_PIT_PCSR0 = MCF_PIT_PCSR_PRE( 0x9 ) | MCF_PIT_PCSR_RLD | MCF_PIT_PCSR_OVW; /* Initialize the periodic timer interrupt. */ MCF_PIT_PMR0 = MCF_PIT_MODULUS_REGISTER( configTICK_RATE_HZ ); /* Configure interrupt priority and level and unmask interrupt. */ MCF_INTC0_ICR36 = MCF_INTC0_ICRn_IL( 0x1 ) | MCF_INTC0_ICRn_IP( 0x1 ); MCF_INTC0_IMRH &= ~( MCF_INTC0_IMRH_INT_MASK36 | MCF_INTC0_IMRH_MASKALL ); /* Enable interrupts */ MCF_PIT_PCSR0 |= MCF_PIT_PCSR_PIE | MCF_PIT_PCSR_EN | MCF_PIT_PCSR_PIF; } /* Restore the context of the first task that is going to run. */ portRESTORE_CONTEXT( ); /* Should not get here. */ return pdTRUE; }
void pit0_init() { // Clear the enable bit so we can configure the timer MCF_PIT0_PCSR &= ~(MCF_PIT_PCSR_EN); // Write a prescaler of 1 which generates an interrupt every 3ms seconds MCF_PIT0_PCSR |= MCF_PIT_PCSR_PRE(0x05); // Timer will stop when execution is halted by the debugger MCF_PIT0_PCSR |= MCF_PIT_PCSR_DBG; // Allow overwriting over the PIT counter MCF_PIT0_PCSR |= MCF_PIT_PCSR_OVW; // Enable interrupts from PIT0 MCF_PIT0_PCSR |= MCF_PIT_PCSR_PIE; // Clear interrupt flag by writing a 1 MCF_PIT0_PCSR |= MCF_PIT_PCSR_PIF; // When PCNTR0 reaches 0, it is reloaded MCF_PIT0_PCSR |= MCF_PIT_PCSR_RLD; // Write 0 into PIT Modulus register (which will reset it to 0xFFFF) MCF_PIT0_PMR = MCF_PIT_PMR_PM(0); // Interrupt Controller: PIT0 interrupts as level 4 priority 7 (Source 55) MCF_INTC0_ICR55 |= MCF_INTC_ICR_IL(0x04); MCF_INTC0_ICR55 |= MCF_INTC_ICR_IP(0x07); // Unmask interrupts from the interrupt source MCF_INTC0_IMRH &= ~(1 << (55 - 32)); // Write PIT0 ISR address into the exception vector table (at position 64+55) __VECTOR_RAM[64+55] = (uint32)pit0_isr; g_pit0_counter = 0; // Enable timer MCF_PIT0_PCSR |= MCF_PIT_PCSR_EN; }