static void __init
mcpcia_startup_hose(struct pci_controller *hose)
{
int mid = MCPCIA_HOSE2MID(hose->index);
unsigned int tmp;
mcpcia_pci_clr_err(mid);
/*
* Set up error reporting.
*/
tmp = *(vuip)MCPCIA_CAP_ERR(mid);
tmp |= 0x0006; /* master/target abort */
*(vuip)MCPCIA_CAP_ERR(mid) = tmp;
mb();
tmp = *(vuip)MCPCIA_CAP_ERR(mid);
/*
* Set up the PCI->physical memory translation windows.
*
* Window 0 is scatter-gather 8MB at 8MB (for isa)
* Window 1 is scatter-gather (up to) 1GB at 1GB (for pci)
* Window 2 is direct access 2GB at 2GB
*/
hose->sg_isa = iommu_arena_new(hose, 0x00800000, 0x00800000, 0);
hose->sg_pci = iommu_arena_new(hose, 0x40000000,
size_for_memory(0x40000000), 0);
__direct_map_base = 0x80000000;
__direct_map_size = 0x80000000;
*(vuip)MCPCIA_W0_BASE(mid) = hose->sg_isa->dma_base | 3;
*(vuip)MCPCIA_W0_MASK(mid) = (hose->sg_isa->size - 1) & 0xfff00000;
*(vuip)MCPCIA_T0_BASE(mid) = virt_to_phys(hose->sg_isa->ptes) >> 8;
*(vuip)MCPCIA_W1_BASE(mid) = hose->sg_pci->dma_base | 3;
*(vuip)MCPCIA_W1_MASK(mid) = (hose->sg_pci->size - 1) & 0xfff00000;
*(vuip)MCPCIA_T1_BASE(mid) = virt_to_phys(hose->sg_pci->ptes) >> 8;
*(vuip)MCPCIA_W2_BASE(mid) = __direct_map_base | 1;
*(vuip)MCPCIA_W2_MASK(mid) = (__direct_map_size - 1) & 0xfff00000;
*(vuip)MCPCIA_T2_BASE(mid) = 0;
*(vuip)MCPCIA_W3_BASE(mid) = 0x0;
mcpcia_pci_tbi(hose, 0, -1);
*(vuip)MCPCIA_HBASE(mid) = 0x0;
mb();
*(vuip)MCPCIA_HAE_MEM(mid) = 0U;
mb();
*(vuip)MCPCIA_HAE_MEM(mid); /* read it back. */
*(vuip)MCPCIA_HAE_IO(mid) = 0;
mb();
*(vuip)MCPCIA_HAE_IO(mid); /* read it back. */
}
void
mcpcia_dma_init(struct mcpcia_config *ccp)
{
bus_dma_tag_t t;
/*
* Initialize the DMA tag used for direct-mapped DMA.
*/
t = &ccp->cc_dmat_direct;
t->_cookie = ccp;
t->_wbase = MCPCIA_DIRECT_MAPPED_BASE;
t->_wsize = MCPCIA_DIRECT_MAPPED_SIZE;
t->_next_window = &ccp->cc_dmat_pci_sgmap;
t->_boundary = 0;
t->_sgmap = NULL;
t->_get_tag = mcpcia_dma_get_tag;
t->_dmamap_create = _bus_dmamap_create;
t->_dmamap_destroy = _bus_dmamap_destroy;
t->_dmamap_load = _bus_dmamap_load_direct;
t->_dmamap_load_mbuf = _bus_dmamap_load_mbuf_direct;
t->_dmamap_load_uio = _bus_dmamap_load_uio_direct;
t->_dmamap_load_raw = _bus_dmamap_load_raw_direct;
t->_dmamap_unload = _bus_dmamap_unload;
t->_dmamap_sync = _bus_dmamap_sync;
t->_dmamem_alloc = _bus_dmamem_alloc;
t->_dmamem_free = _bus_dmamem_free;
t->_dmamem_map = _bus_dmamem_map;
t->_dmamem_unmap = _bus_dmamem_unmap;
t->_dmamem_mmap = _bus_dmamem_mmap;
/*
* Initialize the DMA tag used for sgmap-mapped PCI DMA.
*/
t = &ccp->cc_dmat_pci_sgmap;
t->_cookie = ccp;
t->_wbase = MCPCIA_PCI_SG_MAPPED_BASE;
t->_wsize = MCPCIA_PCI_SG_MAPPED_SIZE;
t->_next_window = NULL;
t->_boundary = 0;
t->_sgmap = &ccp->cc_pci_sgmap;
t->_pfthresh = MCPCIA_SG_MAPPED_PFTHRESH;
t->_get_tag = mcpcia_dma_get_tag;
t->_dmamap_create = alpha_sgmap_dmamap_create;
t->_dmamap_destroy = alpha_sgmap_dmamap_destroy;
t->_dmamap_load = mcpcia_bus_dmamap_load_sgmap;
t->_dmamap_load_mbuf = mcpcia_bus_dmamap_load_mbuf_sgmap;
t->_dmamap_load_uio = mcpcia_bus_dmamap_load_uio_sgmap;
t->_dmamap_load_raw = mcpcia_bus_dmamap_load_raw_sgmap;
t->_dmamap_unload = mcpcia_bus_dmamap_unload_sgmap;
t->_dmamap_sync = _bus_dmamap_sync;
t->_dmamem_alloc = _bus_dmamem_alloc;
t->_dmamem_free = _bus_dmamem_free;
t->_dmamem_map = _bus_dmamem_map;
t->_dmamem_unmap = _bus_dmamem_unmap;
t->_dmamem_mmap = _bus_dmamem_mmap;
/*
* Initialize the DMA tag used for sgmap-mapped ISA DMA.
*/
t = &ccp->cc_dmat_isa_sgmap;
t->_cookie = ccp;
t->_wbase = MCPCIA_ISA_SG_MAPPED_BASE;
t->_wsize = MCPCIA_ISA_SG_MAPPED_SIZE;
t->_next_window = NULL;
t->_boundary = 0;
t->_sgmap = &ccp->cc_isa_sgmap;
t->_pfthresh = MCPCIA_SG_MAPPED_PFTHRESH;
t->_get_tag = mcpcia_dma_get_tag;
t->_dmamap_create = alpha_sgmap_dmamap_create;
t->_dmamap_destroy = alpha_sgmap_dmamap_destroy;
t->_dmamap_load = mcpcia_bus_dmamap_load_sgmap;
t->_dmamap_load_mbuf = mcpcia_bus_dmamap_load_mbuf_sgmap;
t->_dmamap_load_uio = mcpcia_bus_dmamap_load_uio_sgmap;
t->_dmamap_load_raw = mcpcia_bus_dmamap_load_raw_sgmap;
t->_dmamap_unload = mcpcia_bus_dmamap_unload_sgmap;
t->_dmamap_sync = _bus_dmamap_sync;
t->_dmamem_alloc = _bus_dmamem_alloc;
t->_dmamem_free = _bus_dmamem_free;
t->_dmamem_map = _bus_dmamem_map;
t->_dmamem_unmap = _bus_dmamem_unmap;
t->_dmamem_mmap = _bus_dmamem_mmap;
/*
* Initialize the SGMAPs.
*/
alpha_sgmap_init(&ccp->cc_dmat_pci_sgmap, &ccp->cc_pci_sgmap,
"mcpcia pci sgmap",
MCPCIA_PCI_SG_MAPPED_BASE, 0, MCPCIA_PCI_SG_MAPPED_SIZE,
sizeof(uint64_t), NULL, 0);
alpha_sgmap_init(&ccp->cc_dmat_isa_sgmap, &ccp->cc_isa_sgmap,
"mcpcia isa sgmap",
MCPCIA_ISA_SG_MAPPED_BASE, 0, MCPCIA_ISA_SG_MAPPED_SIZE,
sizeof(uint64_t), NULL, 0);
/*
* Disable windows first.
*/
REGVAL(MCPCIA_W0_BASE(ccp)) = 0;
REGVAL(MCPCIA_W1_BASE(ccp)) = 0;
REGVAL(MCPCIA_W2_BASE(ccp)) = 0;
REGVAL(MCPCIA_W3_BASE(ccp)) = 0;
REGVAL(MCPCIA_T0_BASE(ccp)) = 0;
REGVAL(MCPCIA_T1_BASE(ccp)) = 0;
REGVAL(MCPCIA_T2_BASE(ccp)) = 0;
REGVAL(MCPCIA_T3_BASE(ccp)) = 0;
alpha_mb();
/*
* Set up window 0 as an 8MB SGMAP-mapped window starting at 8MB.
*/
REGVAL(MCPCIA_W0_MASK(ccp)) = MCPCIA_WMASK_8M;
REGVAL(MCPCIA_T0_BASE(ccp)) =
ccp->cc_isa_sgmap.aps_ptpa >> MCPCIA_TBASEX_SHIFT;
alpha_mb();
REGVAL(MCPCIA_W0_BASE(ccp)) =
MCPCIA_WBASE_EN | MCPCIA_WBASE_SG | MCPCIA_ISA_SG_MAPPED_BASE;
alpha_mb();
MCPCIA_SGTLB_INVALIDATE(ccp);
/*
* Set up window 1 as a 2 GB Direct-mapped window starting at 2GB.
*/
REGVAL(MCPCIA_W1_MASK(ccp)) = MCPCIA_WMASK_2G;
REGVAL(MCPCIA_T1_BASE(ccp)) = 0;
alpha_mb();
REGVAL(MCPCIA_W1_BASE(ccp)) =
MCPCIA_DIRECT_MAPPED_BASE | MCPCIA_WBASE_EN;
alpha_mb();
/*
* Set up window 2 as a 1G SGMAP-mapped window starting at 1G.
*/
REGVAL(MCPCIA_W2_MASK(ccp)) = MCPCIA_WMASK_1G;
REGVAL(MCPCIA_T2_BASE(ccp)) =
ccp->cc_pci_sgmap.aps_ptpa >> MCPCIA_TBASEX_SHIFT;
alpha_mb();
REGVAL(MCPCIA_W2_BASE(ccp)) =
MCPCIA_WBASE_EN | MCPCIA_WBASE_SG | MCPCIA_PCI_SG_MAPPED_BASE;
alpha_mb();
/* XXX XXX BEGIN XXX XXX */
{ /* XXX */
extern paddr_t alpha_XXX_dmamap_or; /* XXX */
alpha_XXX_dmamap_or = MCPCIA_DIRECT_MAPPED_BASE;/* XXX */
} /* XXX */
/* XXX XXX END XXX XXX */
}
