static void mhl_hpd_stat_isr(struct mhl_tx_ctrl *mhl_ctrl)
{
uint8_t intr_1_stat;
uint8_t cbus_stat;
struct i2c_client *client = mhl_ctrl->i2c_handle;
/* INTR STATUS 1 */
intr_1_stat = MHL_SII_PAGE0_RD(0x0071);
if (!intr_1_stat)
return;
/* Clear interrupts */
MHL_SII_PAGE0_WR(0x0071, intr_1_stat);
if (BIT6 & intr_1_stat) {
/*
* HPD status change event is pending
* Read CBUS HPD status for this info
* MSC REQ ABRT REASON
*/
cbus_stat = MHL_SII_CBUS_RD(0x0D);
if (BIT6 & cbus_stat)
mhl_drive_hpd(mhl_ctrl, HPD_UP);
}
return;
}
static void mhl_hpd_stat_isr(struct mhl_tx_ctrl *mhl_ctrl)
{
uint8_t intr_1_stat, cbus_stat, t;
unsigned long flags;
struct i2c_client *client = mhl_ctrl->i2c_handle;
if (!is_mhl_powered(mhl_ctrl))
return;
/* INTR STATUS 1 */
intr_1_stat = MHL_SII_PAGE0_RD(0x0071);
if (!intr_1_stat)
return;
/* Clear interrupts */
MHL_SII_PAGE0_WR(0x0071, intr_1_stat);
if (BIT6 & intr_1_stat) {
/*
* HPD status change event is pending
* Read CBUS HPD status for this info
* MSC REQ ABRT REASON
*/
cbus_stat = MHL_SII_CBUS_RD(0x0D);
pr_debug("%s: cbus_stat=[0x%02x] cur_pwr=[%u]\n",
__func__, cbus_stat, mhl_ctrl->cur_state);
spin_lock_irqsave(&mhl_ctrl->lock, flags);
t = mhl_ctrl->dwnstream_hpd;
spin_unlock_irqrestore(&mhl_ctrl->lock, flags);
if (BIT6 & (cbus_stat ^ t)) {
u8 status = cbus_stat & BIT6;
mhl_drive_hpd(mhl_ctrl, status ? HPD_UP : HPD_DOWN);
if (!status) {
MHL_SII_PAGE1_MOD(0x003D, BIT0, 0x00);
spin_lock_irqsave(&mhl_ctrl->lock, flags);
mhl_ctrl->tx_powered_off = true;
spin_unlock_irqrestore(&mhl_ctrl->lock, flags);
}
spin_lock_irqsave(&mhl_ctrl->lock, flags);
mhl_ctrl->dwnstream_hpd = cbus_stat;
spin_unlock_irqrestore(&mhl_ctrl->lock, flags);
}
}
}
/*
* Configure the initial reg settings
*/
static void mhl_init_reg_settings(struct mhl_tx_ctrl *mhl_ctrl,
bool mhl_disc_en)
{
uint8_t regval;
/*
* ============================================
* POWER UP
* ============================================
*/
struct i2c_client *client = mhl_ctrl->i2c_handle;
/* Power up 1.2V core */
MHL_SII_PAGE1_WR(0x003D, 0x3F);
/* Enable Tx PLL Clock */
MHL_SII_PAGE2_WR(0x0011, 0x01);
/* Enable Tx Clock Path and Equalizer */
MHL_SII_PAGE2_WR(0x0012, 0x11);
/* Tx Source Termination ON */
MHL_SII_REG_NAME_WR(REG_MHLTX_CTL1, 0x10);
/* Enable 1X MHL Clock output */
MHL_SII_REG_NAME_WR(REG_MHLTX_CTL6, 0xBC);
/* Tx Differential Driver Config */
MHL_SII_REG_NAME_WR(REG_MHLTX_CTL2, 0x3C);
MHL_SII_REG_NAME_WR(REG_MHLTX_CTL4, 0xC8);
/* PLL Bandwidth Control */
MHL_SII_REG_NAME_WR(REG_MHLTX_CTL7, 0x03);
MHL_SII_REG_NAME_WR(REG_MHLTX_CTL8, 0x0A);
/*
* ============================================
* Analog PLL Control
* ============================================
*/
/* Enable Rx PLL clock */
MHL_SII_REG_NAME_WR(REG_TMDS_CCTRL, 0x08);
MHL_SII_PAGE0_WR(0x00F8, 0x8C);
MHL_SII_PAGE0_WR(0x0085, 0x02);
MHL_SII_PAGE2_WR(0x0000, 0x00);
regval = MHL_SII_PAGE2_RD(0x0005);
regval &= ~BIT5;
MHL_SII_PAGE2_WR(0x0005, regval);
MHL_SII_PAGE2_WR(0x0013, 0x60);
/* PLL Cal ref sel */
MHL_SII_PAGE2_WR(0x0017, 0x03);
/* VCO Cal */
MHL_SII_PAGE2_WR(0x001A, 0x20);
/* Auto EQ */
MHL_SII_PAGE2_WR(0x0022, 0xE0);
MHL_SII_PAGE2_WR(0x0023, 0xC0);
MHL_SII_PAGE2_WR(0x0024, 0xA0);
MHL_SII_PAGE2_WR(0x0025, 0x80);
MHL_SII_PAGE2_WR(0x0026, 0x60);
MHL_SII_PAGE2_WR(0x0027, 0x40);
MHL_SII_PAGE2_WR(0x0028, 0x20);
MHL_SII_PAGE2_WR(0x0029, 0x00);
/* Rx PLL Bandwidth 4MHz */
MHL_SII_PAGE2_WR(0x0031, 0x0A);
/* Rx PLL Bandwidth value from I2C */
MHL_SII_PAGE2_WR(0x0045, 0x06);
MHL_SII_PAGE2_WR(0x004B, 0x06);
MHL_SII_PAGE2_WR(0x004C, 0x60);
/* Manual zone control */
MHL_SII_PAGE2_WR(0x004C, 0xE0);
/* PLL Mode value */
MHL_SII_PAGE2_WR(0x004D, 0x00);
MHL_SII_PAGE0_WR(0x0008, 0x35);
/*
* Discovery Control and Status regs
* Setting De-glitch time to 50 ms (default)
* Switch Control Disabled
*/
MHL_SII_REG_NAME_WR(REG_DISC_CTRL2, 0xAD);
/* 1.8V CBUS VTH */
MHL_SII_REG_NAME_WR(REG_DISC_CTRL5, 0x57);
/* RGND and single Discovery attempt */
MHL_SII_REG_NAME_WR(REG_DISC_CTRL6, 0x11);
/* Ignore VBUS */
MHL_SII_REG_NAME_WR(REG_DISC_CTRL8, 0x82);
/* Enable CBUS Discovery */
if (mhl_disc_en) {
MHL_SII_REG_NAME_WR(REG_DISC_CTRL9, 0x24);
/* Enable MHL Discovery */
MHL_SII_REG_NAME_WR(REG_DISC_CTRL1, 0x27);
/* Pull-up resistance off for IDLE state */
MHL_SII_REG_NAME_WR(REG_DISC_CTRL4, 0x8C);
} else {
MHL_SII_REG_NAME_WR(REG_DISC_CTRL9, 0x26);
/* Disable MHL Discovery */
MHL_SII_REG_NAME_WR(REG_DISC_CTRL1, 0x26);
MHL_SII_REG_NAME_WR(REG_DISC_CTRL4, 0x8C);
}
MHL_SII_REG_NAME_WR(REG_DISC_CTRL7, 0x20);
/* MHL CBUS Discovery - immediate comm. */
MHL_SII_REG_NAME_WR(REG_DISC_CTRL3, 0x86);
MHL_SII_PAGE3_WR(0x3C, 0x80);
if (mhl_ctrl->cur_state != POWER_STATE_D3)
MHL_SII_REG_NAME_MOD(REG_INT_CTRL, BIT6 | BIT5 | BIT4, BIT4);
/* Enable Auto Soft RESET */
MHL_SII_REG_NAME_WR(REG_SRST, 0x084);
/* HDMI Transcode mode enable */
MHL_SII_PAGE0_WR(0x000D, 0x1C);
cbus_reset(mhl_ctrl);
init_cbus_regs(client);
}
static void clear_all_intrs(struct i2c_client *client)
{
uint8_t regval = 0x00;
pr_debug_intr("********* exiting isr mask check ?? *************\n");
pr_debug_intr("int1 mask = %02X\n",
(int) MHL_SII_REG_NAME_RD(REG_INTR1));
pr_debug_intr("int3 mask = %02X\n",
(int) MHL_SII_PAGE0_RD(0x0077));
pr_debug_intr("int4 mask = %02X\n",
(int) MHL_SII_REG_NAME_RD(REG_INTR4));
pr_debug_intr("int5 mask = %02X\n",
(int) MHL_SII_REG_NAME_RD(REG_INTR5));
pr_debug_intr("cbus1 mask = %02X\n",
(int) MHL_SII_CBUS_RD(0x0009));
pr_debug_intr("cbus2 mask = %02X\n",
(int) MHL_SII_CBUS_RD(0x001F));
pr_debug_intr("********* end of isr mask check *************\n");
regval = MHL_SII_REG_NAME_RD(REG_INTR1);
pr_debug_intr("int1 st = %02X\n", (int)regval);
MHL_SII_REG_NAME_WR(REG_INTR1, regval);
regval = MHL_SII_REG_NAME_RD(REG_INTR2);
pr_debug_intr("int2 st = %02X\n", (int)regval);
MHL_SII_REG_NAME_WR(REG_INTR2, regval);
regval = MHL_SII_PAGE0_RD(0x0073);
pr_debug_intr("int3 st = %02X\n", (int)regval);
MHL_SII_PAGE0_WR(0x0073, regval);
regval = MHL_SII_REG_NAME_RD(REG_INTR4);
pr_debug_intr("int4 st = %02X\n", (int)regval);
MHL_SII_REG_NAME_WR(REG_INTR4, regval);
regval = MHL_SII_REG_NAME_RD(REG_INTR5);
pr_debug_intr("int5 st = %02X\n", (int)regval);
MHL_SII_REG_NAME_WR(REG_INTR5, regval);
regval = MHL_SII_CBUS_RD(0x0008);
pr_debug_intr("cbusInt st = %02X\n", (int)regval);
MHL_SII_CBUS_WR(0x0008, regval);
regval = MHL_SII_CBUS_RD(0x001E);
pr_debug_intr("CBUS intR_2: %d\n", (int)regval);
MHL_SII_CBUS_WR(0x001E, regval);
regval = MHL_SII_CBUS_RD(0x00A0);
pr_debug_intr("A0 int set = %02X\n", (int)regval);
MHL_SII_CBUS_WR(0x00A0, regval);
regval = MHL_SII_CBUS_RD(0x00A1);
pr_debug_intr("A1 int set = %02X\n", (int)regval);
MHL_SII_CBUS_WR(0x00A1, regval);
regval = MHL_SII_CBUS_RD(0x00A2);
pr_debug_intr("A2 int set = %02X\n", (int)regval);
MHL_SII_CBUS_WR(0x00A2, regval);
regval = MHL_SII_CBUS_RD(0x00A3);
pr_debug_intr("A3 int set = %02X\n", (int)regval);
MHL_SII_CBUS_WR(0x00A3, regval);
regval = MHL_SII_CBUS_RD(0x00B0);
pr_debug_intr("B0 st set = %02X\n", (int)regval);
MHL_SII_CBUS_WR(0x00B0, regval);
regval = MHL_SII_CBUS_RD(0x00B1);
pr_debug_intr("B1 st set = %02X\n", (int)regval);
MHL_SII_CBUS_WR(0x00B1, regval);
regval = MHL_SII_CBUS_RD(0x00B2);
pr_debug_intr("B2 st set = %02X\n", (int)regval);
MHL_SII_CBUS_WR(0x00B2, regval);
regval = MHL_SII_CBUS_RD(0x00B3);
pr_debug_intr("B3 st set = %02X\n", (int)regval);
MHL_SII_CBUS_WR(0x00B3, regval);
regval = MHL_SII_CBUS_RD(0x00E0);
pr_debug_intr("E0 st set = %02X\n", (int)regval);
MHL_SII_CBUS_WR(0x00E0, regval);
regval = MHL_SII_CBUS_RD(0x00E1);
pr_debug_intr("E1 st set = %02X\n", (int)regval);
MHL_SII_CBUS_WR(0x00E1, regval);
regval = MHL_SII_CBUS_RD(0x00E2);
pr_debug_intr("E2 st set = %02X\n", (int)regval);
MHL_SII_CBUS_WR(0x00E2, regval);
regval = MHL_SII_CBUS_RD(0x00E3);
pr_debug_intr("E3 st set = %02X\n", (int)regval);
MHL_SII_CBUS_WR(0x00E3, regval);
regval = MHL_SII_CBUS_RD(0x00F0);
pr_debug_intr("F0 int set = %02X\n", (int)regval);
MHL_SII_CBUS_WR(0x00F0, regval);
regval = MHL_SII_CBUS_RD(0x00F1);
pr_debug_intr("F1 int set = %02X\n", (int)regval);
MHL_SII_CBUS_WR(0x00F1, regval);
regval = MHL_SII_CBUS_RD(0x00F2);
pr_debug_intr("F2 int set = %02X\n", (int)regval);
MHL_SII_CBUS_WR(0x00F2, regval);
regval = MHL_SII_CBUS_RD(0x00F3);
pr_debug_intr("F3 int set = %02X\n", (int)regval);
MHL_SII_CBUS_WR(0x00F3, regval);
pr_debug_intr("********* end of exiting in isr *************\n");
}
