/*
* Routine: get_board_mem_timings
* Description: If we use SPL then there is no x-loader nor config header
* so we have to setup the DDR timings ourself on both banks.
*/
void get_board_mem_timings(struct board_sdrc_timings *timings)
{
int pop_mfr, pop_id;
/*
* We need to identify what PoP memory is on the board so that
* we know what timings to use. If we can't identify it then
* we know it's an xM. To map the ID values please see nand_ids.c
*/
identify_nand_chip(&pop_mfr, &pop_id);
timings->mr = MICRON_V_MR_165;
switch (get_board_revision()) {
case REVISION_C4:
if (pop_mfr == NAND_MFR_STMICRO && pop_id == 0xba) {
/* 512MB DDR */
timings->mcfg = NUMONYX_V_MCFG_165(512 << 20);
timings->ctrla = NUMONYX_V_ACTIMA_165;
timings->ctrlb = NUMONYX_V_ACTIMB_165;
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
break;
} else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xba) {
/* Beagleboard Rev C4, 512MB Nand/256MB DDR*/
timings->mcfg = MICRON_V_MCFG_165(128 << 20);
timings->ctrla = MICRON_V_ACTIMA_165;
timings->ctrlb = MICRON_V_ACTIMB_165;
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
break;
} else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xbc) {
/* Beagleboard Rev C5, 256MB DDR */
timings->mcfg = MICRON_V_MCFG_200(256 << 20);
timings->ctrla = MICRON_V_ACTIMA_200;
timings->ctrlb = MICRON_V_ACTIMB_200;
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
break;
}
case REVISION_XM_AB:
case REVISION_XM_C:
if (pop_mfr == 0) {
/* 256MB DDR */
timings->mcfg = MICRON_V_MCFG_200(256 << 20);
timings->ctrla = MICRON_V_ACTIMA_200;
timings->ctrlb = MICRON_V_ACTIMB_200;
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
} else {
/* 512MB DDR */
timings->mcfg = NUMONYX_V_MCFG_165(512 << 20);
timings->ctrla = NUMONYX_V_ACTIMA_165;
timings->ctrlb = NUMONYX_V_ACTIMB_165;
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
}
break;
default:
/* Assume 128MB and Micron/165MHz timings to be safe */
timings->mcfg = MICRON_V_MCFG_165(128 << 20);
timings->ctrla = MICRON_V_ACTIMA_165;
timings->ctrlb = MICRON_V_ACTIMB_165;
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
}
}
/*
* Routine: get_board_mem_timings
* Description: If we use SPL then there is no x-loader nor config header
* so we have to setup the DDR timings ourself on the first bank. This
* provides the timing values back to the function that configures
* the memory.
*/
void get_board_mem_timings(struct board_sdrc_timings *timings)
{
int pop_mfr, pop_id;
/*
* We need to identify what PoP memory is on the board so that
* we know what timings to use. To map the ID values please see
* nand_ids.c
*/
identify_nand_chip(&pop_mfr, &pop_id);
if (pop_mfr == NAND_MFR_HYNIX && pop_id == 0xbc) {
/* 256MB DDR */
timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
timings->ctrla = HYNIX_V_ACTIMA_200;
timings->ctrlb = HYNIX_V_ACTIMB_200;
} else {
/* 128MB DDR */
timings->mcfg = MICRON_V_MCFG_165(128 << 20);
timings->ctrla = MICRON_V_ACTIMA_165;
timings->ctrlb = MICRON_V_ACTIMB_165;
}
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
timings->mr = MICRON_V_MR_165;
}
/*
* Routine: get_board_mem_timings
* Description: If we use SPL then there is no x-loader nor config header
* so we have to setup the DDR timings ourself on both banks.
*/
void get_board_mem_timings(struct board_sdrc_timings *timings)
{
int pop_mfr, pop_id;
/*
* We need to identify what PoP memory is on the board so that
* we know what timings to use. If we can't identify it then
* we know it's an xM. To map the ID values please see nand_ids.c
*/
identify_nand_chip(&pop_mfr, &pop_id);
timings->mr = MICRON_V_MR_165;
if (pop_mfr == NAND_MFR_STMICRO && pop_id == 0xba) {
/* 512MB DDR */
timings->mcfg = NUMONYX_V_MCFG_165(512 << 20);
timings->ctrla = NUMONYX_V_ACTIMA_165;
timings->ctrlb = NUMONYX_V_ACTIMB_165;
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
} else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xba) {
timings->mcfg = MICRON_V_MCFG_165(128 << 20);
timings->ctrla = MICRON_V_ACTIMA_165;
timings->ctrlb = MICRON_V_ACTIMB_165;
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
} else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xbc) {
timings->mcfg = MICRON_V_MCFG_200(256 << 20);
timings->ctrla = MICRON_V_ACTIMA_200;
timings->ctrlb = MICRON_V_ACTIMB_200;
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
}
}
/*
* Routine: get_board_mem_timings
* Description: If we use SPL then there is no x-loader nor config header
* so we have to setup the DDR timings ourself on both banks.
*/
void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
u32 *mr)
{
int nand_mfr, nand_id;
/*
* We need to identify what PoP memory is on the board so that
* we know what timings to use. If we can't identify it then
* we know it's an xM. To map the ID values please see nand_ids.c
*/
identify_nand_chip(&nand_mfr, &nand_id);
*mr = MICRON_V_MR_165;
#ifdef DDRSIZE_256M
/* BlueShark, 256MB DDR 200MHz */
*mcfg = MICRON_V_MCFG_200(256 << 20);
*ctrla = MICRON_V_ACTIMA_200;
*ctrlb = MICRON_V_ACTIMB_200;
*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
#elif DDRSIZE_512M
/* BlueShark, 512MB DDR 200MHz */
*mcfg = MICRON_V_MCFG_200(512 << 20);
*ctrla = MICRON_V_ACTIMA_200;
*ctrlb = MICRON_V_ACTIMB_200;
*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
#else
/* Assume 128MB and Micron/165MHz timings to be safe */
*mcfg = MICRON_V_MCFG_165(128 << 20);
*ctrla = MICRON_V_ACTIMA_165;
*ctrlb = MICRON_V_ACTIMB_165;
*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
#endif
}
/*
* Routine: get_board_mem_timings
* Description: If we use SPL then there is no x-loader nor config header
* so we have to setup the DDR timings ourself on the first bank. This
* provides the timing values back to the function that configures
* the memory. We have either one or two banks of 128MB DDR.
*/
void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
u32 *mr)
{
/* General SDRC config */
*mcfg = MICRON_V_MCFG_165(128 << 20);
*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
/* AC timings */
*ctrla = MICRON_V_ACTIMA_165;
*ctrlb = MICRON_V_ACTIMB_165;
*mr = MICRON_V_MR_165;
}
/*
* Routine: get_board_mem_timings
* Description: If we use SPL then there is no x-loader nor config header
* so we have to setup the DDR timings ourself on both banks.
*/
void get_board_mem_timings(struct board_sdrc_timings *timings)
{
timings->mr = MICRON_V_MR_165;
switch (get_board_revision()) {
case REVISION_0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */
timings->mcfg = MICRON_V_MCFG_165(256 << 20);
timings->ctrla = MICRON_V_ACTIMA_165;
timings->ctrlb = MICRON_V_ACTIMB_165;
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
break;
case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */
case REVISION_4:
timings->mcfg = MICRON_V_MCFG_200(256 << 20);
timings->ctrla = MICRON_V_ACTIMA_200;
timings->ctrlb = MICRON_V_ACTIMB_200;
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
break;
case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */
timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
timings->ctrla = HYNIX_V_ACTIMA_200;
timings->ctrlb = HYNIX_V_ACTIMB_200;
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
break;
case REVISION_3: /* Micron 512MB/1024MB, 1/2 banks of 512MB */
timings->mcfg = MCFG(512 << 20, 15);
timings->ctrla = MICRON_V_ACTIMA_200;
timings->ctrlb = MICRON_V_ACTIMB_200;
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
break;
default:
timings->mcfg = MICRON_V_MCFG_165(128 << 20);
timings->ctrla = MICRON_V_ACTIMA_165;
timings->ctrlb = MICRON_V_ACTIMB_165;
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
}
}
/*
* Routine: get_board_mem_timings
* Description: If we use SPL then there is no x-loader nor config header
* so we have to setup the DDR timings ourself on the first bank. This
* provides the timing values back to the function that configures
* the memory. We have either one or two banks of 128MB DDR.
*/
void get_board_mem_timings(struct board_sdrc_timings *timings)
{
struct tricorder_eeprom eeprom;
get_eeprom(&eeprom);
/* General SDRC config */
if (eeprom.board_version[0] > 'D') {
/* use optimized timings for our SDRAM device */
timings->mcfg = MCFG((256 << 20), 14);
#define MT46H64M32_TDAL 6 /* Twr/Tck + Trp/tck */
/* 15/6 + 18/6 = 5.5 -> 6 */
#define MT46H64M32_TDPL 3 /* 15/6 = 2.5 -> 3 (Twr) */
#define MT46H64M32_TRRD 2 /* 12/6 = 2 */
#define MT46H64M32_TRCD 3 /* 18/6 = 3 */
#define MT46H64M32_TRP 3 /* 18/6 = 3 */
#define MT46H64M32_TRAS 7 /* 42/6 = 7 */
#define MT46H64M32_TRC 10 /* 60/6 = 10 */
#define MT46H64M32_TRFC 12 /* 72/6 = 12 */
timings->ctrla = ACTIM_CTRLA(MT46H64M32_TRFC, MT46H64M32_TRC,
MT46H64M32_TRAS, MT46H64M32_TRP,
MT46H64M32_TRCD, MT46H64M32_TRRD,
MT46H64M32_TDPL,
MT46H64M32_TDAL);
#define MT46H64M32_TWTR 1
#define MT46H64M32_TCKE 1
#define MT46H64M32_XSR 19 /* 112.5/6 = 18.75 => ~19 */
#define MT46H64M32_TXP 1
timings->ctrlb = ACTIM_CTRLB(MT46H64M32_TWTR, MT46H64M32_TCKE,
MT46H64M32_TXP, MT46H64M32_XSR);
timings->mr = MICRON_V_MR_165;
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
} else {
/* use conservative beagleboard timings as default */
timings->mcfg = MICRON_V_MCFG_165(128 << 20);
timings->ctrla = MICRON_V_ACTIMA_165;
timings->ctrlb = MICRON_V_ACTIMB_165;
timings->mr = MICRON_V_MR_165;
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
}
}
