static void
XPSetupForMono8x8PatternFill(ScrnInfoPtr pScrn,
int patternx, int patterny,
int fg, int bg, int rop,
unsigned int planemask)
{
TRIDENTPtr pTrident = TRIDENTPTR(pScrn);
int drawflag = 0;
REPLICATE(fg);
MMIO_OUT32(pTrident->IOBase, 0x2158, fg);
if (bg == -1) {
drawflag |= 1<<12;
MMIO_OUT32(pTrident->IOBase, 0x215C, ~fg);
} else {
REPLICATE(bg);
MMIO_OUT32(pTrident->IOBase, 0x215C, bg);
}
drawflag |= 7<<18;
TGUI_DRAWFLAG(PATMONO | drawflag);
MMIO_OUT32(pTrident->IOBase, 0x2180, patternx);
MMIO_OUT32(pTrident->IOBase, 0x2184, patterny);
TGUI_FMIX(XAAPatternROP[rop]);
}
static void
XPInitializeAccelerator(ScrnInfoPtr pScrn)
{
TRIDENTPtr pTrident = TRIDENTPTR(pScrn);
int shift;
/* This forces updating the clipper */
pTrident->Clipping = TRUE;
CHECKCLIPPING;
BLADE_XP_OPERMODE(pTrident->EngineOperation);
pTrident->EngineOperation |= 0x40;
switch (pScrn->bitsPerPixel) {
case 8:
default: /* Muffle compiler */
shift = 18;
break;
case 16:
shift = 19;
break;
case 32:
shift = 20;
break;
}
MMIO_OUT32(pTrident->IOBase, 0x2154, (pScrn->displayWidth) << shift);
MMIO_OUT32(pTrident->IOBase, 0x2150, (pScrn->displayWidth) << shift);
MMIO_OUT8(pTrident->IOBase, 0x2126, 3);
}
static void
XP4SubsequentFillRectSolid(ScrnInfoPtr pScrn, int x, int y, int w, int h)
{
TRIDENTPtr pTrident = TRIDENTPTR(pScrn);
MMIO_OUT32(pTrident->IOBase, 0x2138, x<<16 | y);
MMIO_OUT32(pTrident->IOBase, 0x2140, w<<16 | h);
XP4Sync(pScrn);
MMIO_OUT32(pTrident->IOBase, 0x2124, XAAGetPatternROP(ropcode) << 24 | bpp << 8 | 2);
}
static void
XP4SetupForFillRectSolid(ScrnInfoPtr pScrn, int color,
int rop, unsigned int planemask)
{
TRIDENTPtr pTrident = TRIDENTPTR(pScrn);
ropcode = rop;
REPLICATE(color);
MMIO_OUT32(pTrident->IOBase, 0x2158, color);
MMIO_OUT32(pTrident->IOBase, 0x2128, 1<<14);
}
static void virge_chipset_accel_shutdown (virge_chipset_io_t *virge_io) {
kgi_u_t foo;
if (!(CRT_IN8(virge_io, CRT_EXTMISCCONTROL1) & CR66_ENBL_ENH))
return; /* S3D Engine already disabled.*/
virge_chipset_accel_sync (virge_io);
/* Reset S3d Engine */
MMIO_OUT32(0x00008000, SUBSYSTEM_CONTROL);
MMIO_OUT32(0x00004000, SUBSYSTEM_CONTROL);
/* Wait till S3d Engine is ready. */
for (foo = MUCH; --foo && !(MMIO_IN32(SUBSYSTEM_CONTROL) & 0x02000););
if (0 == foo) KRN_DEBUG (0,"ViRGE: S3D Engine reset failed.");
}
static void
XP4SubsequentCPUToScreenColorExpandFill(
ScrnInfoPtr pScrn,
int x, int y, int w, int h,
int skipleft
){
TRIDENTPtr pTrident = TRIDENTPTR(pScrn);
MMIO_OUT32(pTrident->IOBase, 0x2138, x<<16 | y);
MMIO_OUT32(pTrident->IOBase, 0x2140, w<<16 | h);
XP4Sync(pScrn);
MMIO_OUT32(pTrident->IOBase, 0x2124, ropcode << 24 | bpp << 8 | 2);
}
static void virge_chipset_interrupts_enable (virge_chipset_io_t *virge_io, virge_chipset_t *virge)
{
kgi_u8_t crt11;
/* Clear vertical sync interrupt and enable it. */
if (virge->misc.subsys_ctl & SSC_VSY_ENB) {
crt11 = CRT_IN8(virge_io,0x11);
CRT_OUT8(virge_io, crt11 & ~0x30,0x11);
CRT_OUT8(virge_io, crt11 | 0x10,0x11);
}
/* Clear all pending enhanced interrupts and enable them */
MMIO_OUT32(0x0000007F, SUBSYSTEM_CONTROL);
MMIO_OUT32(virge->misc.subsys_ctl, SUBSYSTEM_CONTROL);
}
static void virge_chipset_interrupts_disable (virge_chipset_io_t *virge_io)
{
/* Switch off ViRGE interrupt generator and vertical retrace */
CRT_OUT8(virge_io, (CRT_IN8(virge_io, 0x11) & 0xDF) | 0x10, 0x11);
/* Disable all enhanced interrupts. */
MMIO_OUT32(0, SUBSYSTEM_CONTROL);
}
void Init3D( tridentContextPtr tmesa )
{
unsigned char *MMIO = tmesa->tridentScreen->mmio.map;
int i;
for(i=0;i<initRegDataNum;++i)
MMIO_OUT32(MMIO, initRegData[i].addr, initRegData[i].data);
}
static void virge_chipset_ddc1_init (virge_chipset_io_t * virge_io) {
/* Set the sync lines manually */
// KRN_DEBUG(1,"ddc1_init");
SEQ_OUT8(virge_io, (SEQ_IN8(virge_io, 0x0D) & 0x0C) | 0x52, 0x0D);
/* Let the DDC1 SDA line act as an input. */
//SEQ_OUT8(virge_io, 0x01, 0x1C);
//MMIO_OUT32(0x00000000, LPB_GENIOPORT);
//CRT_OUT8(virge_io, 0xff, 0x5C);
MMIO_OUT32(0x00000012, LPB_SERIALPORT);
}
static void
XPSetupForFillRectSolid(ScrnInfoPtr pScrn, int color,
int rop, unsigned int planemask)
{
TRIDENTPtr pTrident = TRIDENTPTR(pScrn);
REPLICATE(color);
TGUI_FMIX(XAAPatternROP[rop]);
MMIO_OUT32(pTrident->IOBase, 0x2158, color);
TGUI_DRAWFLAG(SOLIDFILL);
}
static void
XP4SubsequentScreenToScreenCopy(ScrnInfoPtr pScrn, int x1, int y1,
int x2, int y2, int w, int h)
{
TRIDENTPtr pTrident = TRIDENTPTR(pScrn);
if (pTrident->BltScanDirection & YNEG) {
y1 = y1 + h - 1;
y2 = y2 + h - 1;
}
if (pTrident->BltScanDirection & XNEG) {
x1 = x1 + w - 1;
x2 = x2 + w - 1;
}
MMIO_OUT32(pTrident->IOBase, 0x2138, x2<<16 | y2);
MMIO_OUT32(pTrident->IOBase, 0x213C, x1<<16 | y1);
MMIO_OUT32(pTrident->IOBase, 0x2140, w<<16 | h);
XP4Sync(pScrn);
MMIO_OUT32(pTrident->IOBase, 0x2124, XAAGetCopyROP(ropcode) << 24 | bpp << 8 | 1);
}
static void
XP4SetupForScreenToScreenCopy(ScrnInfoPtr pScrn,
int xdir, int ydir, int rop,
unsigned int planemask, int transparency_color)
{
TRIDENTPtr pTrident = TRIDENTPTR(pScrn);
int dst = 0;
pTrident->BltScanDirection = 0;
if (xdir < 0) pTrident->BltScanDirection |= XNEG;
if (ydir < 0) pTrident->BltScanDirection |= YNEG;
REPLICATE(transparency_color);
if (transparency_color != -1) {
dst |= 3<<16;
MMIO_OUT32(pTrident->IOBase, 0x2134, transparency_color);
}
ropcode = rop;
MMIO_OUT32(pTrident->IOBase, 0x2128, pTrident->BltScanDirection | SCR2SCR);
}
static void
XPSetupForScreenToScreenCopy(ScrnInfoPtr pScrn,
int xdir, int ydir, int rop,
unsigned int planemask, int transparency_color)
{
TRIDENTPtr pTrident = TRIDENTPTR(pScrn);
int dst = 0;
pTrident->BltScanDirection = 0;
if (xdir < 0) pTrident->BltScanDirection |= XNEG;
if (ydir < 0) pTrident->BltScanDirection |= YNEG;
REPLICATE(transparency_color);
if (transparency_color != -1) {
dst |= 3<<16;
MMIO_OUT32(pTrident->IOBase, 0x2134, transparency_color);
}
TGUI_DRAWFLAG(pTrident->BltScanDirection | SCR2SCR | dst);
TGUI_FMIX(XAACopyROP[rop]);
}
void xf86PokeMmio32(pointer Base, unsigned long Offset, CARD32 v)
{
MMIO_OUT32(Base,Offset,v);
}
int
Permedia3MemorySizeDetect(ScrnInfoPtr pScrn)
{
GLINTPtr pGlint = GLINTPTR (pScrn);
CARD32 size = 0, temp, temp1, temp2, i;
/* We can map 64MB, as that's the size of the Permedia3 aperture
* regardless of memory configuration */
pGlint->FbMapSize = 64*1024*1024;
#ifndef XSERVER_LIBPCIACCESS
/* Mark as VIDMEM_MMIO to avoid write-combining while detecting memory */
pGlint->FbBase = xf86MapPciMem(pScrn->scrnIndex, VIDMEM_MMIO,
pGlint->PciTag, pGlint->FbAddress, pGlint->FbMapSize);
#else
{
void** result = (void**)&pGlint->FbBase;
int err = pci_device_map_range(pGlint->PciInfo,
pGlint->FbAddress,
pGlint->FbMapSize,
PCI_DEV_MAP_FLAG_WRITABLE,
result);
if (err)
return FALSE;
}
#endif
if (pGlint->FbBase == NULL)
return 0;
temp = GLINT_READ_REG(PM3MemBypassWriteMask);
GLINT_SLOW_WRITE_REG(0xffffffff, PM3MemBypassWriteMask);
/* The Permedia3 splits up memory, and even replicates it. Grrr.
* So that each 32MB appears at offset 0, and offset 32, unless
* there's really 64MB attached to the chip.
* So, 16MB appears at offset 0, nothing between 16-32, then it re-appears
* at offset 32.
* This below is to detect the cases of memory combinations
*/
/* Test first 32MB */
for(i=0;i<32;i++) {
/* write test pattern */
MMIO_OUT32(pGlint->FbBase, i*1024*1024, i*0x00345678);
mem_barrier();
temp1 = MMIO_IN32(pGlint->FbBase, i*1024*1024);
/* Let's check for wrapover, write will fail at 16MB boundary */
if (temp1 == (i*0x00345678))
size = i;
else
break;
}
/* Ok, we're satisfied we've got 32MB, let's test the second lot */
if ((size + 1) == i) {
for(i=0;i<32;i++) {
/* Clear first 32MB */
MMIO_OUT32(pGlint->FbBase, i*1024*1024, 0);
}
mem_barrier();
for(i=32;i<64;i++) {
/* write test pattern */
MMIO_OUT32(pGlint->FbBase, i*1024*1024, i*0x00345678);
mem_barrier();
temp1 = MMIO_IN32(pGlint->FbBase, i*1024*1024);
temp2 = MMIO_IN32(pGlint->FbBase, (i-32)*1024*1024);
/* Let's check for wrapover */
if ( (temp1 == (i*0x00345678)) && (temp2 == 0) )
size = i;
else
break;
}
}
GLINT_SLOW_WRITE_REG(temp, PM3MemBypassWriteMask);
#ifndef XSERVER_LIBPCIACCESS
xf86UnMapVidMem(pScrn->scrnIndex, (pointer)pGlint->FbBase,
pGlint->FbMapSize);
#else
pci_device_unmap_range(pGlint->PciInfo, pGlint->FbBase, pGlint->FbMapSize);
#endif
pGlint->FbBase = NULL;
pGlint->FbMapSize = 0;
return ( (size+1) * 1024 );
}
static INLINE void trident_draw_quad( tridentContextPtr tmesa,
const tridentVertex *v0,
const tridentVertex *v1,
const tridentVertex *v2,
const tridentVertex *v3 )
{
GLuint vertsize = tmesa->vertex_size;
GLint coloridx = (vertsize > 4) ? 4 : 3;
unsigned char *MMIO = tmesa->tridentScreen->mmio.map;
int clr;
float *ftmp = (float *)(&clr);
if (tmesa->dirty)
tridentUploadHwStateLocked( tmesa );
#if 0
DrawTriangle(tmesa);
exit(0);
#else
#if 1
if (first) {
Init3D(tmesa);
#if 0
DrawTriangle(tmesa);
#endif
first = 0;
}
#endif
LOCK_HARDWARE( tmesa );
MMIO_OUT32(MMIO, 0x002C00 , 0x00000010 );
MMIO_OUT32(MMIO, 0x002C04 , 0x029C00C0 );
/* Z buffer */
MMIO_OUT32(MMIO, 0x002C24 , 0x00100000 /*| (tmesa->tridentScreen->depthOffset)*/ );
MMIO_OUT32(MMIO, 0x002C28 , 0xE0000000 | (tmesa->tridentScreen->depthPitch * 4) );
/* front buffer */
MMIO_OUT32(MMIO, 0x002C50 , 0x00000000 | (tmesa->drawOffset) );
MMIO_OUT32(MMIO, 0x002C54 , 0x0C320000 | (tmesa->drawPitch * 4) );
/* clipper */
MMIO_OUT32(MMIO, 0x002C80 , 0x20008000 | tmesa->tridentScreen->height );
MMIO_OUT32(MMIO, 0x002C84 , 0x20000000 | tmesa->tridentScreen->width );
/* writemask */
MMIO_OUT32(MMIO, 0x002C94 , 0xFFFFFFFF );
if (vertsize == 4) {
MMIO_OUT32(MMIO, 0x002818 , 0x0003A020 );
MMIO_OUT32(MMIO, 0x00281C , 0x00098021 );
*ftmp = v0->v.x;
MMIO_OUT32(MMIO, 0x002820 , clr );
*ftmp = v0->v.y;
MMIO_OUT32(MMIO, 0x002824 , clr );
*ftmp = v0->v.z;
MMIO_OUT32(MMIO, 0x002828 , clr );
#if 0
*ftmp = v0->v.w;
MMIO_OUT32(MMIO, 0x00282C , clr );
#endif
MMIO_OUT32(MMIO, 0x00282C , v0->ui[coloridx] );
*ftmp = v1->v.x;
MMIO_OUT32(MMIO, 0x002820 , clr );
*ftmp = v1->v.y;
MMIO_OUT32(MMIO, 0x002824 , clr );
*ftmp = v1->v.z;
MMIO_OUT32(MMIO, 0x002828 , clr );
#if 0
*ftmp = v1->v.w;
MMIO_OUT32(MMIO, 0x00282C , clr );
#endif
MMIO_OUT32(MMIO, 0x00282C , v1->ui[coloridx] );
*ftmp = v2->v.x;
MMIO_OUT32(MMIO, 0x002820 , clr );
*ftmp = v2->v.y;
MMIO_OUT32(MMIO, 0x002824 , clr );
*ftmp = v2->v.z;
MMIO_OUT32(MMIO, 0x002828 , clr );
#if 0
*ftmp = v2->v.w;
MMIO_OUT32(MMIO, 0x00282C , clr );
#endif
MMIO_OUT32(MMIO, 0x00282C , v2->ui[coloridx] );
MMIO_OUT32(MMIO, 0x00281C , 0x00093020 );
*ftmp = v3->v.x;
MMIO_OUT32(MMIO, 0x002820 , clr );
*ftmp = v3->v.y;
MMIO_OUT32(MMIO, 0x002824 , clr );
*ftmp = v3->v.z;
MMIO_OUT32(MMIO, 0x002828 , clr );
#if 0
*ftmp = v3->v.w;
MMIO_OUT32(MMIO, 0x00282C , clr );
#endif
MMIO_OUT32(MMIO, 0x00282C , v3->ui[coloridx] );
}
#endif
UNLOCK_HARDWARE( tmesa );
}
int DrawTriangle( tridentContextPtr tmesa)
{
unsigned char *MMIO = tmesa->tridentScreen->mmio.map;
dmaBufRec clr;
printf("DRAW TRI\n");
Init3D(tmesa);
printf("ENGINE STATUS 0x%x\n",MMIO_IN32(MMIO, 0x2800));
MMIO_OUT32(MMIO, 0x002800, 0x00000000 );
#if 0
MMIO_OUT32(MMIO, 0x002368 , MMIO_IN32(MMIO,0x002368)|1 );
#endif
MMIO_OUT32(MMIO, 0x002C00 , 0x00000014 );
#if 0
MMIO_OUT32(MMIO, 0x002C04 , 0x0A8004C0 );
#else
MMIO_OUT32(MMIO, 0x002C04 , 0x0A8000C0 );
#endif
#if 0
MMIO_OUT32(MMIO, 0x002C08 , 0x00000000 );
MMIO_OUT32(MMIO, 0x002C0C , 0xFFCCCCCC );
MMIO_OUT32(MMIO, 0x002C10 , 0x3F800000 );
MMIO_OUT32(MMIO, 0x002C14 , 0x3D0D3DCB );
MMIO_OUT32(MMIO, 0x002C2C , 0x70000000 );
MMIO_OUT32(MMIO, 0x002C24 , 0x00202C00 );
MMIO_OUT32(MMIO, 0x002C28 , 0xE0002500 );
MMIO_OUT32(MMIO, 0x002C30 , 0x00000000 );
MMIO_OUT32(MMIO, 0x002C34 , 0xE0000000 );
MMIO_OUT32(MMIO, 0x002C38 , 0x00000000 );
#endif
MMIO_OUT32(MMIO, 0x002C50 , 0x00000000 );
MMIO_OUT32(MMIO, 0x002C54 , 0x0C320C80 );
MMIO_OUT32(MMIO, 0x002C50 , 0x00000000 );
MMIO_OUT32(MMIO, 0x002C54 , 0x0C320C80 );
MMIO_OUT32(MMIO, 0x002C80 , 0x20008258 );
MMIO_OUT32(MMIO, 0x002C84 , 0x20000320 );
MMIO_OUT32(MMIO, 0x002C94 , 0xFFFFFFFF );
#if 0
MMIO_OUT32(MMIO, 0x002D00 , 0x00009009 );
MMIO_OUT32(MMIO, 0x002D38 , 0x00000000 );
MMIO_OUT32(MMIO, 0x002D94 , 0x20002000 );
MMIO_OUT32(MMIO, 0x002D50 , 0xf0000000 );
MMIO_OUT32(MMIO, 0x002D80 , 0x24002000 );
MMIO_OUT32(MMIO, 0x002D98 , 0x81000000 );
MMIO_OUT32(MMIO, 0x002DB0 , 0x81000000 );
MMIO_OUT32(MMIO, 0x002DC8 , 0x808000FF );
MMIO_OUT32(MMIO, 0x002DD4 , 0x02000200 );
MMIO_OUT32(MMIO, 0x002DD8 , 0x02000200 );
MMIO_OUT32(MMIO, 0x002D30 , 0x02092400 );
MMIO_OUT32(MMIO, 0x002D04 , 0x00102120 );
MMIO_OUT32(MMIO, 0x002D08 , 0xFFFFFFFF );
MMIO_OUT32(MMIO, 0x002D0C , 0xF00010D0 );
MMIO_OUT32(MMIO, 0x002D10 , 0xC0000400 );
#endif
MMIO_OUT32(MMIO, 0x002814, 0x00000000 );
#if 0
MMIO_OUT32(MMIO, 0x002818 , 0x00036C20 );
#else
MMIO_OUT32(MMIO, 0x002818 , 0x00036020 );
#endif
MMIO_OUT32(MMIO, 0x00281C , 0x00098081 );
printf("first TRI\n");
clr.f = 5.0;
MMIO_OUT32(MMIO, 0x002820 , clr.i );
clr.f = 595.0;
MMIO_OUT32(MMIO, 0x002824 , clr.i );
clr.f = 1.0;
MMIO_OUT32(MMIO, 0x002828 , clr.i );
MMIO_OUT32(MMIO, 0x00282C , 0x00FF00 );
#if 0
clr.f = 0.0;
MMIO_OUT32(MMIO, 0x002830 , clr.i );
clr.f = 1.0;
MMIO_OUT32(MMIO, 0x002834 , clr.i );
#endif
clr.f = 5.0;
MMIO_OUT32(MMIO, 0x002820 , clr.i );
clr.f = 5.0;
MMIO_OUT32(MMIO, 0x002824 , clr.i );
clr.f = 1.0;
MMIO_OUT32(MMIO, 0x002828 , clr.i );
MMIO_OUT32(MMIO, 0x00282C , 0xFF0000 );
#if 0
clr.f = 0.0;
MMIO_OUT32(MMIO, 0x002830 , clr.i );
clr.f = 0.0;
MMIO_OUT32(MMIO, 0x002834 , clr.i );
#endif
clr.f = 395.0;
printf("0x%x\n",clr.i);
MMIO_OUT32(MMIO, 0x002820 , clr.i );
clr.f = 5.0;
MMIO_OUT32(MMIO, 0x002824 , clr.i );
clr.f = 1.0;
MMIO_OUT32(MMIO, 0x002828 , clr.i );
MMIO_OUT32(MMIO, 0x00282C , 0xFF );
#if 0
clr.f = 1.0;
MMIO_OUT32(MMIO, 0x002830 , clr.i );
clr.f = 0.0;
MMIO_OUT32(MMIO, 0x002834 , clr.i );
#endif
printf("sec TRI\n");
MMIO_OUT32(MMIO, 0x00281C , 0x00093980 );
clr.f = 395.0;
MMIO_OUT32(MMIO, 0x002820 , clr.i );
clr.f = 595.0;
MMIO_OUT32(MMIO, 0x002824 , clr.i );
clr.f = 1.0;
MMIO_OUT32(MMIO, 0x002828 , clr.i );
MMIO_OUT32(MMIO, 0x00282C , 0x00FF00 );
#if 0
clr.f = 1.0;
MMIO_OUT32(MMIO, 0x002830 , clr.i );
clr.f = 1.0;
MMIO_OUT32(MMIO, 0x002834 , clr.i );
#endif
#if 0
MMIO_OUT32(MMIO, 0x002368 , MMIO_IN32(MMIO,0x002368)&0xfffffffe );
#endif
printf("fin TRI\n");
return 0;
}
kgi_error_t virge_chipset_irq_handler(virge_chipset_t *virge, virge_chipset_io_t *virge_io, irq_system_t *system)
{
kgi_u32_t handled = 0;
/* Get interrupt status and clear pending interrupts immediately */
kgi_u32_t sss = MMIO_IN32 (SUBSYSTEM_STATUS);
kgi_u32_t lif = MMIO_IN32 (LPB_INTR_FLAGS);
MMIO_OUT32(SSC_CLEAR_ALL_INTERRUPTS, SUBSYSTEM_CONTROL);
MMIO_OUT32(virge->misc.subsys_ctl, SUBSYSTEM_CONTROL);
CRT_OUT8(virge_io, CRT_IN8(virge_io, 0x11)&~0x30,0x11);
if (virge->misc.subsys_ctl & SSC_VSY_ENB)
CRT_OUT8(virge_io, CRT_IN8(virge_io, 0x11)|0x10,0x11);
/* Now act on pending interrupts. */
KRN_DEBUG(3, "Interrupt: SSS=0x%.8x",sss);
if (sss & SSS_VSY_INT)
{
/* Vertical Sync Interrupt */
handled |= SSS_VSY_INT;
KRN_TRACE(0, virge->interrupt.VSY++);
KRN_DEBUG(1, "VSY interrupt (pcidev %.8x)",
VIRGE_PCIDEV(virge_io));
}
if (sss & SSS_S3D_DON)
{
/* 3D Engine done */
handled |= SSS_S3D_DON;
KRN_TRACE(0, virge->interrupt.S3D_DON++);
KRN_DEBUG(1, "S3D_DON interrupt (pcidev %.8x)",
VIRGE_PCIDEV(virge_io));
}
if (sss & SSS_FIFO_OVF)
{
/* Command FIFO Overflow */
handled |= SSS_FIFO_OVF;
KRN_TRACE(0, virge->interrupt.FIFO_OVF++);
KRN_DEBUG(1, "FIFO_OVF interrupt (pcidev %.8x)",
VIRGE_PCIDEV(virge_io));
}
if (sss & SSS_FIFO_EMP)
{
/* Command FIFO Empty */
handled |= SSS_FIFO_EMP;
KRN_TRACE(0, virge->interrupt.FIFO_EMP++);
KRN_DEBUG(1, "FIFO_EMP interrupt (pcidev %.8x)",
VIRGE_PCIDEV(virge_io));
}
if (sss & SSS_HD_DON)
{
/* Host DMA Done */
handled |= SSS_HD_DON;
KRN_TRACE(0, virge->interrupt.HD_DON++);
KRN_DEBUG(1, "HD_DON interrupt (pcidev %.8x)",
VIRGE_PCIDEV(virge_io));
}
if (sss & SSS_CD_DON)
{
/* Command DMA Done */
handled |= SSS_CD_DON;
KRN_TRACE(0, virge->interrupt.CD_DON++);
KRN_DEBUG(1, "CD_DON interrupt (pcidev %.8x)",
VIRGE_PCIDEV(virge_io));
}
if (sss & SSS_S3DF_FIF)
{
/* S3d FIFO Empty */
handled |= SSS_S3DF_FIF;
KRN_TRACE(0, virge->interrupt.S3DF_FIF++);
KRN_DEBUG(1, "S3DF_FIF interrupt (pcidev %.8x)",
VIRGE_PCIDEV(virge_io));
}
if (sss & SSS_LPB_INT)
{
/* LPB Interrupt */
handled |= SSS_LPB_INT;
KRN_TRACE(0, virge->interrupt.LPB_INT++);
KRN_DEBUG(1, "LPB_INT interrupt (pcidev %.8x)",
VIRGE_PCIDEV(virge_io));
}
if (lif & LIF_SPS)
{
/* Serial Port Start */
KRN_TRACE(0, virge->interrupt.SPS++);
KRN_DEBUG(1, "SPS interrupt (pcidev %.8x)",
VIRGE_PCIDEV(virge_io));
}
if (sss & ~handled & 0x000000ff)
{
KRN_TRACE(0, virge->interrupt.not_handled++);
KRN_ERROR("virge: unhandled interrupt flag(s) %.8x (pcidev %.8x)", sss & ~handled, VIRGE_PCIDEV(virge_io));
}
if (!(sss & 0x000000ff))
{
KRN_TRACE(0, virge->interrupt.no_reason++);
KRN_ERROR("virge: interrupt but no reason indicated.");
}
return KGI_EOK;
}
static void virge_chipset_ddc1_done (virge_chipset_io_t * virge_io) {
// KRN_DEBUG(1,"ddc1_done");
SEQ_OUT8(virge_io, (SEQ_IN8(virge_io, 0x0D) & 0x0C) | 0x00, 0x0D);
MMIO_OUT32 (0x00000000,LPB_SERIALPORT);
}
