conf_object_t *
ts_new_instance(parse_object_t *pa)
{
trans_splitter_t *ts = MM_ZALLOC(1, trans_splitter_t);
SIM_log_constructor(&ts->log, pa);
ts->pool = MM_ZALLOC(TRANS_POOL_TOTAL, double_trans_t);
return (conf_object_t *) ts;
}
conf_object_t *ruby_new_instance(parse_object_t *pa) {
ruby_object_t *obj = MM_ZALLOC(1, ruby_object_t);
SIM_object_constructor((conf_object_t *)obj, pa);
obj->timing_interface = ruby_timing_interface;
return (conf_object_t *)obj;
}
/*
* This function is registered with the SIM_register_class
* call (see init_local() below), and is used as a constructor
* for every instance of the sample-device class.
*/
static conf_object_t *
sample_new_instance(parse_object_t *parse_obj)
{
sample_device_t *sample = MM_ZALLOC(1, sample_device_t);
SIM_log_constructor(&sample->log, parse_obj);
return &sample->log.obj;
}
DLL_EXPORT void
init_local(void)
{
class_data_t funcs;
conf_class_t *class;
io_memory_interface_t *memory_interface;
memset(&funcs, 0, sizeof(class_data_t));
funcs.new_instance = new_instance;
funcs.description =
DEVICE_NAME " is a simple device that dumps all "
"bytes written to a particular location in memory to "
"a file specified by the \"filename\" attribute.";
class = SIM_register_class(DEVICE_NAME, &funcs);
memory_interface = MM_ZALLOC(1, io_memory_interface_t);
memory_interface->operation = operation;
SIM_register_interface(class, IO_MEMORY_INTERFACE, memory_interface);
SIM_register_typed_attribute(class, "filename",
get_filename, NULL,
set_filename, NULL,
Sim_Attr_Optional,
"s", NULL,
"Filename to write bytes to. If not set, "
"bytes are only added to the device log.");
}
static conf_object_t *
id_splitter_new_instance(parse_object_t *pa)
{
id_splitter_t *ids = MM_ZALLOC(1, id_splitter_t);
SIM_object_constructor(&ids->obj, pa);
return &ids->obj;
}
static conf_object_t *
new_instance(parse_object_t *parse_obj)
{
byte_dump_device_t *bdd = MM_ZALLOC(1, byte_dump_device_t);
SIM_log_constructor(&bdd->log, parse_obj);
bdd->fd = -1;
return &bdd->log.obj;
}
static conf_object_t *
new_instance(parse_object_t *parse_obj)
{
uart_sampler_t *s = MM_ZALLOC(1, uart_sampler_t);
SIM_log_constructor(&s->log, parse_obj);
return &s->log.obj;
}
static conf_object_t *
ts_new_instance(parse_object_t *pa)
{
trans_splitter_t *ts = MM_ZALLOC(1, trans_splitter_t);
SIM_log_constructor(&ts->log, pa);
return (conf_object_t *) ts;
}
void
gc_set_config_line_number(generic_cache_t *gc, int line_number)
{
gc->config.line_number = line_number;
/* re-allocate the lines */
MM_FREE(gc->lines);
gc->lines = MM_ZALLOC(gc->config.line_number, cache_line_t);
update_precomputed_values(gc);
}
static conf_object_t *
new_instance(parse_object_t *parse_obj)
{
sample_i2c_device_t *dev = MM_ZALLOC(1, sample_i2c_device_t);
SIM_log_constructor(&dev->log, parse_obj);
i2c_device_init(&dev->log, &dev->i2c);
return &dev->log.obj;
}
/* called when a new cache is created */
conf_object_t *
gc_new_instance(parse_object_t *pa)
{
generic_cache_t *gc = MM_ZALLOC(1, generic_cache_t);
SIM_log_constructor(&gc->log, pa);
/* set default values in the cache */
gc_init_cache(gc);
return (conf_object_t *) gc;
}
//**************************************************************************
static conf_object_t *hfa_new_instance(parse_object_t *pa)
{
hfa_object_t *obj = MM_ZALLOC(1, hfa_object_t);
//hfa_object_t *obj;
SIM_object_constructor((conf_object_t *)obj, pa);
obj->timing_interface = &hfa_timing_interface;
obj->snoop_interface = &hfa_snoop_interface;
obj->event_poster_interface = &hfa_event_poster_interface;
return (conf_object_t *)obj;
}
conf_object_t *consistency_controller_new_instance(parse_object_t *pa)
{
consistency_controller_object_t *obj = MM_ZALLOC(1, consistency_controller_object_t);
SIM_log_constructor((log_object_t *)obj, pa);
obj->timing_interface = consistency_controller_timing_interface;
obj->load_load = 0;
obj->load_store = 0;
obj->store_load = 0;
obj->store_store = 0;
return (conf_object_t *)obj;
}
void
init_local(void)
{
class_data_t funcs;
conf_class_t *class;
i2c_device_interface_t *iface;
memset(&funcs, 0, sizeof(class_data_t));
funcs.new_instance = new_instance;
funcs.finalize_instance = finalize_instance;
funcs.description =
"The is the sample-i2c-device class which is an example of "
"how i2c devices can be written in Simics.";
class = SIM_register_class("sample-i2c-device", &funcs);
iface = MM_ZALLOC(1, i2c_device_interface_t);
iface->set_state = set_state;
iface->read_data = read_data;
iface->write_data = write_data;
SIM_register_interface(class, I2C_DEVICE_INTERFACE, iface);
register_i2c_device_attributes(class);
SIM_register_typed_attribute(class, "address",
get_address, NULL,
set_address, NULL,
Sim_Attr_Required,
"i", NULL,
"Address on the i2c bus.");
SIM_register_typed_attribute(class, "read_value",
get_read_value, NULL,
set_read_value, NULL,
Sim_Attr_Optional,
"i", NULL,
"Value to return on reads.");
SIM_register_typed_attribute(class, "written_value",
get_written_value, NULL,
set_written_value, NULL,
Sim_Attr_Optional,
"i", NULL,
"Last byte written to this device.");
}
/*
* init_local() is called once when the device module is loaded into Simics.
*/
void
init_local(void)
{
class_data_t funcs;
conf_class_t *sample_class;
sample_interface_t *sample_interface;
io_memory_interface_t *memory_interface;
/*
* Register the sample device class. The 'sample_new_instance'
* function serve as a constructor, and is called every time
* a new instance is created.
*/
memset(&funcs, 0, sizeof(class_data_t));
funcs.new_instance = sample_new_instance;
funcs.description =
"The sample-device device is a dummy device that compiles and "
"that can be loaded into Simics. Using it as a starting point "
"when writing own devices for Simics is encouraged. Several "
"device specific functions are included. The source is "
"included in <tt>simics/src/devices/sample-device</tt>.";
sample_class = SIM_register_class(DEVICE_NAME, &funcs);
/*
* Register the 'sample-interface', which is an example
* of a unique, customized interface that we've implemented
* for this device.
*/
sample_interface = MM_ZALLOC(1, sample_interface_t);
sample_interface->simple_function = simple_function;
SIM_register_interface(sample_class, "sample_interface",
sample_interface);
/*
* Register the 'io-memory' interface, which is an example
* of a generic interface that is implemented by a large
* number of devices.
*/
memory_interface = MM_ZALLOC(1, io_memory_interface_t);
memory_interface->operation = sample_operation;
SIM_register_interface(sample_class, IO_MEMORY_INTERFACE,
memory_interface);
/*
* Register attributes (device specific data) together with
* functions for getting and setting these attributes.
* The 'Sim_Attr_Optional' attribute will be saved with a configuration
*/
SIM_register_typed_attribute(
sample_class, "value",
get_value_attribute, NULL,
set_value_attribute, NULL,
Sim_Attr_Optional,
"i", NULL,
"The <i>value</i> field.");
/* Pseudo attribute, not saved in configuration */
SIM_register_typed_attribute(
sample_class, "add_log",
0, NULL,
set_add_log_attribute, NULL,
Sim_Attr_Pseudo,
"s", NULL,
"<i>Write-only</i>. Strings written to this "
"attribute will end up in the device's log file.");
/* Example of attribute using indexing */
SIM_register_typed_attribute(
sample_class, "range_sum",
get_range_sum_attribute, NULL,
0, NULL,
(attr_attr_t)(Sim_Attr_Pseudo | Sim_Attr_List_Indexed),
"i", "i",
"<i>Read-only</i>. When read from index <tt>[<i>i0</i>, "
"<i>i1</i>]</tt>, the sum of the integers between "
"<tt><i>i0</i></tt> and <tt><i>i1</i></tt> will "
"be returned.");
}
//**************************************************************************
void init_local() {
class_data_t ruby_funcs;
conf_class_t *ruby_class;
conf_object_t *ruby_obj;
attr_value_t val;
conf_object_t *phys_mem0;
/* Initialize and register the class "ruby-class". */
bzero(&ruby_funcs, sizeof(class_data_t));
ruby_funcs.new_instance = ruby_new_instance;
ruby_funcs.delete_instance = NULL;
ruby_class = SIM_register_class("ruby", &ruby_funcs);
/* initialize the variable reader: sets all global variables to defaults */
init_variables();
/* Initialize and register the timing-model interface */
ruby_timing_interface = MM_ZALLOC(1, timing_model_interface_t);
ruby_timing_interface->operate = ruby_operate;
SIM_register_interface(ruby_class, "timing-model", ruby_timing_interface);
ruby_obj = SIM_new_object(ruby_class, "ruby0");
phys_mem0 = SIM_get_object("phys_mem0");
if(phys_mem0 == NULL) {
/* Look for an object called "phys_mem" instead */
SIM_clear_exception();
phys_mem0 = SIM_get_object("phys_mem");
}
if(phys_mem0 == NULL) {
/* Okay, now we can panic */
#ifndef SIMICS30
/*
* Must load a checkpoint BEFORE load-module ruby
*/
printf("Please load a checkpoint BEFORE executing \"load-module ruby\"\n");
#endif
#ifdef SIMICS30
/*
* This case arises because of Simics 3.0:
* Simics 3.0 loads and "digitally signs" modules immediately after compiling them.
* This raises havoc with Multifacet's modules, since most of them require a checkpoint
* to be loaded BEFORE the module.
*/
printf("\033[34;1m\n");
printf(" /***************************************************************************\\\n");
printf(" > Physical Memory object cannot be found. If you are NOT compiling Ruby and <\n");
printf(" > you see this message, something is wrong. <\n");
printf(" > This message is part of the normal compilation process. <\n");
printf(" \\***************************************************************************/\033[m\n\n");
#endif
SIM_clear_exception();
return;
}
val.kind = Sim_Val_Object;
val.u.object = ruby_obj;
set_error_t install_error = SIM_set_attribute(phys_mem0, "timing_model", &val);
if (install_error == Sim_Set_Ok) {
printf( "successful installation of the ruby timing model.\n");
} else {
printf( "error installing ruby timing model.\n");
exit(1);
}
/* Initialize the snoop interface if we are tracking values in simics */
if (init_use_snoop() == 1) {
ruby_observe_interface = MM_ZALLOC(1, timing_model_interface_t);
ruby_observe_interface->operate = ruby_observe;
SIM_register_interface(ruby_class, "snoop-memory", ruby_observe_interface);
SIM_set_attribute(phys_mem0, "snoop_device", &val);
}
/* init_opal_interface calls to a static function in OpalInterface.C
* to determine is opal is installed. If it is, it registers itself,
* and notifies opal that ruby is loaded. Otherwise, it does nothing. */
opal_interface = MM_ZALLOC(1, mf_ruby_api_t);
SIM_register_interface(ruby_class, "mf-ruby-api", opal_interface);
init_opal_interface( opal_interface );
// register a number of commands
#define RUBY_COMMAND( COMMAND ) \
SIM_register_attribute( ruby_class, COMMAND, \
initvar_dispatch_get, (void *) COMMAND, \
initvar_dispatch_set, (void *) COMMAND, \
Sim_Attr_Session, \
"See documentation with associated ruby command." )
RUBY_COMMAND( "init" );
RUBY_COMMAND( "readparam" );
RUBY_COMMAND( "saveparam" );
RUBY_COMMAND( "param" );
RUBY_COMMAND( "dump-stats" );
RUBY_COMMAND( "dump-short-stats" );
RUBY_COMMAND( "periodic-stats-file" );
RUBY_COMMAND( "periodic-stats-interval" );
RUBY_COMMAND( "clear-stats" );
RUBY_COMMAND( "system-recovery" );
RUBY_COMMAND( "debug-verb" );
RUBY_COMMAND( "debug-filter" );
RUBY_COMMAND( "debug-output-file" );
RUBY_COMMAND( "debug-start-time" );
RUBY_COMMAND( "set-checkpoint-interval" );
RUBY_COMMAND( "load-caches" );
RUBY_COMMAND( "save-caches" );
RUBY_COMMAND( "dump-cache" );
RUBY_COMMAND( "dump-cache-data" );
RUBY_COMMAND( "tracer-output-file" );
RUBY_COMMAND( "set-procs-per-chip" );
RUBY_COMMAND( "abort-all" );
RUBY_COMMAND( "xact-visualizer-file" );
RUBY_COMMAND( "print-temp" );
RUBY_COMMAND( "reset-temp" );
RUBY_COMMAND( "print-reuse" );
RUBY_COMMAND( "reset-reuse" );
// Add end_transaction magic callback
SIM_hap_add_callback("Core_Magic_Instruction", (obj_hap_func_t) magic_instruction_callback, NULL);
#ifdef SPARC
SIM_hap_add_callback("Core_Exception", (obj_hap_func_t) ctrl_exception_start, NULL);
SIM_hap_add_callback("Core_Exception_Return", (obj_hap_func_t) ctrl_exception_done, NULL);
SIM_hap_add_callback("Core_Mode_Change", (obj_hap_func_t) change_mode_callback, NULL);
/// for MMU
SIM_hap_add_callback("MMU_Data_TLB_Demap", (obj_hap_func_t) dtlb_demap_callback, NULL);
SIM_hap_add_callback("MMU_Data_TLB_Map", (obj_hap_func_t) dtlb_map_callback, NULL);
SIM_hap_add_callback("MMU_Data_TLB_Overwrite", (obj_hap_func_t) dtlb_overwrite_callback, NULL);
SIM_hap_add_callback("MMU_Data_TLB_Replace", (obj_hap_func_t) dtlb_replace_callback, NULL);
// Add callbacks to abort transactions on exceptions in Rock.
//
SIM_hap_add_callback("Core_Exception", (obj_hap_func_t) rock_exception_start, (void *) NULL);
SIM_hap_add_callback("Core_Exception_Return", (obj_hap_func_t) rock_exception_done, (void *) NULL);
// Add instruction decoder to install handlers for Rock-specific behavior.
//
decoder_t* decoder = ATMTP_create_instruction_decoder();
SIM_register_arch_decoder(decoder, NULL, 0);
#endif
// CM 2/2003:
// Note: Please register other callbacks in the appropriate interface file,
// instead of here. This module should only register callbacks that
// are common to the "Driver" class (parent class to SimicsInterface
// and OpalInterface).
// If its only used by SimicsInterface, put it in that class.
}
void
init_local(void)
{
conf_class_t *conf_class;
/* Initialize and register the class "consistency_controller". */
memset(&class_data, 0, sizeof(class_data_t));
class_data.new_instance = consistency_controller_new_instance;
class_data.description =
"The consistency controller class implements a "
"memory hierarchy that communicates with the instruction tree "
"(in an out of order Simics) to enforce the architecturally "
"defined consistency model. This is done by stalling loads and stores "
"that would violate the consistency model but are otherwise ready to "
"issue to the memory system. The reason for not integrating the "
"consistency controller into the Simics core is to allow the user to "
"experiment with relaxed consistency model implementations. The user "
"can replace the consistency controller or modify the default one to "
"meet their needs (the source code is available in the distribution). "
"\n\n"
"The default consistency controller can be constrained through "
"attributes";
conf_class = SIM_register_class("consistency-controller", &class_data);
/* Initialize and register the timing-model interface */
consistency_controller_timing_interface = MM_ZALLOC(1, timing_model_interface_t);
consistency_controller_timing_interface->operate = consistency_controller_operate;
SIM_register_interface(conf_class, "timing-model", consistency_controller_timing_interface);
/* Initialize attributes */
SIM_register_attribute(conf_class, "timing_model",
get_timing_model_attribute, 0,
set_timing_model_attribute, 0, Sim_Attr_Optional,
"The next memory hierarchy object");
SIM_register_attribute(conf_class, "load-load",
get_load_load, 0,
set_load_load, 0, Sim_Attr_Optional,
"If set to non-zero load-load memory consistency will be enforced.");
SIM_register_attribute(conf_class, "load-store",
get_load_store, 0,
set_load_store, 0, Sim_Attr_Optional,
"If set to non-zero load-store memory consistency will be enforced.");
SIM_register_attribute(conf_class, "store-load",
get_store_load, 0,
set_store_load, 0, Sim_Attr_Optional,
"If set to non-zero store-load memory consistency will be enforced. This is the default");
SIM_register_attribute(conf_class, "store-store",
get_store_store, 0,
set_store_store, 0, Sim_Attr_Optional,
"If set to non-zero store-store memory consistency will be enforced. This is the default.");
SIM_register_attribute(conf_class, "prefetch",
get_prefetch, 0,
set_prefetch, 0, Sim_Attr_Optional,
"If set to non-zero prefetch memory transaction will be sent to the rest "
"of the memory hierarchy for transactions that breaks the memory consistency. "
"Zero is default.");
}
