void Jit::Comp_FPULS(MIPSOpcode op)
{
CONDITIONAL_DISABLE;
s32 offset = _IMM16;
int ft = _FT;
MIPSGPReg rs = _RS;
switch(op >> 26)
{
case 49: //FI(ft) = Memory::Read_U32(addr); break; //lwc1
{
gpr.Lock(rs);
fpr.SpillLock(ft);
fpr.MapReg(ft, false, true);
JitSafeMem safe(this, rs, offset);
OpArg src;
if (safe.PrepareRead(src, 4))
MOVSS(fpr.RX(ft), src);
if (safe.PrepareSlowRead(&Memory::Read_U32))
{
MOV(32, M(&ssLoadStoreTemp), R(EAX));
MOVSS(fpr.RX(ft), M(&ssLoadStoreTemp));
}
safe.Finish();
gpr.UnlockAll();
fpr.ReleaseSpillLocks();
}
break;
case 57: //Memory::Write_U32(FI(ft), addr); break; //swc1
{
gpr.Lock(rs);
fpr.SpillLock(ft);
fpr.MapReg(ft, true, false);
JitSafeMem safe(this, rs, offset);
OpArg dest;
if (safe.PrepareWrite(dest, 4))
MOVSS(dest, fpr.RX(ft));
if (safe.PrepareSlowWrite())
{
MOVSS(M(&ssLoadStoreTemp), fpr.RX(ft));
safe.DoSlowWrite(&Memory::Write_U32, M(&ssLoadStoreTemp));
}
safe.Finish();
gpr.UnlockAll();
fpr.ReleaseSpillLocks();
}
break;
default:
_dbg_assert_msg_(CPU,0,"Trying to interpret FPULS instruction that can't be interpreted");
break;
}
}
void Jit::Comp_FPULS(u32 op)
{
CONDITIONAL_DISABLE;
if (!g_Config.bFastMemory) {
DISABLE;
}
s32 offset = (s16)(op&0xFFFF);
int ft = ((op>>16)&0x1f);
int rs = _RS;
// u32 addr = R(rs) + offset;
switch(op >> 26)
{
case 49: //FI(ft) = Memory::Read_U32(addr); break; //lwc1
gpr.Lock(rs);
fpr.Lock(ft);
fpr.BindToRegister(ft, false, true);
#ifdef _M_IX86
MOV(32, R(EAX), gpr.R(rs));
AND(32, R(EAX), Imm32(Memory::MEMVIEW32_MASK));
MOVSS(fpr.RX(ft), MDisp(EAX, (u32)Memory::base + offset));
#else
MOV(32, R(EAX), gpr.R(rs));
MOVSS(fpr.RX(ft), MComplex(RBX, RAX, SCALE_1, offset));
#endif
gpr.UnlockAll();
fpr.UnlockAll();
break;
case 57: //Memory::Write_U32(FI(ft), addr); break; //swc1
gpr.Lock(rs);
fpr.Lock(ft);
fpr.BindToRegister(ft, true, false);
#ifdef _M_IX86
MOV(32, R(EAX), gpr.R(rs));
AND(32, R(EAX), Imm32(Memory::MEMVIEW32_MASK));
MOVSS(MDisp(EAX, (u32)Memory::base + offset), fpr.RX(ft));
#else
MOV(32, R(EAX), gpr.R(rs));
MOVSS(MComplex(RBX, RAX, SCALE_1, offset), fpr.RX(ft));
#endif
gpr.UnlockAll();
fpr.UnlockAll();
break;
default:
_dbg_assert_msg_(CPU,0,"Trying to interpret FPULS instruction that can't be interpreted");
break;
}
}
void Jit::CompFPComp(int lhs, int rhs, u8 compare, bool allowNaN)
{
MOVSS(XMM0, fpr.R(lhs));
CMPSS(XMM0, fpr.R(rhs), compare);
MOVSS(M(¤tMIPS->fpcond), XMM0);
// This means that NaN also means true, e.g. !<> or !>, etc.
if (allowNaN)
{
MOVSS(XMM0, fpr.R(lhs));
CMPUNORDSS(XMM0, fpr.R(rhs));
MOVSS(M(&ssCompareTemp), XMM0);
MOV(32, R(EAX), M(&ssCompareTemp));
OR(32, M(¤tMIPS->fpcond), R(EAX));
}
}
void Jit::CompFPComp(int lhs, int rhs, u8 compare, bool allowNaN)
{
gpr.MapReg(MIPS_REG_FPCOND, false, true);
MOVSS(XMM0, fpr.R(lhs));
CMPSS(XMM0, fpr.R(rhs), compare);
MOVD_xmm(gpr.R(MIPS_REG_FPCOND), XMM0);
// This means that NaN also means true, e.g. !<> or !>, etc.
if (allowNaN)
{
MOVSS(XMM0, fpr.R(lhs));
CMPUNORDSS(XMM0, fpr.R(rhs));
MOVD_xmm(R(EAX), XMM0);
OR(32, gpr.R(MIPS_REG_FPCOND), R(EAX));
}
}
bool SamplerJitCache::Jit_Decode4444() {
MOVD_xmm(fpScratchReg1, R(resultReg));
PUNPCKLBW(fpScratchReg1, R(fpScratchReg1));
if (RipAccessible(color4444mask)) {
PAND(fpScratchReg1, M(color4444mask)); // rip accessible
} else {
Crash();
}
MOVSS(fpScratchReg2, R(fpScratchReg1));
MOVSS(fpScratchReg3, R(fpScratchReg1));
PSRLW(fpScratchReg2, 4);
PSLLW(fpScratchReg3, 4);
POR(fpScratchReg1, R(fpScratchReg2));
POR(fpScratchReg1, R(fpScratchReg3));
MOVD_xmm(R(resultReg), fpScratchReg1);
return true;
}
void Jit::Comp_mxc1(u32 op)
{
CONDITIONAL_DISABLE;
int fs = _FS;
int rt = _RT;
switch((op >> 21) & 0x1f)
{
case 0: // R(rt) = FI(fs); break; //mfc1
// Cross move! slightly tricky
fpr.StoreFromRegister(fs);
gpr.Lock(rt);
gpr.BindToRegister(rt, false, true);
MOV(32, gpr.R(rt), fpr.R(fs));
gpr.UnlockAll();
return;
case 2: // R(rt) = currentMIPS->ReadFCR(fs); break; //cfc1
Comp_Generic(op);
return;
case 4: //FI(fs) = R(rt); break; //mtc1
// Cross move! slightly tricky
gpr.StoreFromRegister(rt);
fpr.Lock(fs);
fpr.BindToRegister(fs, false, true);
MOVSS(fpr.RX(fs), gpr.R(rt));
fpr.UnlockAll();
return;
case 6: //currentMIPS->WriteFCR(fs, R(rt)); break; //ctc1
Comp_Generic(op);
return;
}
}
void Jit::Comp_FPU2op(MIPSOpcode op) {
CONDITIONAL_DISABLE;
int fs = _FS;
int fd = _FD;
switch (op & 0x3f)
{
case 5: //F(fd) = fabsf(F(fs)); break; //abs
fpr.SpillLock(fd, fs);
fpr.MapReg(fd, fd == fs, true);
MOVSS(fpr.RX(fd), fpr.R(fs));
PAND(fpr.RX(fd), M(ssNoSignMask));
break;
case 6: //F(fd) = F(fs); break; //mov
if (fd != fs) {
fpr.SpillLock(fd, fs);
fpr.MapReg(fd, fd == fs, true);
MOVSS(fpr.RX(fd), fpr.R(fs));
}
break;
case 7: //F(fd) = -F(fs); break; //neg
fpr.SpillLock(fd, fs);
fpr.MapReg(fd, fd == fs, true);
MOVSS(fpr.RX(fd), fpr.R(fs));
PXOR(fpr.RX(fd), M(ssSignBits2));
break;
case 4: //F(fd) = sqrtf(F(fs)); break; //sqrt
fpr.SpillLock(fd, fs); // this probably works, just badly tested
fpr.MapReg(fd, fd == fs, true);
SQRTSS(fpr.RX(fd), fpr.R(fs));
break;
case 13: //FsI(fd) = F(fs)>=0 ? (int)floorf(F(fs)) : (int)ceilf(F(fs)); break;//trunc.w.s
{
fpr.SpillLock(fs, fd);
fpr.StoreFromRegister(fd);
CVTTSS2SI(EAX, fpr.R(fs));
// Did we get an indefinite integer value?
CMP(32, R(EAX), Imm32(0x80000000));
FixupBranch skip = J_CC(CC_NE);
MOVSS(XMM0, fpr.R(fs));
XORPS(XMM1, R(XMM1));
CMPSS(XMM0, R(XMM1), CMP_LT);
// At this point, -inf = 0xffffffff, inf/nan = 0x00000000.
// We want -inf to be 0x80000000 inf/nan to be 0x7fffffff, so we flip those bits.
MOVD_xmm(R(EAX), XMM0);
XOR(32, R(EAX), Imm32(0x7fffffff));
SetJumpTarget(skip);
MOV(32, fpr.R(fd), R(EAX));
}
break;
case 32: //F(fd) = (float)FsI(fs); break; //cvt.s.w
// Store to memory so we can read it as an integer value.
fpr.StoreFromRegister(fs);
CVTSI2SS(XMM0, fpr.R(fs));
MOVSS(fpr.R(fd), XMM0);
break;
case 12: //FsI(fd) = (int)floorf(F(fs)+0.5f); break; //round.w.s
case 14: //FsI(fd) = (int)ceilf (F(fs)); break; //ceil.w.s
case 15: //FsI(fd) = (int)floorf(F(fs)); break; //floor.w.s
case 36: //FsI(fd) = (int) F(fs); break; //cvt.w.s
default:
DISABLE;
return;
}
fpr.ReleaseSpillLocks();
}
void Jit::Comp_FPU2op(MIPSOpcode op) {
CONDITIONAL_DISABLE(FPU);
int fs = _FS;
int fd = _FD;
auto execRounding = [&](void (XEmitter::*conv)(X64Reg, OpArg), int setMXCSR) {
fpr.SpillLock(fd, fs);
fpr.MapReg(fd, fs == fd, true);
// Small optimization: 0 is our default mode anyway.
if (setMXCSR == 0 && !js.hasSetRounding) {
setMXCSR = -1;
}
if (setMXCSR != -1) {
STMXCSR(MIPSSTATE_VAR(mxcsrTemp));
MOV(32, R(TEMPREG), MIPSSTATE_VAR(mxcsrTemp));
AND(32, R(TEMPREG), Imm32(~(3 << 13)));
OR(32, R(TEMPREG), Imm32(setMXCSR << 13));
MOV(32, MIPSSTATE_VAR(temp), R(TEMPREG));
LDMXCSR(MIPSSTATE_VAR(temp));
}
(this->*conv)(TEMPREG, fpr.R(fs));
// Did we get an indefinite integer value?
CMP(32, R(TEMPREG), Imm32(0x80000000));
FixupBranch skip = J_CC(CC_NE);
if (fd != fs) {
CopyFPReg(fpr.RX(fd), fpr.R(fs));
}
XORPS(XMM1, R(XMM1));
CMPSS(fpr.RX(fd), R(XMM1), CMP_LT);
// At this point, -inf = 0xffffffff, inf/nan = 0x00000000.
// We want -inf to be 0x80000000 inf/nan to be 0x7fffffff, so we flip those bits.
MOVD_xmm(R(TEMPREG), fpr.RX(fd));
XOR(32, R(TEMPREG), Imm32(0x7fffffff));
SetJumpTarget(skip);
MOVD_xmm(fpr.RX(fd), R(TEMPREG));
if (setMXCSR != -1) {
LDMXCSR(MIPSSTATE_VAR(mxcsrTemp));
}
};
switch (op & 0x3f) {
case 5: //F(fd) = fabsf(F(fs)); break; //abs
fpr.SpillLock(fd, fs);
fpr.MapReg(fd, fd == fs, true);
MOV(PTRBITS, R(TEMPREG), ImmPtr(&ssNoSignMask[0]));
if (fd != fs && fpr.IsMapped(fs)) {
MOVAPS(fpr.RX(fd), MatR(TEMPREG));
ANDPS(fpr.RX(fd), fpr.R(fs));
} else {
if (fd != fs) {
MOVSS(fpr.RX(fd), fpr.R(fs));
}
ANDPS(fpr.RX(fd), MatR(TEMPREG));
}
break;
case 6: //F(fd) = F(fs); break; //mov
if (fd != fs) {
fpr.SpillLock(fd, fs);
fpr.MapReg(fd, fd == fs, true);
CopyFPReg(fpr.RX(fd), fpr.R(fs));
}
break;
case 7: //F(fd) = -F(fs); break; //neg
fpr.SpillLock(fd, fs);
fpr.MapReg(fd, fd == fs, true);
MOV(PTRBITS, R(TEMPREG), ImmPtr(&ssSignBits2[0]));
if (fd != fs && fpr.IsMapped(fs)) {
MOVAPS(fpr.RX(fd), MatR(TEMPREG));
XORPS(fpr.RX(fd), fpr.R(fs));
} else {
if (fd != fs) {
MOVSS(fpr.RX(fd), fpr.R(fs));
}
XORPS(fpr.RX(fd), MatR(TEMPREG));
}
break;
case 4: //F(fd) = sqrtf(F(fs)); break; //sqrt
fpr.SpillLock(fd, fs);
fpr.MapReg(fd, fd == fs, true);
SQRTSS(fpr.RX(fd), fpr.R(fs));
break;
case 13: //FsI(fd) = F(fs)>=0 ? (int)floorf(F(fs)) : (int)ceilf(F(fs)); break; //trunc.w.s
execRounding(&XEmitter::CVTTSS2SI, -1);
break;
case 32: //F(fd) = (float)FsI(fs); break; //cvt.s.w
fpr.SpillLock(fd, fs);
fpr.MapReg(fd, fs == fd, true);
if (fpr.IsMapped(fs)) {
CVTDQ2PS(fpr.RX(fd), fpr.R(fs));
} else {
// If fs was fd, we'd be in the case above since we mapped fd.
MOVSS(fpr.RX(fd), fpr.R(fs));
CVTDQ2PS(fpr.RX(fd), fpr.R(fd));
}
break;
case 36: //FsI(fd) = (int) F(fs); break; //cvt.w.s
// Uses the current rounding mode.
execRounding(&XEmitter::CVTSS2SI, -1);
break;
case 12: //FsI(fd) = (int)floorf(F(fs)+0.5f); break; //round.w.s
execRounding(&XEmitter::CVTSS2SI, 0);
break;
case 14: //FsI(fd) = (int)ceilf (F(fs)); break; //ceil.w.s
execRounding(&XEmitter::CVTSS2SI, 2);
break;
case 15: //FsI(fd) = (int)floorf(F(fs)); break; //floor.w.s
execRounding(&XEmitter::CVTSS2SI, 1);
break;
default:
DISABLE;
return;
}
fpr.ReleaseSpillLocks();
}
void Jit::Comp_FPU2op(u32 op)
{
CONDITIONAL_DISABLE;
int fs = _FS;
int fd = _FD;
switch (op & 0x3f)
{
case 5: //F(fd) = fabsf(F(fs)); break; //abs
fpr.Lock(fd, fs);
fpr.BindToRegister(fd, fd == fs, true);
MOVSS(fpr.RX(fd), fpr.R(fs));
PAND(fpr.RX(fd), M((void *)ssNoSignMask));
fpr.UnlockAll();
break;
case 6: //F(fd) = F(fs); break; //mov
if (fd != fs) {
fpr.Lock(fd, fs);
fpr.BindToRegister(fd, fd == fs, true);
MOVSS(fpr.RX(fd), fpr.R(fs));
fpr.UnlockAll();
}
break;
case 7: //F(fd) = -F(fs); break; //neg
fpr.Lock(fd, fs);
fpr.BindToRegister(fd, fd == fs, true);
MOVSS(fpr.RX(fd), fpr.R(fs));
PXOR(fpr.RX(fd), M((void *)ssSignBits2));
fpr.UnlockAll();
break;
case 12: //FsI(fd) = (int)floorf(F(fs)+0.5f); break; //round.w.s
case 4: //F(fd) = sqrtf(F(fs)); break; //sqrt
/* fpr.Lock(fd, fs); // this probably works, just badly tested
fpr.BindToRegister(fd, fd == fs, true);
SQRTSS(fpr.RX(fd), fpr.R(fs));
fpr.UnlockAll();
break;*/
Comp_Generic(op);
return;
case 13: //FsI(fd) = F(fs)>=0 ? (int)floorf(F(fs)) : (int)ceilf(F(fs)); break;//trunc.w.s
fpr.Lock(fs, fd);
fpr.StoreFromRegister(fd);
CVTTSS2SI(EAX, fpr.R(fs));
MOV(32, fpr.R(fd), R(EAX));
fpr.UnlockAll();
break;
case 14: //FsI(fd) = (int)ceilf (F(fs)); break; //ceil.w.s
case 15: //FsI(fd) = (int)floorf(F(fs)); break; //floor.w.s
case 32: //F(fd) = (float)FsI(fs); break; //cvt.s.w
case 36: //FsI(fd) = (int) F(fs); break; //cvt.w.s
default:
Comp_Generic(op);
return;
}
}
