static __init void ja_pci1_init(void) { uint32_t mem0_base, mem0_size; uint32_t io_base, io_size; io_base = MV_READ(MV64340_PCI_1_IO_BASE_ADDR) << 16; io_size = (MV_READ(MV64340_PCI_1_IO_SIZE) + 1) << 16; mem0_base = MV_READ(MV64340_PCI_1_MEMORY0_BASE_ADDR) << 16; mem0_size = (MV_READ(MV64340_PCI_1_MEMORY0_SIZE) + 1) << 16; /* * Here we assume the I/O window of second bus to be contiguous with * the first. A gap is no problem but would waste address space for * remapping the port space. */ mv_pci_io_mem1_resource.start = mv_io_size; mv_pci_io_mem1_resource.end = mv_io_size + io_size - 1; mv_pci_mem1_resource.start = mem0_base; mv_pci_mem1_resource.end = mem0_base + mem0_size - 1; mv_bus1_controller.pcic.mem_offset = mem0_base; mv_bus1_controller.pcic.io_offset = 0; ioport_resource.end = io_base + io_size -mv_io_base - 1; register_pci_controller(&mv_bus1_controller.pcic); mv_io_size = io_base + io_size - mv_io_base; }
int mveth_init(struct mv64340_private *mp) { int i; mp->p_rx_desc_area = rx_ring; mp->p_tx_desc_area = tx_ring; rx_stopq(mp->port_num); tx_stopq(mp->port_num); /* MotLoad has cache snooping disabled on the ENET2MEM windows. * Some comments in (linux) indicate that there are errata * which cause problems which is a real bummer. * We try it anyways... */ { unsigned long disbl, bar; disbl = MV_READ(MV64340_ETH_BASE_ADDR_ENABLE_REG); /* disable all 6 windows */ MV_WRITE(MV64340_ETH_BASE_ADDR_ENABLE_REG, 0x3f); /* set WB snooping */ for ( i=0; i<6*8; i+=8 ) { if ( (bar = MV_READ(MV64340_ETH_BAR_0 + i)) && MV_READ(MV64340_ETH_SIZE_REG_0 + i) ) { MV_WRITE(MV64340_ETH_BAR_0 + i, bar | MV64360_ENET2MEM_SNOOP_WB); /* read back to flush fifo [linux comment] */ (void)MV_READ(MV64340_ETH_BAR_0 + i); } } /* restore/re-enable */ MV_WRITE(MV64340_ETH_BASE_ADDR_ENABLE_REG, disbl); } eth_port_init(mp); sleep(1); mveth_init_tx_desc_ring(mp); mveth_init_rx_desc_ring(mp); #if 0 for ( i = 0; i<MV64340_RX_QUEUE_SIZE; i++ ) { p0.byte_cnt = sizeof(rx_buf[0]); p0.buf_ptr = (dma_addr_t)rx_buf[i]; p0.return_info = (void*)i; /* other fields are not used by ll driver */ assert ( ETH_OK == eth_rx_return_buff(mp,&p0) ); } memset(&p0, 0, sizeof(p0)); #endif return eth_port_start(mp); }
/* unmask an interrupt -- 1 is enable, 0 is disable */ static inline void unmask_mv64340_irq(unsigned int irq) { uint32_t value; if (irq < (irq_base + 32)) { value = MV_READ(MV64340_INTERRUPT0_MASK_0_LOW); value |= 1 << (irq - irq_base); MV_WRITE(MV64340_INTERRUPT0_MASK_0_LOW, value); } else { value = MV_READ(MV64340_INTERRUPT0_MASK_0_HIGH); value |= 1 << (irq - (irq_base - 32)); MV_WRITE(MV64340_INTERRUPT0_MASK_0_HIGH, value); } }
static int Enable_SRAM(void) { u32 ALong; if (mv643xx_reg_base == NULL) mv643xx_reg_base = ioremap(PEGASOS2_MARVELL_REGBASE, PEGASOS2_MARVELL_REGSIZE); if (mv643xx_reg_base == NULL) return -ENOMEM; #ifdef BE_VERBOSE printk("Pegasos II/Marvell MV64361: register remapped from %p to %p\n", (void *)PEGASOS2_MARVELL_REGBASE, (void *)mv643xx_reg_base); #endif MV_WRITE(MV64340_SRAM_CONFIG, 0); MV_WRITE(MV64340_INTEGRATED_SRAM_BASE_ADDR, PEGASOS2_SRAM_BASE >> 16); MV_READ(MV64340_BASE_ADDR_ENABLE, ALong); ALong &= ~(1 << 19); MV_WRITE(MV64340_BASE_ADDR_ENABLE, ALong); ALong = 0x02; ALong |= PEGASOS2_SRAM_BASE & 0xffff0000; MV_WRITE(MV643XX_ETH_BAR_4, ALong); MV_WRITE(MV643XX_ETH_SIZE_REG_4, (PEGASOS2_SRAM_SIZE-1) & 0xffff0000); MV_READ(MV643XX_ETH_BASE_ADDR_ENABLE_REG, ALong); ALong &= ~(1 << 4); MV_WRITE(MV643XX_ETH_BASE_ADDR_ENABLE_REG, ALong); #ifdef BE_VERBOSE printk("Pegasos II/Marvell MV64361: register unmapped\n"); printk("Pegasos II/Marvell MV64361: SRAM at %p, size=%x\n", (void*) PEGASOS2_SRAM_BASE, PEGASOS2_SRAM_SIZE); #endif iounmap(mv643xx_reg_base); mv643xx_reg_base = NULL; return 1; }
/* * Interrupt handler for interrupts coming from the Marvell chip. * It could be built in ethernet ports etc... */ void ll_mv64340_irq(struct pt_regs *regs) { unsigned int irq_src_low, irq_src_high; unsigned int irq_mask_low, irq_mask_high; /* read the interrupt status registers */ irq_mask_low = MV_READ(MV64340_INTERRUPT0_MASK_0_LOW); irq_mask_high = MV_READ(MV64340_INTERRUPT0_MASK_0_HIGH); irq_src_low = MV_READ(MV64340_MAIN_INTERRUPT_CAUSE_LOW); irq_src_high = MV_READ(MV64340_MAIN_INTERRUPT_CAUSE_HIGH); /* mask for just the interrupts we want */ irq_src_low &= irq_mask_low; irq_src_high &= irq_mask_high; if (irq_src_low) do_IRQ(ls1bit32(irq_src_low) + irq_base, regs); else do_IRQ(ls1bit32(irq_src_high) + irq_base + 32, regs); }
static int config_access(unsigned char access_type, struct pci_bus *bus, unsigned int devfn, unsigned char where, u32 * data) { unsigned int slot = PCI_SLOT(devfn); u8 func = PCI_FUNC(devfn); uint32_t address_reg, data_reg; unsigned int address; address_reg = RALINK_PCI_CONFIG_ADDR; data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG; /* Setup address */ #if defined(CONFIG_RALINK_RT3883) address = (bus->number << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000; #elif defined(CONFIG_RALINK_RT6855) address = (bus->number << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000; #elif defined(CONFIG_RALINK_MT7620) address = (bus->number << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000; #else address = (bus->number << 16) | (slot << 11) | (func << 8) | (where& 0xfc) | 0x80000000; #endif /* start the configuration cycle */ MV_WRITE(address_reg, address); switch(access_type) { case PCI_ACCESS_WRITE_1: MV_WRITE_8(data_reg+(where&0x3), *data); break; case PCI_ACCESS_WRITE_2: MV_WRITE_16(data_reg+(where&0x3), *data); break; case PCI_ACCESS_WRITE_4: MV_WRITE(data_reg, *data); break; case PCI_ACCESS_READ_1: MV_READ_8( data_reg+(where&0x3), data); break; case PCI_ACCESS_READ_2: MV_READ_16(data_reg+(where&0x3), data); break; case PCI_ACCESS_READ_4: MV_READ(data_reg, data); break; default: printk("no specify access type\n"); break; } return 0; }
static void ja_pci0_init(void) { uint32_t mem0_base, mem0_size; uint32_t io_base, io_size; io_base = MV_READ(MV64340_PCI_0_IO_BASE_ADDR) << 16; io_size = (MV_READ(MV64340_PCI_0_IO_SIZE) + 1) << 16; mem0_base = MV_READ(MV64340_PCI_0_MEMORY0_BASE_ADDR) << 16; mem0_size = (MV_READ(MV64340_PCI_0_MEMORY0_SIZE) + 1) << 16; mv_pci_io_mem0_resource.start = 0; mv_pci_io_mem0_resource.end = io_size - 1; mv_pci_mem0_resource.start = mem0_base; mv_pci_mem0_resource.end = mem0_base + mem0_size - 1; mv_bus0_controller.pcic.mem_offset = mem0_base; mv_bus0_controller.pcic.io_offset = 0; ioport_resource.end = io_size - 1; register_pci_controller(&mv_bus0_controller.pcic); mv_io_base = io_base; mv_io_size = io_size; }
/* * Flush the Address Translation Unit (ATU). */ static void mvphy_flushatu(struct mii_softc *sc) { uint16_t status; int i; /* wait for any previous request to complete */ /* XXX if busy defer to tick */ /* XXX timeout */ for (i = 0; i < 1000; i++) { status = MV_READ(sc, MII_MV_SWITCH_GLOBAL_ADDR, MV_ATU_OPERATION); if (MV_ATU_IS_BUSY(status)) break; } if (i != 1000) { MV_WRITE(sc, MII_MV_SWITCH_GLOBAL_ADDR, MV_ATU_OPERATION, MV_ATU_OP_FLUSH_ALL | MV_ATU_BUSY); } /*else aprint_error_dev(sc->mii_dev, "timeout waiting for ATU flush\n");*/ }
void __inline__ read_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long *val) { unsigned long address_reg, data_reg, address; address_reg = RALINK_PCI_CONFIG_ADDR; data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG; /* set addr */ #if defined(CONFIG_RALINK_RT3883) address = (bus << 16) | (dev << 11) | (func << 8) | (reg& 0xfc) | 0x80000000 ; #elif defined(CONFIG_RALINK_RT6855) address = (bus << 16) | (dev << 11) | (func << 8) | (reg& 0xfc) | 0x80000000 ; #elif defined(CONFIG_RALINK_MT7620) address = (bus << 16) | (dev << 11) | (func << 8) | (reg& 0xfc) | 0x80000000 ; #else address = (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000 ; #endif /* start the configuration cycle */ MV_WRITE(address_reg, address); /* read the data */ MV_READ(data_reg, val); return; }
void __init plat_setup(void) { unsigned int tmpword; board_time_init = momenco_time_init; _machine_restart = momenco_jaguar_restart; _machine_halt = momenco_jaguar_halt; _machine_power_off = momenco_jaguar_power_off; /* * initrd_start = (ulong)jaguar_initrd_start; * initrd_end = (ulong)jaguar_initrd_start + (ulong)jaguar_initrd_size; * initrd_below_start_ok = 1; */ wire_stupidity_into_tlb(); /* * shut down ethernet ports, just to be sure our memory doesn't get * corrupted by random ethernet traffic. */ MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8); MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8); MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(2), 0xff << 8); MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8); MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8); MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(2), 0xff << 8); while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff); while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff); while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(2)) & 0xff); while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff); while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff); while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(2)) & 0xff); MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0), MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1); MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1), MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1); MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(2), MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(2)) & ~1); /* Turn off the Bit-Error LED */ JAGUAR_FPGA_WRITE(0x80, CLR); tmpword = JAGUAR_FPGA_READ(BOARDREV); if (tmpword < 26) printk("Momentum Jaguar-ATX: Board Assembly Rev. %c\n", 'A'+tmpword); else printk("Momentum Jaguar-ATX: Board Assembly Revision #0x%x\n", tmpword); tmpword = JAGUAR_FPGA_READ(FPGA_REV); printk("FPGA Rev: %d.%d\n", tmpword>>4, tmpword&15); tmpword = JAGUAR_FPGA_READ(RESET_STATUS); printk("Reset reason: 0x%x\n", tmpword); switch (tmpword) { case 0x1: printk(" - Power-up reset\n"); break; case 0x2: printk(" - Push-button reset\n"); break; case 0x8: printk(" - Watchdog reset\n"); break; case 0x10: printk(" - JTAG reset\n"); break; default: printk(" - Unknown reset cause\n"); } reset_reason = tmpword; JAGUAR_FPGA_WRITE(0xff, RESET_STATUS); tmpword = JAGUAR_FPGA_READ(BOARD_STATUS); printk("Board Status register: 0x%02x\n", tmpword); printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent"); printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent"); /* 256MiB of RM9000x2 DDR */ // add_memory_region(0x0, 0x100<<20, BOOT_MEM_RAM); /* 128MiB of MV-64340 DDR */ // add_memory_region(0x100<<20, 0x80<<20, BOOT_MEM_RAM); /* XXX Memory configuration should be picked up from PMON2k */ #ifdef CONFIG_JAGUAR_DMALOW printk("Jaguar ATX DMA-low mode set\n"); add_memory_region(0x00000000, 0x08000000, BOOT_MEM_RAM); add_memory_region(0x08000000, 0x10000000, BOOT_MEM_RAM); #else /* 128MiB of MV-64340 DDR RAM */ printk("Jaguar ATX DMA-low mode is not set\n"); add_memory_region(0x100<<20, 0x80<<20, BOOT_MEM_RAM); #endif #ifdef GEMDEBUG_TRACEBUFFER { unsigned int tbControl; tbControl = 0 << 26 | /* post trigger delay 0 */ 0x2 << 16 | /* sequential trace mode */ // 0x0 << 16 | /* non-sequential trace mode */ // 0xf << 4 | /* watchpoints disabled */ 2 << 2 | /* armed */ 2 ; /* interrupt disabled */ printk ("setting tbControl = %08lx\n", tbControl); write_32bit_cp0_set1_register($22, tbControl); __asm__ __volatile__(".set noreorder\n\t" \ "nop; nop; nop; nop; nop; nop;\n\t" \ "nop; nop; nop; nop; nop; nop;\n\t" \ ".set reorder\n\t"); } #endif }
void __init plat_setup(void) { unsigned int tmpword; board_time_init = momenco_time_init; _machine_restart = momenco_ocelot_restart; _machine_halt = momenco_ocelot_halt; pm_power_off = momenco_ocelot_power_off; /* Wired TLB entries */ setup_wired_tlb_entries(); /* shut down ethernet ports, just to be sure our memory doesn't get * corrupted by random ethernet traffic. */ MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8); MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8); MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8); MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8); do {} while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff); do {} while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff); do {} while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff); do {} while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff); MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0), MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1); MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1), MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1); /* Turn off the Bit-Error LED */ OCELOT_FPGA_WRITE(0x80, CLR); tmpword = OCELOT_FPGA_READ(BOARDREV); if (tmpword < 26) printk("Momenco Ocelot-3: Board Assembly Rev. %c\n", 'A'+tmpword); else printk("Momenco Ocelot-3: Board Assembly Revision #0x%x\n", tmpword); tmpword = OCELOT_FPGA_READ(FPGA_REV); printk("FPGA Rev: %d.%d\n", tmpword>>4, tmpword&15); tmpword = OCELOT_FPGA_READ(RESET_STATUS); printk("Reset reason: 0x%x\n", tmpword); switch (tmpword) { case 0x1: printk(" - Power-up reset\n"); break; case 0x2: printk(" - Push-button reset\n"); break; case 0x4: printk(" - cPCI bus reset\n"); break; case 0x8: printk(" - Watchdog reset\n"); break; case 0x10: printk(" - Software reset\n"); break; default: printk(" - Unknown reset cause\n"); } reset_reason = tmpword; OCELOT_FPGA_WRITE(0xff, RESET_STATUS); tmpword = OCELOT_FPGA_READ(CPCI_ID); printk("cPCI ID register: 0x%02x\n", tmpword); printk(" - Slot number: %d\n", tmpword & 0x1f); printk(" - PCI bus present: %s\n", tmpword & 0x40 ? "yes" : "no"); printk(" - System Slot: %s\n", tmpword & 0x20 ? "yes" : "no"); tmpword = OCELOT_FPGA_READ(BOARD_STATUS); printk("Board Status register: 0x%02x\n", tmpword); printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent"); printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent"); printk(" - L3 cache size: %d MB\n", (1<<((tmpword&12) >> 2))&~1); /* Support for 128 MB memory */ add_memory_region(0x0, 0x08000000, BOOT_MEM_RAM); }
void __init plat_setup(void) { unsigned int tmpword; board_time_init = momenco_time_init; _machine_restart = momenco_ocelot_restart; _machine_halt = momenco_ocelot_halt; _machine_power_off = momenco_ocelot_power_off; /* * initrd_start = (ulong)ocelot_initrd_start; * initrd_end = (ulong)ocelot_initrd_start + (ulong)ocelot_initrd_size; * initrd_below_start_ok = 1; */ /* do handoff reconfiguration */ PMON_v2_setup(); /* shut down ethernet ports, just to be sure our memory doesn't get * corrupted by random ethernet traffic. */ MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8); MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8); MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8); MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8); do {} while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff); do {} while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff); do {} while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff); do {} while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff); MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0), MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1); MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1), MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1); /* Turn off the Bit-Error LED */ OCELOT_FPGA_WRITE(0x80, CLR); tmpword = OCELOT_FPGA_READ(BOARDREV); #ifdef CONFIG_CPU_SR71000 if (tmpword < 26) printk("Momenco Ocelot-CS: Board Assembly Rev. %c\n", 'A'+tmpword); else printk("Momenco Ocelot-CS: Board Assembly Revision #0x%x\n", tmpword); #else if (tmpword < 26) printk("Momenco Ocelot-C: Board Assembly Rev. %c\n", 'A'+tmpword); else printk("Momenco Ocelot-C: Board Assembly Revision #0x%x\n", tmpword); #endif tmpword = OCELOT_FPGA_READ(FPGA_REV); printk("FPGA Rev: %d.%d\n", tmpword>>4, tmpword&15); tmpword = OCELOT_FPGA_READ(RESET_STATUS); printk("Reset reason: 0x%x\n", tmpword); switch (tmpword) { case 0x1: printk(" - Power-up reset\n"); break; case 0x2: printk(" - Push-button reset\n"); break; case 0x4: printk(" - cPCI bus reset\n"); break; case 0x8: printk(" - Watchdog reset\n"); break; case 0x10: printk(" - Software reset\n"); break; default: printk(" - Unknown reset cause\n"); } reset_reason = tmpword; OCELOT_FPGA_WRITE(0xff, RESET_STATUS); tmpword = OCELOT_FPGA_READ(CPCI_ID); printk("cPCI ID register: 0x%02x\n", tmpword); printk(" - Slot number: %d\n", tmpword & 0x1f); printk(" - PCI bus present: %s\n", tmpword & 0x40 ? "yes" : "no"); printk(" - System Slot: %s\n", tmpword & 0x20 ? "yes" : "no"); tmpword = OCELOT_FPGA_READ(BOARD_STATUS); printk("Board Status register: 0x%02x\n", tmpword); printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent"); printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent"); printk(" - L3 Cache size: %d MiB\n", (1<<((tmpword&12) >> 2))&~1); printk(" - SDRAM size: %d MiB\n", 1<<(6+(tmpword&3))); switch(tmpword &3) { case 3: /* 512MiB */ add_memory_region(0x0, 0x200<<20, BOOT_MEM_RAM); break; case 2: /* 256MiB */ add_memory_region(0x0, 0x100<<20, BOOT_MEM_RAM); break; case 1: /* 128MiB */ add_memory_region(0x0, 0x80<<20, BOOT_MEM_RAM); break; case 0: /* 1GiB -- needs CONFIG_HIGHMEM */ add_memory_region(0x0, 0x400<<20, BOOT_MEM_RAM); break; } }