void mxr_reg_graph_buffer(struct mxr_device *mdev, int idx, dma_addr_t addr) { u32 val = addr ? ~0 : 0; unsigned long flags; spin_lock_irqsave(&mdev->reg_slock, flags); mxr_vsync_set_update(mdev, MXR_DISABLE); if (idx == 0) { mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_GRP0_ENABLE); mxr_write(mdev, MXR_GRAPHIC_BASE(0), addr); } else if (idx == 1) { mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_GRP1_ENABLE); mxr_write(mdev, MXR_GRAPHIC_BASE(1), addr); } else if (idx == 2) { mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_MX1_GRP0_ENABLE); mxr_write(mdev, MXR1_GRAPHIC_BASE(0), addr); } else if (idx == 3) { mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_MX1_GRP1_ENABLE); mxr_write(mdev, MXR1_GRAPHIC_BASE(1), addr); } mxr_vsync_set_update(mdev, MXR_ENABLE); spin_unlock_irqrestore(&mdev->reg_slock, flags); }
void mxr_reg_graph_buffer(struct mxr_device *mdev, int idx, dma_addr_t addr) { u32 val = addr ? ~0 : 0; if (idx == 0) { mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_GRP0_ENABLE); mxr_write(mdev, MXR_GRAPHIC_BASE(0), addr); } else if (idx == 1) { mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_GRP1_ENABLE); mxr_write(mdev, MXR_GRAPHIC_BASE(1), addr); } else if (idx == 2) { mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_MX1_GRP0_ENABLE); mxr_write(mdev, MXR1_GRAPHIC_BASE(0), addr); } else if (idx == 3) { mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_MX1_GRP1_ENABLE); mxr_write(mdev, MXR1_GRAPHIC_BASE(1), addr); } }