void mxr_reg_graph_chromakey_value(struct mxr_device *mdev, int idx,u32 en) { unsigned long flags; spin_lock_irqsave(&mdev->reg_slock, flags); mxr_write(mdev,MXR_GRAPHIC_BLANK(idx),en); spin_unlock_irqrestore(&mdev->reg_slock, flags); }
void mxr_reg_colorkey_val(struct mxr_device *mdev, int sub_mxr, int num, u32 v) { unsigned long flags; spin_lock_irqsave(&mdev->reg_slock, flags); mxr_vsync_set_update(mdev, MXR_DISABLE); if (sub_mxr == MXR_SUB_MIXER0 && num == MXR_LAYER_GRP0) mxr_write(mdev, MXR_GRAPHIC_BLANK(0), v); else if (sub_mxr == MXR_SUB_MIXER0 && num == MXR_LAYER_GRP1) mxr_write(mdev, MXR_GRAPHIC_BLANK(1), v); #if defined(CONFIG_ARCH_EXYNOS5) else if (sub_mxr == MXR_SUB_MIXER1 && num == MXR_LAYER_GRP0) mxr_write(mdev, MXR1_GRAPHIC_BLANK(0), v); else if (sub_mxr == MXR_SUB_MIXER1 && num == MXR_LAYER_GRP1) mxr_write(mdev, MXR1_GRAPHIC_BLANK(1), v); #endif mxr_vsync_set_update(mdev, MXR_ENABLE); spin_unlock_irqrestore(&mdev->reg_slock, flags); }