int
pcscp_dma_intr(struct ncr53c9x_softc *sc)
{
struct pcscp_softc *esc = (struct pcscp_softc *)sc;
int trans, resid, i;
bus_dmamap_t dmap = esc->sc_xfermap;
int datain = esc->sc_datain;
u_int32_t dmastat;
char *p = NULL;
dmastat = READ_DMAREG(esc, DMA_STAT);
if (dmastat & DMASTAT_ERR) {
/* XXX not tested... */
WRITE_DMAREG(esc, DMA_CMD,
DMACMD_ABORT | (datain ? DMACMD_DIR : 0));
printf("%s: error: DMA error detected; Aborting.\n",
sc->sc_dev.dv_xname);
bus_dmamap_unload(esc->sc_dmat, dmap);
return -1;
}
if (dmastat & DMASTAT_ABT) {
/* XXX What should be done? */
printf("%s: dma_intr: DMA aborted.\n", sc->sc_dev.dv_xname);
WRITE_DMAREG(esc, DMA_CMD,
DMACMD_IDLE | (datain ? DMACMD_DIR : 0));
esc->sc_active = 0;
return 0;
}
#ifdef DIAGNOSTIC
/* This is an "assertion" :) */
if (esc->sc_active == 0)
panic("pcscp dmaintr: DMA wasn't active");
#endif
/* DMA has stopped */
esc->sc_active = 0;
if (esc->sc_dmasize == 0) {
/* A "Transfer Pad" operation completed */
NCR_DMA(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n",
PCSCP_READ_REG(esc, NCR_TCL) |
(PCSCP_READ_REG(esc, NCR_TCM) << 8),
PCSCP_READ_REG(esc, NCR_TCL),
PCSCP_READ_REG(esc, NCR_TCM)));
return 0;
}
resid = 0;
/*
* If a transfer onto the SCSI bus gets interrupted by the device
* (e.g. for a SAVEPOINTER message), the data in the FIFO counts
* as residual since the ESP counter registers get decremented as
* bytes are clocked into the FIFO.
*/
if (!datain &&
(resid = (PCSCP_READ_REG(esc, NCR_FFLAG) & NCRFIFO_FF)) != 0) {
NCR_DMA(("pcscp_dma_intr: empty esp FIFO of %d ", resid));
}
if ((sc->sc_espstat & NCRSTAT_TC) == 0) {
/*
* `Terminal count' is off, so read the residue
* out of the ESP counter registers.
*/
if (datain) {
resid = PCSCP_READ_REG(esc, NCR_FFLAG) & NCRFIFO_FF;
while (resid > 1)
resid =
PCSCP_READ_REG(esc, NCR_FFLAG) & NCRFIFO_FF;
WRITE_DMAREG(esc, DMA_CMD, DMACMD_BLAST | DMACMD_MDL |
(datain ? DMACMD_DIR : 0));
for (i = 0; i < 0x8000; i++) /* XXX 0x8000 ? */
if (READ_DMAREG(esc, DMA_STAT) & DMASTAT_BCMP)
break;
/* See the below comments... */
if (resid)
p = *esc->sc_dmaaddr;
}
resid += PCSCP_READ_REG(esc, NCR_TCL) |
(PCSCP_READ_REG(esc, NCR_TCM) << 8) |
(PCSCP_READ_REG(esc, NCR_TCH) << 16);
} else {
while ((dmastat & DMASTAT_DONE) == 0)
dmastat = READ_DMAREG(esc, DMA_STAT);
}
WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain ? DMACMD_DIR : 0));
/* sync MDL */
bus_dmamap_sync(esc->sc_dmat, esc->sc_mdldmap,
0, sizeof(u_int32_t) * dmap->dm_nsegs, BUS_DMASYNC_POSTWRITE);
/* sync transfer buffer */
bus_dmamap_sync(esc->sc_dmat, dmap, 0, dmap->dm_mapsize,
datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(esc->sc_dmat, dmap);
trans = esc->sc_dmasize - resid;
/*
* From the technical manual notes:
*
* `In some odd byte conditions, one residual byte will be left
* in the SCSI FIFO, and the FIFO flags will never count to 0.
* When this happens, the residual byte should be retrieved
* via PIO following completion of the BLAST operation.'
*/
if (p) {
p += trans;
*p = PCSCP_READ_REG(esc, NCR_FIFO);
trans++;
}
if (trans < 0) { /* transferred < 0 ? */
#if 0
/*
* This situation can happen in perfectly normal operation
* if the ESP is reselected while using DMA to select
* another target. As such, don't print the warning.
*/
printf("%s: xfer (%d) > req (%d)\n",
sc->sc_dev.dv_xname, trans, esc->sc_dmasize);
#endif
trans = esc->sc_dmasize;
}
NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n",
PCSCP_READ_REG(esc, NCR_TCL),
PCSCP_READ_REG(esc, NCR_TCM),
PCSCP_READ_REG(esc, NCR_TCH),
trans, resid));
*esc->sc_dmalen -= trans;
*esc->sc_dmaaddr += trans;
return 0;
}
/*
* Pseudo (chained) interrupt from the esp driver to kick the
* current running DMA transfer. I am replying on espintr() to
* pickup and clean errors for now
*
* return 1 if it was a DMA continue.
*/
int
espdmaintr(struct esp_softc *sc)
{
struct ncr53c9x_softc *nsc = (struct ncr53c9x_softc *)sc;
int trans, resid;
u_long csr = sc->sc_dma_direction;
/* This is an "assertion" :) */
if (sc->sc_dmaactive == 0)
panic("dmaintr: DMA wasn't active");
/* DMA has stopped */
dbdma_stop(sc->sc_dmareg);
bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap);
sc->sc_dmaactive = 0;
if (sc->sc_dmasize == 0) {
/* A "Transfer Pad" operation completed */
NCR_DMA(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n",
NCR_READ_REG(nsc, NCR_TCL) |
(NCR_READ_REG(nsc, NCR_TCM) << 8),
NCR_READ_REG(nsc, NCR_TCL),
NCR_READ_REG(nsc, NCR_TCM)));
return 0;
}
resid = 0;
/*
* If a transfer onto the SCSI bus gets interrupted by the device
* (e.g. for a SAVEPOINTER message), the data in the FIFO counts
* as residual since the ESP counter registers get decremented as
* bytes are clocked into the FIFO.
*/
if (!(csr & D_WRITE) &&
(resid = (NCR_READ_REG(nsc, NCR_FFLAG) & NCRFIFO_FF)) != 0) {
NCR_DMA(("dmaintr: empty esp FIFO of %d ", resid));
}
if ((nsc->sc_espstat & NCRSTAT_TC) == 0) {
/*
* `Terminal count' is off, so read the residue
* out of the ESP counter registers.
*/
resid += (NCR_READ_REG(nsc, NCR_TCL) |
(NCR_READ_REG(nsc, NCR_TCM) << 8) |
((nsc->sc_cfg2 & NCRCFG2_FE)
? (NCR_READ_REG(nsc, NCR_TCH) << 16) : 0));
if (resid == 0 && sc->sc_dmasize == 65536 &&
(nsc->sc_cfg2 & NCRCFG2_FE) == 0)
/* A transfer of 64K is encoded as `TCL=TCM=0' */
resid = 65536;
}
trans = sc->sc_dmasize - resid;
if (trans < 0) { /* transferred < 0 ? */
trans = sc->sc_dmasize;
}
NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n",
NCR_READ_REG(nsc, NCR_TCL), NCR_READ_REG(nsc, NCR_TCM),
(nsc->sc_cfg2 & NCRCFG2_FE) ? NCR_READ_REG(nsc, NCR_TCH) : 0,
trans, resid));
*sc->sc_dmalen -= trans;
*sc->sc_dmaaddr += trans;
return 0;
}
static int
esp_pci_dma_intr(struct ncr53c9x_softc *sc)
{
struct esp_pci_softc *esc = (struct esp_pci_softc *)sc;
bus_dma_tag_t xferdmat;
bus_dmamap_t xferdmam;
size_t dmasize;
int datain, i, resid, trans;
uint32_t dmastat;
char *p = NULL;
xferdmat = esc->sc_xferdmat;
xferdmam = esc->sc_xferdmam;
datain = esc->sc_datain;
dmastat = READ_DMAREG(esc, DMA_STAT);
if ((dmastat & DMASTAT_ERR) != 0) {
/* XXX not tested... */
WRITE_DMAREG(esc, DMA_CMD, DMACMD_ABORT | (datain != 0 ?
DMACMD_DIR : 0));
device_printf(esc->sc_dev, "DMA error detected; Aborting.\n");
bus_dmamap_sync(xferdmat, xferdmam, datain != 0 ?
BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(xferdmat, xferdmam);
return (-1);
}
if ((dmastat & DMASTAT_ABT) != 0) {
/* XXX what should be done? */
device_printf(esc->sc_dev, "DMA aborted.\n");
WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain != 0 ?
DMACMD_DIR : 0));
esc->sc_active = 0;
return (0);
}
KASSERT(esc->sc_active != 0, ("%s: DMA wasn't active", __func__));
/* DMA has stopped. */
esc->sc_active = 0;
dmasize = esc->sc_dmasize;
if (dmasize == 0) {
/* A "Transfer Pad" operation completed. */
NCR_DMA(("%s: discarded %d bytes (tcl=%d, tcm=%d)\n",
__func__, READ_ESPREG(esc, NCR_TCL) |
(READ_ESPREG(esc, NCR_TCM) << 8),
READ_ESPREG(esc, NCR_TCL), READ_ESPREG(esc, NCR_TCM)));
return (0);
}
resid = 0;
/*
* If a transfer onto the SCSI bus gets interrupted by the device
* (e.g. for a SAVEPOINTER message), the data in the FIFO counts
* as residual since the ESP counter registers get decremented as
* bytes are clocked into the FIFO.
*/
if (datain == 0 &&
(resid = (READ_ESPREG(esc, NCR_FFLAG) & NCRFIFO_FF)) != 0)
NCR_DMA(("%s: empty esp FIFO of %d ", __func__, resid));
if ((sc->sc_espstat & NCRSTAT_TC) == 0) {
/*
* "Terminal count" is off, so read the residue
* out of the ESP counter registers.
*/
if (datain != 0) {
resid = READ_ESPREG(esc, NCR_FFLAG) & NCRFIFO_FF;
while (resid > 1)
resid =
READ_ESPREG(esc, NCR_FFLAG) & NCRFIFO_FF;
WRITE_DMAREG(esc, DMA_CMD, DMACMD_BLAST | DMACMD_DIR);
for (i = 0; i < 0x8000; i++) /* XXX 0x8000 ? */
if ((READ_DMAREG(esc, DMA_STAT) &
DMASTAT_BCMP) != 0)
break;
/* See the below comments... */
if (resid != 0)
p = *esc->sc_dmaaddr;
}
resid += READ_ESPREG(esc, NCR_TCL) |
(READ_ESPREG(esc, NCR_TCM) << 8) |
(READ_ESPREG(esc, NCR_TCH) << 16);
} else
while ((dmastat & DMASTAT_DONE) == 0)
dmastat = READ_DMAREG(esc, DMA_STAT);
WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain != 0 ?
DMACMD_DIR : 0));
/* Sync the transfer buffer. */
bus_dmamap_sync(xferdmat, xferdmam, datain != 0 ?
BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(xferdmat, xferdmam);
trans = dmasize - resid;
/*
* From the technical manual notes:
*
* "In some odd byte conditions, one residual byte will be left
* in the SCSI FIFO, and the FIFO flags will never count to 0.
* When this happens, the residual byte should be retrieved
* via PIO following completion of the BLAST operation."
*/
if (p != NULL) {
p += trans;
*p = READ_ESPREG(esc, NCR_FIFO);
trans++;
}
if (trans < 0) { /* transferred < 0 ? */
#if 0
/*
* This situation can happen in perfectly normal operation
* if the ESP is reselected while using DMA to select
* another target. As such, don't print the warning.
*/
device_printf(dev, "xfer (%d) > req (%d)\n", trans, dmasize);
#endif
trans = dmasize;
}
NCR_DMA(("%s: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", __func__,
READ_ESPREG(esc, NCR_TCL), READ_ESPREG(esc, NCR_TCM),
READ_ESPREG(esc, NCR_TCH), trans, resid));
*esc->sc_dmalen -= trans;
*esc->sc_dmaaddr = (char *)*esc->sc_dmaaddr + trans;
return (0);
}
static int
asc_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len,
int datain, size_t *dmasize)
{
struct asc_softc *esc = (struct asc_softc *)sc;
paddr_t paddr;
size_t count, blocks;
int prime, err;
#ifdef DIAGNOSTIC
if (esc->sc_flags & DMA_ACTIVE) {
dma_status(sc);
panic("DMA active");
}
#endif
esc->sc_dmaaddr = addr;
esc->sc_dmalen = len;
esc->sc_dmasize = *dmasize;
esc->sc_flags = datain ? DMA_PULLUP : 0;
NCR_DMA(("asc_dma_setup va=%p len=%d datain=%d count=%d\n",
*addr, *len, datain, esc->sc_dmasize));
if (esc->sc_dmasize == 0)
return 0;
/* have dmamap for the transfering addresses */
if ((err=bus_dmamap_load(esc->sc_dmat, esc->sc_dmamap,
*esc->sc_dmaaddr, esc->sc_dmasize,
NULL /* kernel address */,
BUS_DMA_NOWAIT)) != 0)
panic("%s: bus_dmamap_load err=%d", sc->sc_dev.dv_xname, err);
esc->sc_flags |= DMA_MAPLOADED;
paddr = esc->sc_dmamap->dm_segs[0].ds_addr;
count = esc->sc_dmamap->dm_segs[0].ds_len;
prime = (u_int32_t)paddr & 0x3f;
blocks = (prime + count + 63) >> 6;
esc->dm_mode = (datain ? RB_DMA_WR : RB_DMA_RD);
/* Set transfer direction and disable DMA */
bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, esc->dm_mode);
/* Load DMA transfer address */
bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_LADDR,
paddr & ~0x3f);
/* Load number of blocks to DMA (1 block = 64 bytes) */
bus_space_write_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT, blocks);
/* If non block-aligned transfer prime FIFO manually */
if (prime) {
/* Enable DMA to prime the FIFO buffer */
bus_space_write_4(esc->sc_bst, esc->dm_bsh,
RAMBO_MODE, esc->dm_mode | RB_DMA_ENABLE);
if (esc->sc_flags & DMA_PULLUP) {
/* Read from NCR 53c94 controller*/
u_int16_t *p;
p = (u_int16_t *)((u_int32_t)*esc->sc_dmaaddr & ~0x3f);
bus_space_write_multi_2(esc->sc_bst, esc->dm_bsh,
RAMBO_FIFO, p, prime>>1);
} else
/* Write to NCR 53C94 controller */
while (prime > 0) {
