static void setup_i2c(unsigned int port_number) { static const iomux_v3_cfg_t i2c1_pads[] = { NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL), }; static const iomux_v3_cfg_t i2c2_pads[] = { NEW_PAD_CTRL(MX53_PAD_KEY_ROW3__I2C2_SDA, I2C_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_KEY_COL3__I2C2_SCL, I2C_PAD_CTRL), }; switch (port_number) { case 0: imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads)); break; case 1: imx_iomux_v3_setup_multiple_pads(i2c2_pads, ARRAY_SIZE(i2c2_pads)); break; default: printf("Warning: Wrong I2C port number\n"); break; } }
int board_mmc_init(bd_t *bis) { int ret; static const iomux_v3_cfg_t sd3_pads[] = { NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD, SD_CMD_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL), }; esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); imx_iomux_v3_setup_multiple_pads(sd3_pads, ARRAY_SIZE(sd3_pads)); ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]); if (ret) return ret; return 0; }
static void setup_iomux_i2c(void) { static const iomux_v3_cfg_t pads[] = { NEW_PAD_CTRL(MX53_PAD_EIM_D28__I2C1_SDA, I2C_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_EIM_D21__I2C1_SCL, I2C_PAD_CTRL), }; imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads)); }
static void setup_iomux_uart(void) { static const iomux_v3_cfg_t uart1_pads[] = { NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, UART_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, UART_PAD_CTRL), }; imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); }
static void setup_iomux_i2c(void) { static const iomux_v3_cfg_t i2c1_pads[] = { NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL), }; imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads)); }
static void setup_iomux_uart(void) { static const iomux_v3_cfg_t uart_pads[] = { NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL), }; imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); }
static void setup_iomux_i2c(void) { static const iomux_v3_cfg_t i2c_pads[] = { NEW_PAD_CTRL(MX53_PAD_EIM_D16__I2C2_SDA, I2C_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_EIM_EB2__I2C2_SCL, I2C_PAD_CTRL), }; imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads)); }
static void mx25pdk_uart1_init(void) { static const iomux_v3_cfg_t uart1_pads[] = { NEW_PAD_CTRL(MX25_PAD_UART1_RXD__UART1_RXD, UART1_IN_PAD_CTRL), NEW_PAD_CTRL(MX25_PAD_UART1_TXD__UART1_TXD, UART1_OUT_PAD_CTRL), NEW_PAD_CTRL(MX25_PAD_UART1_RTS__UART1_RTS, UART1_OUT_PAD_CTRL), NEW_PAD_CTRL(MX25_PAD_UART1_CTS__UART1_CTS, UART1_IN_PAD_CTRL), }; imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); }
static void setup_iomux_uart(void) { static const iomux_v3_cfg_t uart_pads[] = { MX51_PAD_UART1_RXD__UART1_RXD, MX51_PAD_UART1_TXD__UART1_TXD, NEW_PAD_CTRL(MX51_PAD_UART1_RTS__UART1_RTS, UART_PAD_CTRL), NEW_PAD_CTRL(MX51_PAD_UART1_CTS__UART1_CTS, UART_PAD_CTRL), }; imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); }
static void setup_iomux_spi(void) { static const iomux_v3_cfg_t spi_pads[] = { NEW_PAD_CTRL(MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, PAD_CTL_HYS | PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST), NEW_PAD_CTRL(MX51_PAD_CSPI1_MISO__ECSPI1_MISO, PAD_CTL_HYS | PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST), NEW_PAD_CTRL(MX51_PAD_CSPI1_SS1__ECSPI1_SS1, MX51_GPIO_PAD_CTRL), MX51_PAD_CSPI1_SS0__ECSPI1_SS0, NEW_PAD_CTRL(MX51_PAD_CSPI1_RDY__ECSPI1_RDY, MX51_PAD_CTRL_2), NEW_PAD_CTRL(MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, PAD_CTL_HYS | PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST), }; imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads)); }
static void setup_iomux_i2c(void) { static const iomux_v3_cfg_t i2c_pads[] = { NEW_PAD_CTRL(MX35_PAD_I2C1_CLK__I2C1_SCL, I2C_PAD_CTRL), NEW_PAD_CTRL(MX35_PAD_I2C1_DAT__I2C1_SDA, I2C_PAD_CTRL), NEW_PAD_CTRL(MX35_PAD_TX3_RX2__I2C3_SCL, I2C_PAD_CTRL), NEW_PAD_CTRL(MX35_PAD_TX2_RX3__I2C3_SDA, I2C_PAD_CTRL), }; imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads)); }
static void setup_iomux_pinheader(void) { static const iomux_v3_cfg_t pads[] = { NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__GPIO5_26, PAD_CTRL_UP), NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__GPIO5_27, PAD_CTRL_UP), NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, MX53_UART_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, MX53_UART_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_CSI0_DAT12__GPIO5_30, PAD_CTRL_UP), }; imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads)); }
int board_ehci_hcd_init(int port) { /* Set USBH1_STP to GPIO and toggle it */ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_USBH1_STP__GPIO1_27, MX51_USBH_PAD_CTRL)); gpio_direction_output(MX51EVK_USBH1_STP, 0); gpio_direction_output(MX51EVK_USB_PHY_RESET, 0); mdelay(10); gpio_set_value(MX51EVK_USBH1_STP, 1); /* Set back USBH1_STP to be function */ imx_iomux_v3_setup_pad(MX51_PAD_USBH1_STP__USBH1_STP); /* De-assert USB PHY RESETB */ gpio_set_value(MX51EVK_USB_PHY_RESET, 1); /* Drive USB_CLK_EN_B line low */ gpio_direction_output(MX51EVK_USB_CLK_EN_B, 0); /* Reset USB hub */ gpio_direction_output(MX51EVK_USBH1_HUB_RST, 0); mdelay(2); gpio_set_value(MX51EVK_USBH1_HUB_RST, 1); return 0; }
static void m53_set_clock(void) { int ret; const uint32_t ref_clk = MXC_HCLK; const uint32_t dramclk = 400; uint32_t cpuclk; imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0, PAD_CTL_DSE_HIGH | PAD_CTL_PKE)); gpio_direction_input(IMX_GPIO_NR(4, 0)); /* GPIO10 selects modules' CPU speed, 1 = 1200MHz ; 0 = 800MHz */ cpuclk = gpio_get_value(IMX_GPIO_NR(4, 0)) ? 1200 : 800; ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK); if (ret) printf("CPU: Switch CPU clock to %dMHz failed\n", cpuclk); ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK); if (ret) { printf("CPU: Switch peripheral clock to %dMHz failed\n", dramclk); } ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK); if (ret) printf("CPU: Switch DDR clock to %dMHz failed\n", dramclk); }
static void setup_iomux_enet(void) { static const iomux_v3_cfg_t enet0_pads[] = { NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKIN, ENET_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTC1__RMII0_MDIO, ENET_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTC0__RMII0_MDC, ENET_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTC2__RMII0_CRS_DV, ENET_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTC3__RMII0_RD1, ENET_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTC4__RMII0_RD0, ENET_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTC5__RMII0_RXER, ENET_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTC6__RMII0_TD1, ENET_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTC7__RMII0_TD0, ENET_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTC8__RMII0_TXEN, ENET_PAD_CTRL), }; imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads)); }
int board_mmc_getcd(struct mmc *mmc) { /* Set up the Card Detect pin. */ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX25_PAD_A15__GPIO_2_1, 0)); gpio_direction_input(CARD_DETECT); return !gpio_get_value(CARD_DETECT); }
static void setup_iomux_fec(void) { static const iomux_v3_cfg_t fec_pads[] = { NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO, PAD_CTL_HYS | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE | PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST), MX51_PAD_NANDF_CS3__FEC_MDC, NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2), NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2), NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2), MX51_PAD_NANDF_D9__FEC_RDATA0, MX51_PAD_NANDF_CS6__FEC_TDATA3, MX51_PAD_NANDF_CS5__FEC_TDATA2, MX51_PAD_NANDF_CS4__FEC_TDATA1, MX51_PAD_NANDF_D8__FEC_TDATA0, MX51_PAD_NANDF_CS7__FEC_TX_EN, MX51_PAD_NANDF_CS2__FEC_TX_ER, MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK, NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4), NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4), MX51_PAD_EIM_CS5__FEC_CRS, MX51_PAD_EIM_CS4__FEC_RX_ER, NEW_PAD_CTRL(MX51_PAD_NANDF_D11__FEC_RX_DV, MX51_PAD_CTRL_4), }; imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); }
static void setup_iomux_led(void) { static const iomux_v3_cfg_t pads[] = { NEW_PAD_CTRL(MX53_PAD_DISP0_DAT6__GPIO4_27, PAD_CTL_PUS_100K_DOWN), }; imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads)); }
int board_mmc_getcd(struct mmc *mmc) { struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; int ret; imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_0__GPIO1_0, NO_PAD_CTRL)); gpio_direction_input(IMX_GPIO_NR(1, 0)); imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6, NO_PAD_CTRL)); gpio_direction_input(IMX_GPIO_NR(1, 6)); if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) ret = !gpio_get_value(IMX_GPIO_NR(1, 0)); else ret = !gpio_get_value(IMX_GPIO_NR(1, 6)); return ret; }
int board_ehci_hcd_init(int port) { if (port == 0) { /* USB OTG PWRON */ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_4__GPIO1_4, PAD_CTL_PKE | PAD_CTL_DSE_HIGH)); gpio_direction_output(IMX_GPIO_NR(1, 4), 0); /* USB OTG Over Current */ imx_iomux_v3_setup_pad(MX53_PAD_GPIO_18__GPIO7_13); } else if (port == 1) { /* USB Host PWRON */ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_2__GPIO1_2, PAD_CTL_PKE | PAD_CTL_DSE_HIGH)); gpio_direction_output(IMX_GPIO_NR(1, 2), 0); /* USB Host Over Current */ imx_iomux_v3_setup_pad(MX53_PAD_GPIO_3__USBOH3_USBH1_OC); } return 0; }
static void setup_iomux_fec(void) { static const iomux_v3_cfg_t fec_pads[] = { NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE), NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH), NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1, PAD_CTL_HYS | PAD_CTL_PKE), NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0, PAD_CTL_HYS | PAD_CTL_PKE), NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH), NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH), NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH), NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK, PAD_CTL_HYS | PAD_CTL_PKE), NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER, PAD_CTL_HYS | PAD_CTL_PKE), NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV, PAD_CTL_HYS | PAD_CTL_PKE), }; imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); }
/* * Board specific initialization. */ static void __init mx51_babbage_init(void) { iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP; iomux_v3_cfg_t power_key = NEW_PAD_CTRL(MX51_PAD_EIM_A27__GPIO2_21, PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH); imx51_soc_init(); #if defined(CONFIG_CPU_FREQ_IMX) get_cpu_op = mx51_get_cpu_op; #endif imx51_babbage_common_init(); imx51_add_imx_uart(0, &uart_pdata); imx51_add_imx_uart(1, NULL); imx51_add_imx_uart(2, &uart_pdata); babbage_fec_reset(); imx51_add_fec(NULL); /* Set the PAD settings for the pwr key. */ mxc_iomux_v3_setup_pad(power_key); imx_add_gpio_keys(&imx_button_data); imx51_add_imx_i2c(0, &babbage_i2c_data); imx51_add_imx_i2c(1, &babbage_i2c_data); imx51_add_hsi2c(&babbage_hsi2c_data); if (otg_mode_host) imx51_add_mxc_ehci_otg(&dr_utmi_config); else { initialize_otg_port(NULL); imx51_add_fsl_usb2_udc(&usb_pdata); } gpio_usbh1_active(); imx51_add_mxc_ehci_hs(1, &usbh1_config); /* setback USBH1_STP to be function */ mxc_iomux_v3_setup_pad(usbh1stp); babbage_usbhub_reset(); imx51_add_sdhci_esdhc_imx(0, &mx51_babbage_sd1_data); imx51_add_sdhci_esdhc_imx(1, &mx51_babbage_sd2_data); spi_register_board_info(mx51_babbage_spi_board_info, ARRAY_SIZE(mx51_babbage_spi_board_info)); imx51_add_ecspi(0, &mx51_babbage_spi_pdata); imx51_add_imx2_wdt(0); }
void setup_iomux_lcd(void) { /* DI2_PIN15 */ imx_iomux_v3_setup_pad(MX51_PAD_DI_GP4__DI2_PIN15); /* Pad settings for DI2_DISP_CLK */ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK, PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_SLOW)); /* Turn on 3.3V voltage for LCD */ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_CSI2_D12__GPIO4_9, NO_PAD_CTRL)); gpio_direction_output(MX51EVK_LCD_3V3, 1); /* Turn on 5V voltage for LCD */ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_CSI2_D13__GPIO4_10, NO_PAD_CTRL)); gpio_direction_output(MX51EVK_LCD_5V, 1); /* Turn on GPIO backlight */ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_DI1_D1_CS__GPIO3_4, NO_PAD_CTRL)); gpio_direction_output(MX51EVK_LCD_BACKLIGHT, 1); }
int board_mmc_init(bd_t *bis) { static const iomux_v3_cfg_t sdhc1_pads[] = { NEW_PAD_CTRL(MX25_PAD_SD1_CMD__SD1_CMD, NO_PAD_CTRL), NEW_PAD_CTRL(MX25_PAD_SD1_CLK__SD1_CLK, NO_PAD_CTRL), NEW_PAD_CTRL(MX25_PAD_SD1_DATA0__SD1_DATA0, NO_PAD_CTRL), NEW_PAD_CTRL(MX25_PAD_SD1_DATA1__SD1_DATA1, NO_PAD_CTRL), NEW_PAD_CTRL(MX25_PAD_SD1_DATA2__SD1_DATA2, NO_PAD_CTRL), NEW_PAD_CTRL(MX25_PAD_SD1_DATA3__SD1_DATA3, NO_PAD_CTRL), }; imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads)); esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK); return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); }
static void mx25pdk_fec_init(void) { static const iomux_v3_cfg_t fec_pads[] = { MX25_PAD_FEC_TX_CLK__FEC_TX_CLK, MX25_PAD_FEC_RX_DV__FEC_RX_DV, MX25_PAD_FEC_RDATA0__FEC_RDATA0, NEW_PAD_CTRL(MX25_PAD_FEC_TDATA0__FEC_TDATA0, FEC_OUT_PAD_CTRL), NEW_PAD_CTRL(MX25_PAD_FEC_TX_EN__FEC_TX_EN, FEC_OUT_PAD_CTRL), NEW_PAD_CTRL(MX25_PAD_FEC_MDC__FEC_MDC, FEC_OUT_PAD_CTRL), MX25_PAD_FEC_MDIO__FEC_MDIO, MX25_PAD_FEC_RDATA1__FEC_RDATA1, NEW_PAD_CTRL(MX25_PAD_FEC_TDATA1__FEC_TDATA1, FEC_OUT_PAD_CTRL), NEW_PAD_CTRL(MX25_PAD_D12__GPIO_4_8, 0), /* FEC_RESET_B */ NEW_PAD_CTRL(MX25_PAD_A17__GPIO_2_3, 0), /* FEC_ENABLE_B */ }; static const iomux_v3_cfg_t i2c_pads[] = { NEW_PAD_CTRL(MX25_PAD_I2C1_CLK__I2C1_CLK, I2C_PAD_CTRL), NEW_PAD_CTRL(MX25_PAD_I2C1_DAT__I2C1_DAT, I2C_PAD_CTRL), }; imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); /* Assert RESET and ENABLE low */ gpio_direction_output(FEC_RESET_B, 0); gpio_direction_output(FEC_ENABLE_B, 0); udelay(10); /* Deassert RESET and ENABLE */ gpio_set_value(FEC_RESET_B, 1); gpio_set_value(FEC_ENABLE_B, 1); /* Setup I2C pins so that PMIC can turn on PHY supply */ imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads)); }
static void setup_usb_h1(void) { static const iomux_v3_cfg_t usb_h1_pads[] = { MX51_PAD_USBH1_CLK__USBH1_CLK, MX51_PAD_USBH1_DIR__USBH1_DIR, MX51_PAD_USBH1_STP__USBH1_STP, MX51_PAD_USBH1_NXT__USBH1_NXT, MX51_PAD_USBH1_DATA0__USBH1_DATA0, MX51_PAD_USBH1_DATA1__USBH1_DATA1, MX51_PAD_USBH1_DATA2__USBH1_DATA2, MX51_PAD_USBH1_DATA3__USBH1_DATA3, MX51_PAD_USBH1_DATA4__USBH1_DATA4, MX51_PAD_USBH1_DATA5__USBH1_DATA5, MX51_PAD_USBH1_DATA6__USBH1_DATA6, MX51_PAD_USBH1_DATA7__USBH1_DATA7, NEW_PAD_CTRL(MX51_PAD_GPIO1_7__GPIO1_7, 0), /* H1 hub reset */ MX51_PAD_EIM_D17__GPIO2_1, MX51_PAD_EIM_D21__GPIO2_5, /* PHY reset */ }; imx_iomux_v3_setup_multiple_pads(usb_h1_pads, ARRAY_SIZE(usb_h1_pads)); }
static void setup_iomux_sd(void) { static const iomux_v3_cfg_t pads[] = { NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, MX53_SDHC_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, MX53_SDHC_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, MX53_SDHC_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, MX53_SDHC_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, MX53_SDHC_PAD_CTRL), MX53_PAD_EIM_DA13__GPIO3_13, }; imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads)); }
int board_mmc_init(bd_t *bis) { static const iomux_v3_cfg_t esdhc1_pads[] = { NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL), }; esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); imx_iomux_v3_setup_multiple_pads( esdhc1_pads, ARRAY_SIZE(esdhc1_pads)); return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); }
int board_mmc_init(bd_t *bis) { static const iomux_v3_cfg_t sd1_pads[] = { NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL), MX53_PAD_EIM_DA13__GPIO3_13, MX53_PAD_EIM_EB3__GPIO2_31, /* SD power */ }; esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads)); /* GPIO 2_31 is SD power */ gpio_direction_output(IMX_GPIO_NR(2, 31), 0); return fsl_esdhc_initialize(bis, &esdhc_cfg); }
int board_mmc_init(bd_t *bis) { static const iomux_v3_cfg_t sd1_pads[] = { NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL), NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL), MX53_PAD_EIM_DA13__GPIO3_13, }; u32 index; int ret; esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) { switch (index) { case 0: imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads)); break; default: printf("Warning: you configured more ESDHC controller" "(%d) as supported by the board(1)\n", CONFIG_SYS_FSL_ESDHC_NUM); return -EINVAL; } ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]); if (ret) return ret; } return 0; }