t_stat mctl_wrreg (int32 val, int32 pa, int32 lnt)
{
int32 ofs;
ofs = NEXUS_GETOFS (pa); /* get offset */
switch (ofs) { /* case on offset */
case MCSR0_OF: /* CSR0 */
mcsr0 = mcsr0 & ~(MCSR0_RS & val);
break;
case MCSR1_OF: /* CSR1 */
mcsr1 = val & MCSR1_RW;
break;
case MCSR2_OF: /* CSR2 */
break;
default:
return SCPE_NXM;
}
if (DEBUG_PRI (mctl_dev, MCTL_DEB_RWR))
fprintf (sim_deb, ">>MCTL: reg %d write, value = %X\n", ofs, val);
return SCPE_OK;
}
t_stat mctl_rdreg (int32 *val, int32 pa, int32 lnt)
{
int32 ofs;
ofs = NEXUS_GETOFS (pa); /* get offset */
switch (ofs) { /* case on offset */
case MCSR0_OF: /* CSR0 */
*val = mcsr0;
break;
case MCSR1_OF: /* CSR1 */
*val = mcsr1;
break;
case MCSR2_OF: /* CSR2 */
*val = mcsr2 & ~MCSR2_MBZ;
break;
default:
return SCPE_NXM;
}
if (DEBUG_PRI (mctl_dev, MCTL_DEB_RRD))
fprintf (sim_deb, ">>MCTL: reg %d read, value = %X\n", ofs, *val);
return SCPE_OK;
}
t_stat uba_wrreg (int32 val, int32 pa, int32 lnt)
{
int32 idx, ofs, old_cr;
if ((pa & 3) || (lnt != L_LONG)) { /* unaligned or not lw? */
sim_printf (">>UBA: invalid adapter write mask, pa = %X, lnt = %d\r\n", pa, lnt);
sbi_set_errcnf (); /* err confirmation */
return SCPE_OK;
}
ofs = NEXUS_GETOFS (pa); /* get offset */
if (uba_aiip && (ofs != UBACNF_OF) && (ofs != UBADR_OF) &&
(ofs != UBACR_OF) && (ofs != UBASR_OF))
return SCPE_NXM;
if (ofs >= UBAMAP_OF) { /* map? */
idx = ofs - UBAMAP_OF;
if (idx >= UBA_NMAPR) /* valid? */
return SCPE_NXM;
uba_map[idx] = val & UBAMAP_WR;
if (DEBUG_PRI (uba_dev, UBA_DEB_MWR))
fprintf (sim_deb, ">>UBA: map %d write, value = %X\n", idx, val);
return SCPE_OK;
}
switch (ofs) { /* case on offset */
case UBACNF_OF: /* CNF */
uba_cnf = uba_cnf & ~(val & UBACNF_W1C); /* W1C bits */
uba_adap_clr_int (); /* possible clr int */
break;
case UBACR_OF: /* CR */
old_cr = uba_cr;
if (val & UBACR_ADINIT) { /* adapter init */
uba_reset (&uba_dev); /* reset adapter */
uba_aiip = 1; /* set init in prog */
uba_ubpdn (uba_aitime); /* power fail UB */
}
if ((val & UBACR_UPF) && !(old_cr & UBACR_UPF) /* Unibus power clear */
&& !sim_is_active (&uba_unit))
uba_ubpdn (uba_aitime + uba_uitime); /* power fail UB */
uba_cr = (uba_cr & ~UBACR_WR) | (val & UBACR_WR);
uba_adap_set_int (uba_cr & ~old_cr); /* possible int set */
uba_adap_clr_int (); /* possible int clr */
break;
case UBASR_OF: /* SR */
uba_sr = uba_sr & ~(val & UBASR_W1C); /* W1C bits */
uba_adap_clr_int (); /* possible clr int */
break;
case UBADR_OF: /* DR */
uba_dr = (uba_dr & ~UBADR_WR) | (val & UBADR_WR);
uba_cnf = uba_cnf & ~(val & UBACNF_W1C);
uba_adap_clr_int (); /* possible clr int */
break;
case UBABRSVR_OF + 0: case UBABRSVR_OF + 1: /* BRSVR */
case UBABRSVR_OF + 2: case UBABRSVR_OF + 3:
idx = ofs - UBABRSVR_OF;
uba_svr[idx] = val;
break;
case UBADPR_OF + 0: /* DPR */
break; /* direct */
case UBADPR_OF + 1:
case UBADPR_OF + 2: case UBADPR_OF + 3:
case UBADPR_OF + 4: case UBADPR_OF + 5:
case UBADPR_OF + 6: case UBADPR_OF + 7:
case UBADPR_OF + 8: case UBADPR_OF + 9:
case UBADPR_OF + 10: case UBADPR_OF + 11:
case UBADPR_OF + 12: case UBADPR_OF + 13:
case UBADPR_OF + 14: case UBADPR_OF + 15:
idx = ofs - UBADPR_OF;
uba_dpr[idx] = uba_dpr[idx] & ~(val & UBADPR_W1C);
break;
default:
return SCPE_NXM;
}
if (DEBUG_PRI (uba_dev, UBA_DEB_RWR))
fprintf (sim_deb, ">>UBA: reg %d write, value = %X\n", ofs, val);
return SCPE_OK;
}
t_stat uba_rdreg (int32 *val, int32 pa, int32 lnt)
{
int32 idx, ofs;
if ((pa & 3) || (lnt != L_LONG)) { /* unaligned or not lw? */
sim_printf (">>UBA: invalid adapter read mask, pa = %X, lnt = %d\r\n", pa, lnt);
sbi_set_errcnf (); /* err confirmation */
return SCPE_OK;
}
ofs = NEXUS_GETOFS (pa); /* get offset */
if (uba_aiip && (ofs != UBACNF_OF)&& (ofs != UBADR_OF)) /* init in prog? */
return SCPE_NXM; /* only cnf, dr */
if (ofs >= UBAMAP_OF) { /* map? */
idx = ofs - UBAMAP_OF;
if (idx >= UBA_NMAPR) /* valid? */
return SCPE_NXM;
*val = uba_map[idx] & UBAMAP_RD;
if (DEBUG_PRI (uba_dev, UBA_DEB_MRD))
fprintf (sim_deb, ">>UBA: map %d read, value = %X\n", idx, *val);
return SCPE_OK;
}
switch (ofs) { /* case on offset */
case UBACNF_OF: /* CNF */
*val = (uba_cnf & UBACNF_RD) | UBACNF_CODE;
break;
case UBACR_OF: /* CR */
*val = uba_cr & UBACR_RD;
break;
case UBASR_OF: /* SR */
*val = uba_sr & UBASR_RD;
break;
case UBADR_OF: /* DR */
*val = (uba_dr & UBADR_RD) | UBADR_MICOK |
((uba_cnf & UBADR_CNF_RD) | UBACNF_CODE);
break;
case UBAFMER_OF: case UBAFMER_OF1: /* FMER */
*val = uba_fmer & UBAFMER_RD;
break;
case UBAFUBAR_OF: case UBAFUBAR_OF1: /* FUBAR */
*val = uba_fubar & UBAFUBAR_RD;
break;
case UBABRSVR_OF + 0: case UBABRSVR_OF + 1: /* BRSVR */
case UBABRSVR_OF + 2: case UBABRSVR_OF + 3:
idx = ofs - UBABRSVR_OF;
*val = uba_svr[idx];
break;
case UBABRRVR_OF + 0: case UBABRRVR_OF + 1: /* BRRVR */
case UBABRRVR_OF + 2: case UBABRRVR_OF + 3:
idx = ofs - UBABRRVR_OF;
uba_rvr[idx] = uba_get_ubvector (idx);
*val = uba_rvr[idx];
break;
case UBADPR_OF + 0: /* DPR */
*val = 0; /* direct */
break;
case UBADPR_OF + 1:
case UBADPR_OF + 2: case UBADPR_OF + 3:
case UBADPR_OF + 4: case UBADPR_OF + 5:
case UBADPR_OF + 6: case UBADPR_OF + 7:
case UBADPR_OF + 8: case UBADPR_OF + 9:
case UBADPR_OF + 10: case UBADPR_OF + 11:
case UBADPR_OF + 12: case UBADPR_OF + 13:
case UBADPR_OF + 14: case UBADPR_OF + 15:
idx = ofs - UBADPR_OF;
*val = uba_dpr[idx] & UBADPR_RD;
break;
default:
return SCPE_NXM;
}
if (DEBUG_PRI (uba_dev, UBA_DEB_RRD))
fprintf (sim_deb, ">>UBA: reg %d read, value = %X\n", ofs, *val);
return SCPE_OK;
}
