/**
* @brief Gets Pending Interrupt (reads the pending register in the NVIC
* and returns the pending bit for the specified interrupt).
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
* @retval status: - 0 Interrupt status is not pending.
* - 1 Interrupt status is pending.
*/
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) {
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Return 1 if pending else 0 */
return NVIC_GetPendingIRQ(IRQn);
}
uint32_t vIRQ_GetPendingIRQ(uint32_t irqn)
{
if(__uvisor_mode == 0) {
return NVIC_GetPendingIRQ((IRQn_Type) irqn);
}
else {
return UVISOR_SVC(UVISOR_SVC_ID_IRQ_PEND_GET, "", irqn);
}
}
CU_TEST_END
static void event_decoder_suite_setup(void)
{
nrf_cunit_mock_call * p_mock_obj;
reset_test();
nrf_cunit_reset_mock();
// Verify the SWI2_IRQ is not set.
CU_ASSERT(NVIC_GetPendingIRQ(SWI2_IRQn) == 0);
nrf_cunit_expect_call_return((uint8_t *)"hci_transport_rx_pkt_consume", &p_mock_obj);
p_mock_obj->compare_rule[0] = COMPARE_ANY;
}
// ---------------------------------------------------------------------------
BOOL CPU_INTC_InterruptState(UINT32 Irq_Index)
{
// Return TRUE if interrupt status is pending.
return (BOOL)NVIC_GetPendingIRQ((IRQn_Type) Irq_Index);
}
/**
* @brief Gets Pending Interrupt (reads the pending register in the NVIC
* and returns the pending bit for the specified interrupt).
* @param IRQn External interrupt number
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h))
* @retval status: - 0 Interrupt status is not pending.
* - 1 Interrupt status is pending.
*/
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
/* Return 1 if pending else 0 */
return NVIC_GetPendingIRQ(IRQn);
}
/**
\brief Test case: TC_CoreFunc_EnDisIRQ
\details
Check expected behavior of interrupt related control functions:
- __disable_irq() and __enable_irq()
- NVIC_EnableIRQ, NVIC_DisableIRQ, and NVIC_GetEnableIRQ
- NVIC_SetPendingIRQ, NVIC_ClearPendingIRQ, and NVIC_GetPendingIRQ
- NVIC_GetActive (not on Cortex-M0/M0+)
*/
void TC_CoreFunc_EnDisIRQ (void)
{
// Globally disable all interrupt servicing
__disable_irq();
// Enable the interrupt
NVIC_EnableIRQ(WDT_IRQn);
ASSERT_TRUE(NVIC_GetEnableIRQ(WDT_IRQn) != 0U);
// Clear its pending state
NVIC_ClearPendingIRQ(WDT_IRQn);
ASSERT_TRUE(NVIC_GetPendingIRQ(WDT_IRQn) == 0U);
// Register test interrupt handler.
TST_IRQHandler = TC_CoreFunc_EnDisIRQIRQHandler;
irqTaken = 0U;
#if defined(__CORTEX_M) && (__CORTEX_M > 0)
irqActive = UINT32_MAX;
#endif
// Set the interrupt pending state
NVIC_SetPendingIRQ(WDT_IRQn);
for(uint32_t i = 10U; i > 0U; --i) {}
// Interrupt is not taken
ASSERT_TRUE(irqTaken == 0U);
ASSERT_TRUE(NVIC_GetPendingIRQ(WDT_IRQn) != 0U);
#if defined(__CORTEX_M) && (__CORTEX_M > 0)
ASSERT_TRUE(NVIC_GetActive(WDT_IRQn) == 0U);
#endif
// Globally enable interrupt servicing
__enable_irq();
for(uint32_t i = 10U; i > 0U; --i) {}
// Interrupt was taken
ASSERT_TRUE(irqTaken == 1U);
#if defined(__CORTEX_M) && (__CORTEX_M > 0)
ASSERT_TRUE(irqActive != 0U);
ASSERT_TRUE(NVIC_GetActive(WDT_IRQn) == 0U);
#endif
// Interrupt it not pending anymore.
ASSERT_TRUE(NVIC_GetPendingIRQ(WDT_IRQn) == 0U);
// Disable interrupt
NVIC_DisableIRQ(WDT_IRQn);
ASSERT_TRUE(NVIC_GetEnableIRQ(WDT_IRQn) == 0U);
// Set interrupt pending
NVIC_SetPendingIRQ(WDT_IRQn);
for(uint32_t i = 10U; i > 0U; --i) {}
// Interrupt is not taken again
ASSERT_TRUE(irqTaken == 1U);
ASSERT_TRUE(NVIC_GetPendingIRQ(WDT_IRQn) != 0U);
// Clear interrupt pending
NVIC_ClearPendingIRQ(WDT_IRQn);
for(uint32_t i = 10U; i > 0U; --i) {}
// Interrupt it not pending anymore.
ASSERT_TRUE(NVIC_GetPendingIRQ(WDT_IRQn) == 0U);
// Globally disable interrupt servicing
__disable_irq();
}
/*__STATIC_INLINE*/ uint32_t CMSIS_STUB_NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return NVIC_GetPendingIRQ(IRQn);
}
